KR100437607B1 - Refresh generation circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh generating circuit of a semiconductor memory device, and more particularly to a refresh generating circuit of a semiconductor memory device capable of automatically performing a refresh operation and controlling the refresh operation.

The refresh generation circuit of the semiconductor memory device of the present invention includes a refresh generation circuit unit configured to perform a refresh operation internally when a word line is enabled and accesses a memory cell, and controls the refresh operation by receiving an external control signal from an external pad. It characterized in that it comprises a refresh operation control unit capable of.

Description

Refresh generation circuit of semiconductor memory device {REFRESH GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh generation circuit of a semiconductor memory device, and more particularly, to a refresh generation circuit applicable to a semiconductor memory device which does not have a refresh command signal but needs refreshing internally.

In general, DRAM must be refreshed periodically to preserve internal data. Such refresh methods include auto refresh, self refresh, and the like. It can be controlled externally by making command signal with external clock.

In addition, in the case of a synchronous DRAM (SDRAM), a command signal of 'auto refresh' exists, and the self-refresh can be enabled by using an external clock signal.

However, in case of pseudo static random access memory (PSRAM) using DRAM, SRAM operation is required, and thus, a refresh command signal using a clock as well as a clock for refreshing externally cannot be generated. Also, you can't control it externally.

Accordingly, an object of the present invention devised to solve the above problems is to provide a refresh generating circuit of a semiconductor memory device capable of automatically performing a refresh operation internally and controlling the refresh operation.

1 is a block diagram of a refresh generation circuit of a semiconductor memory device of the present invention.

2 and 3 are circuit diagrams of the refresh generation circuit of the present invention.

4 is an operation timing diagram of FIGS. 2 and 3;

Explanation of symbols on the main parts of the drawings

10: refresh generating circuit part 12: enable part

15: oscillator section 16: ring oscillator

18: pulse generator 19: delay unit

20: refresh operation control unit

The refresh generation circuit of the semiconductor memory device of the present invention for achieving the above object is a refresh generation circuit unit for performing a refresh operation internally when the word line is enabled to access the memory cell, and receives an external control signal from an external pad It characterized in that it comprises a refresh operation control unit for controlling the refresh operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a refresh generation circuit of a semiconductor memory device according to the present invention, FIGS. 2 and 3 are detailed circuit diagrams of FIG. 1, and FIG. 4 is an operation timing diagram of the present invention.

First, as shown in FIG. 1, the refresh generation circuit of the present invention includes a refresh generation circuit unit 10 for performing a refresh operation internally when a word line is enabled to access a memory cell, and an external command signal from an external pad. It is composed of a refresh operation control unit 20 that can be applied to control the refresh operation. The refresh generation circuit of the present invention operates by the first internal signal and the second internal signal to perform the refresh operation in any one of the test mode and the normal mode by the internal control signal. Herein, when the power is turned on, the first internal signal rises to a certain level when the power is turned on to transition from the 'low' level to the 'high' level, and when the power is turned off, the first internal signal is turned on from the 'high' level to the 'low' level. The second internal signal is a low-active signal ROWACT for enabling a word line, and the internal control signal STMN has a 'low' level in the normal mode. In test mode, it is a signal with a 'high' level.

In such a refresh operation, when a refresh power is applied to access a memory cell, the refresh operation is automatically performed from this time to perform a self-refresh operation. However, if the refresh is operated without an external command, there is no way to control it, and since refresh occurs regardless of the external command, it is not known when the refresh occurs. Accordingly, the refresh operation control unit 20 that receives the external command signal TEST from the external pad is provided to generate the external control signal A capable of controlling the refresh operation.

As shown in FIG. 2, the refresh generation circuit unit 10 is operated by the power-up signal PWRUP and the ROWACT signal ROWACT, and is controlled by one of the test mode and the normal mode by the internal control signal STMN. In the enable unit 12 to perform the refresh operation in the mode state, the oscillator unit 15 for receiving a signal from the enable unit 12 and generating a level having a predetermined period, and in the oscillator unit 15 A pulse generation unit 18 may be generated by generating a pulse having the same period and receiving a signal from the refresh operation controller 20 to control the refresh operation from an external pad.

The enable unit 12 is commonly connected to the pull-up PMOS transistor P activated by the power-up signal PWRUP and the drain terminal of the pull-up PMOS transistor P, and activated by the low active signal ROWACT. A pull-down NMOS transistor N, a latch means LCT for latching a potential at the drain terminal, a first inverter IV1 for inverting the internal control signal STMN, a latch means LCT, and The NAND gate ND receives the signal from the first inverter IV1 and the second inverter IV2 inverts the signal from the NAND gate ND. Here, the latch means LCT is a form in which two inverters are fed back.

The oscillator unit 15 is composed of a ring oscillator 16 for receiving a signal from the second inverter IV2 and a third inverter IV3 for inverting the signal from the ring oscillator 16. The ring oscillator ( 16), as is known, consists of a NAND gate and two inverters in a feedback form.

The pulse generator 18 may include a first NAND gate ND1 for receiving signals from the first inverter IV1 and the oscillator unit 15, and a fourth inverter for inverting the signal from the refresh operation controller 20. IV4), a delay for a predetermined time delay while inverting the signals of the second NAND gate ND2 and the second NAND gate ND2 that receive signals from the first NAND gate ND1 and the fourth inverter IV4. The unit 19, the third NAND gate ND3 for receiving signals from the second NAND gate ND2 and the delay unit 19, and a fifth inverter for inverting the signals of the third NAND gate ND3 ( IV5). Here, the delay unit 19 is preferably composed of an odd number of inverters, three inverters in the figure.

Next, as shown in FIG. 3, the refresh operation controller 20 may include the fourth NAND gate ND4 for receiving the internal control signal STMN and the external control signal TEST for controlling the refresh operation from the external pad. And a sixth inverter IV6 that inverts the signal of the fourth NAND gate ND4.

The refresh generation circuit having the above configuration will be described with reference to the operation timing diagram shown in FIG.

First, for example, in the normal operation, the enable unit 12 maintains the 'high' level when the power-up signal PWRUP becomes 'high' level. The 'high' level is maintained at the 'high' level by the latch means LCT even when the first node nd1 is floating, and the second node nd2 is maintained at the 'low' level. The internal control signal STMN maintains the 'low' level during the normal operation so that the signal from the first inverter IV1 becomes the 'high' level so that the OSCEN signal input to the oscillator unit 15 becomes the second node ( nd2) receive the 'low' level of the level as it is. In this way, each node has the initial value as described above.

The low active signal ROWACT generates a pulse signal when the external command signal is a read or write operation signal. When the signal is enabled, the word line is enabled. When the signal is inputted in one pulse, the potential of the first node nd1 becomes 'low' level, and the OSCEN signal transitions to the 'high' level. The level is also maintained at the 'high' level until the power-up signal PWRUP becomes the 'low' level by the latch means LCT. This causes the OSCEN signal to remain 'high' level until the power is turned off in the first operation.

Then, when the OSCEN signal is at the 'low' level, the oscillator unit 15 outputs the OSC signal of the ring oscillator 16 to the 'low' level, and when the OSC signal is at the 'high' level, the OSC signal is toggled at a period Ts ( Toggle). At this time, the period Ts is determined by the number of inverters of the ring oscillator 16.

Next, when the OSC signal of the oscillator unit 15 is at the 'low' level, the pulse generator 18 is at the 'low' level, and the output SREF_REQ signal of the pulse generator 18 is' Low level. When the OSC signal transitions to the 'high' level, since the signal of the first inverter IV1 is the 'high' level, the third node nd3 transitions from the 'high' level to the 'low' level. Meanwhile, the A signal is a signal input from an external pad in test mode, and maintains a 'low' level in the normal mode. As a result, the fourth node nd4 transitions to the 'high' level. The fifth node nd5 transitions from the 'high' level to the 'low' level via the delay unit 19. Thus, the SREF_REQ signal is generated as a pulse having a width of d1. That is, when the OSC signal transitions from the 'low' level to the 'high' level, a SREF_REQ signal is generated with a pulse. The word line is enabled by the SREF_REQ signal to perform the refresh operation in the period of Ts.

Then, as described above, by using the refresh operation control unit 20 for controlling the refresh operation from the outside, it is possible to apply the refresh at the required timing. That is, when entering the mode for controlling the refresh, the internal control signal STMN transitions from the 'low' level to the 'high' level, and when the signal is at the 'low' level, the external control signal TEST is received from the external pad. The output A signal of the refresh operation control unit 20 becomes a 'low' level so as not to be inputted internally. This is a normal mode of operation to perform a refresh operation at a period Ts.

When the internal control signal STMN is at the 'high' level, the external control signal TEST is received as an input so that the output A signal of the refresh operation control unit 20 has the same voltage level as the external control signal TEST. It is to be an input of the generation unit 18.

When the test mode is entered, the internal control signal STMN transitions from the 'low' level to the 'high' level, and the output signal of the enable unit 12 by the first inverter IV1 is 'low' level. As a result, the OSCEN signal is generated at the 'low' level regardless of the second node nd2. The oscillator unit 15 receives the OSCEN signal and disables the ring oscillator 16 to generate the OSC signal to a 'low' level. This operation serves to disable the internal refresh operation. In the pulse generator 18, since the signal of the first inverter IV1 is at the 'low' level, the third node nd3 unconditionally becomes the 'high' level irrespective of the OSC signal to generate the A signal with the SREF_REQ pulse. It is used as a signal. Only when the A signal transitions from the 'low' level to the 'high' level, it generates a SREF_REQ signal pulse with a width of d1. That is, this causes the SREF_REQ signal pulse having a width of d1 to be generated only when the external control signal TEST transitions from 'low' to 'high' level.

Therefore, after entering the test mode, the refresh operation can be controlled by transitioning the external control signal from the 'low' level to the 'high' level to generate the SREF_REQ signal.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

According to the refresh generation circuit of the semiconductor memory device of the present invention described above, when there is no pin (PIN) for controlling the refresh from the outside, when the internal refresh is required using the DRAM cell, after entering the test mode, the external The refresh operation can be controlled by shifting the control signal TEST from the 'low' level to the 'high' level to generate the SREF_REQ signal.

Claims (7)

delete A refresh generation circuit unit which performs a refresh operation internally when a word line is enabled and accesses a memory cell; A refresh operation control unit which receives an external control signal from an external pad and controls the refresh operation in a specific mode, The refresh generation circuit unit An enable unit operated by the first internal signal and the second internal signal to perform the refresh operation in any one of test mode and normal mode by the internal control signal; An oscillator unit for receiving a signal from the enable unit and generating a level having a predetermined period; And a pulse generator for generating a refresh pulse having the same period according to the signal from the oscillator unit and receiving an external control signal from the refresh operation controller to control a refresh operation on an external pad in the specific mode. A refresh generating circuit of a semiconductor memory device. The method of claim 2, When the power is turned on, the first internal signal rises to a certain level when the power is turned on to transition from the 'low' level to the 'high' level, and when the power is turned off, the first internal signal is turned from the 'high' level to the 'low' level. Is a power-up signal that transitions to The second internal signal is a low active signal for enabling a word line. The internal control signal has a 'low' level in the normal mode and has a 'high' level in the test mode. The method of claim 3, The enable unit and the PMOS transistor is activated by the power-up signal, A pull-down NMOS transistor connected in common with the drain terminal of the pull-up PMOS transistor and activated by the low active signal; Latch means for latching a potential at the drain end; A first inverter for inverting the internal control signal; A NAND gate for receiving signals from the latch means and the first inverter, And a second inverter for inverting the signal from the NAND gate. The method of claim 4, wherein The oscillator unit includes a ring oscillator for receiving a signal from the second inverter, And a third inverter for inverting the signal from the ring oscillator. The method of claim 5, The pulse generator may include a first NAND gate configured to receive signals from the first inverter and the oscillator unit; A fourth inverter for inverting an external control signal from the refresh operation control unit; A second NAND gate configured to receive signals from the first NAND gate and the fourth inverter; A delay unit configured to delay a predetermined time while inverting the signal of the second NAND gate; A third NAND gate that receives signals from the second NAND gate and the delay unit, And a fifth inverter for inverting the signal of the third NAND gate. The method of claim 6, The refresh operation controller may include a fourth NAND gate configured to receive the internal control signal and the external control signal; And a sixth inverter for inverting the signal of the fourth NAND gate.