KR20010026902A - A circuit for controlling refresh of dynamic random access memory - Google Patents

Abstract

PURPOSE: A refresh control circuit within a dynamic random access memory device is provided to acquire stable voltage from a refresh-control signal by generating a switch control signal. CONSTITUTION: The circuit includes a switch-control signal generator(100) and a refresh-control signal generator(200). According to the input signals(TRAS,PCS) and an internal clock signal(PCLK), the switch-control signal generator(100) generates a switch-control signal(PRP) which activates in an activation period of the internal clock signal(PCLK). According to input signals(PCF,PWRCF) and the switch-control signal(PRP), the refresh-control signal generator(200) generates a refresh-control signal(PRFHB) for informing a refresh operation mode within the dynamic random access memory device. Thereby, the voltage of the refresh-control signal(PRFHB) can be stable by the switch-control signal(PRP), so that a refresh error is prevented.

Description

A CIRCUIT FOR CONTROLLING REFRESH OF DYNAMIC RANDOM ACCESS MEMORY}

The present invention relates to a DRAM device, and more particularly to a refresh control circuit of a DRAM device.

In general, a dynamic random access memory (DRAM) includes an array of memory cells (not shown) for storing data, a row address buffer (not shown) for accepting an m bit row address, and an n bit column address. A column address buffer (not shown), a row address buffer (not shown) for selecting a word line of a memory cell array, a column decoder (not shown) for selecting a column of memory cells to be accessed, and data A data input buffer (not shown) for reception and a data output buffer (not shown) for outputting data to the outside.

As is well known, one memory cell of a DRAM is composed of one select transistor and one data storing capacitor, thus increasing the integration density in the semiconductor substrate. DRAM is widely used as a semiconductor device suitable for use. However, in the DRAM, since charge leaks through the storage capacitor and the selection transistors, it is necessary to periodically perform a refresh to charge the charge.

Thus, unlike static random access memory (SRAM) and nonvolatile semiconductor memory (DRAM), the DRAM can periodically amplify the data stored in the memory cells by a sense amplifier (not shown) and rewrite the memory cells. It is further provided with a refresh circuit (not shown) which controls so that it may be. There are several well-known methods that are widely used to refresh DRAM cells. The following is a brief description of the main refresh methods.

First, in the RASB only refresh, that is, the "ROR" method, cells are activated by activating only a row address strobe (RASB) signal while a column address strobe (CASB) signal is maintained at a precharge level. The refresh operation for is performed. In such a refresh method, refresh addresses must be provided to the memory device externally for each refresh operation, and address buses connected to the memory device cannot be used for other purposes during each refresh operation.

Another refresh method is "CBR", that is, CASB before RASB refresh method. When memory cells are accessed during normal operations, externally applied 'RASB' signals are also activated prior to externally applied 'CASB' signals. However, in this 'CASB' method, the 'CASB' signal is activated before the 'RASB' signal to recognize the refresh mode. That is, before the 'RASB' signal is transitioned to the low level, the 'CASB' signal is first transitioned to the low level. This allows the refresh operations to be performed.

Referring to FIG. 1, a general refresh circuit includes a switch control signal generation circuit 10 and a refresh control signal generation circuit 20. The switch control signal generation circuit 10 includes an inverter 11, a switch circuit 12, a latch 13, a NAND gate 14, and an inverter 15. The refresh control signal generation circuit 20 is composed of an inversion circuit 21, a switch circuit 22, a latch circuit 23, an inverter 24, and a NAND gate 25.

Referring again to FIGS. 1 and 2, the refresh circuit generates a refresh control signal PRFHB informing the refresh operation of DRAM cells. First, the inverter 11 of the switch control signal generation circuit 10 inverts the signal TRAS from the outside. The switch circuit 12 selectively transmits the signal TRAS inverted by the inverter 11 to the latch 13 in response to the internal clock PCLK buffering the external clock CLK. The latch 13 latches the inverted signal TRASB transmitted through the switch circuit 12. The NAND gate 14 outputs a combined signal PRPB combining the signals PCLK, TRASB, and PCS. The inverter 15 inverts the combined signal PRPB from the NAND gate 14 and outputs it as a switch control signal PRP.

The refresh combination signal generation circuit 20 receives signals PCF and PWRCF from the outside and informs the refresh operation mode by the control of the switch control signal PRP from the switch control signal generation circuit 10. The refresh control signal PRFHB is output. The inversion circuit 21 of the refresh control circuit 20 inverts the signals PCF and PWRCF. The switch circuit 22 selectively transfers the signals PCF and PWRCF inverted by the inversion circuit 21 to the latch circuit 23 under the control of the switch control signal PRP. The latch circuit 23 latches signals PCFB and PWRCFB transmitted through the switch circuit 22. The inverter 24 inverts the signal PWRCFB from the latch circuit 23. The NAND gate 25 outputs the combined signal PRFHB combining the signal PCFB from the latch circuit 23 and the signal PWRCF from the inverter 24 as a refresh control signal PRFHB.

When the refresh control signal PRFHB of FIG. 2 transitions to the low level, it indicates the start of the refresh operation mode. However, since the refresh control signal PRFHB is generated by the control of the switch control signal PRP when the signals PCF and PWRCF are high and low levels, the switch control signal PRP is at a high level. When the logic level of one of the signals PCF and PWRCF transitions, the refresh control signal PWFHB transitions back to a high level as shown by the dotted line of FIG. 2, and thus the DRAM cells are not refreshed.

A semiconductor memory device such as a DRAM device should normally perform a normal read and write operation and various functions using the same. When the normal operation is being performed, the cell data must be written / read naturally, and when the command for notifying the refresh is performed from the outside is performed smoothly. However, as described above, when the refresh control signal PRFHB announces the execution of the refresh operation mode after the refresh command is input, if the levels of the signals PCF and PWRCF are varied, the normal refresh operation is not performed. Therefore, there is a problem that a malfunction of the DRAM device occurs.

Accordingly, it is an object of the present invention to provide a refresh control circuit which prevents a malfunction of a DRAM device.

1 is a circuit diagram showing a configuration of a general refresh control circuit;

2 is an operation timing diagram illustrating an operation of the refresh control circuit of FIG. 1;

3 is a circuit diagram showing a configuration of a refresh control circuit according to the present invention;

4 is an operation timing diagram illustrating an operation of the refresh control circuit of FIG. 3.

* Explanation of symbols on the main parts of the drawings

10. 100: switch control signal generating circuit

20, 200: refresh control signal generation circuit

(Configuration)

According to one aspect of the present invention for achieving the object as described above, the refresh control circuit of the DRAM device according to the present invention receives the first and second input signals informing the refresh operation mode, and has an internal clock having a predetermined frequency Switch control signal generating means for generating a switch control signal that is activated when the internal clock is activated in response to the internal clock; And a refresh control signal generation circuit for generating a refresh control signal combining third and fourth input signals informing the refresh operation mode in response to the switch control signal, wherein the switch control signal is before the internal clock is deactivated. It is activated during a predetermined predetermined interval of.

In this embodiment, the switch control circuit further comprises a first inverter for inverting the first input signal and a switch circuit for selectively transferring the first input signal inverted by the first inverter in response to the internal clock. And a latch for latching the first input signal transmitted through the switch circuit, and a first combination signal NAND combining the internal clock, the second input signal, and the first input signal stored in the latch. A first inverter, a second inverter for inverting the combined signal from the first NAND gate, a delay circuit for delaying the first combined signal inverted by the inverter, and the first inverted by the inverter. A second NAND outputting a second combined signal obtained by NAND combining the first combined signal and the first combined signal delayed by the delay circuit; Byte and the second by inverting the second combined signal from the NAND gate and a third inverter to output as said switch control signal.

In this embodiment, the delay circuit includes an odd number of inverters connected in series between the output terminal of the second inverter and the second NAND gate.

(Action)

By such a device, a malfunction of the refresh operation is prevented by generating a switch control signal that is activated during a predetermined predetermined period.

(Example)

Hereinafter, reference will be described in detail with reference to FIGS. 3 to 4 according to a preferred embodiment of the present invention.

Referring to FIG. 3, the refresh control circuit of the DRAM device according to the present invention includes a switch control signal generation circuit 100 and a refresh control signal generation circuit 200. The switch control signal generation circuit 100 receives the first and second input signals TRS and PCS from the outside and starts the internal clock PCLK from the time when the internal clock PCLK is activated in response to the internal clock PCLK. A switch control signal PRP is generated which is activated during a predetermined predetermined period before the clock PCLK is deactivated. The refresh control signal generation circuit 200 receives third and fourth input signals PCF and PWRCF from the outside and informs the refresh operation mode of the DRAM device in response to the switch control signal PRP. Generate signal PRFHB. As such, the switch control signal PRP is activated during a predetermined period of time from when the internal clock PCLK is activated to before the internal clock is deactivated, thereby changing the voltage level of the refresh control signal PRFHB. The malfunction of the refresh operation that is performed is prevented.

Referring to FIG. 3, a refresh control circuit of a DRAM according to the present invention includes a switch control signal generation circuit 100 and a refresh control signal generation circuit 200. The switch control signal generation circuit 100 includes an inverter 110, a switch circuit 120, a latch 130, a NAND gate 140, an inverter 150, a delay circuit 160, a NAND gate 170, and an inverter. And 180. The input terminal of the inverter 110 receives a signal TRAS, and the output terminal is connected to the transfer gate 122 of the switch circuit 120. The switch circuit 120 includes an inverter 121 and a transfer gate 122. The input terminal of the inverter 121 receives the internal clock PCLK, and the output terminal is connected to one gate of the transfer gate 122. The transfer gate 122 has current paths formed between the inverter 100 and the latch 130 and gates connected to input / output terminals of the inverter 121, respectively.

The latch 130 includes inverters 131 and 132 connected to the input / output terminals to cross each other. The first input terminal of the NAND gate 140 receives the internal clock PCLK, the second input terminal is connected to the output terminal of the inverter 131 in the latch 130, and the third input terminal is the signal PCS. And the output terminal is connected to the input terminal of the inverter 150. The input terminal of the inverter 150 is connected to the output terminal of the NAND gate 140, and the output terminal is commonly connected to the delay circuit 160 and the first input terminal of the NAND gate 170.

The delay circuit 160 includes inverters 161, 162, 163. The input terminal of the inverter 161 is connected to the output terminal of the inverter 150, and the output terminal is connected to the input terminal of the inverter 162. The input terminal of the inverter 162 is connected to the output terminal of the inverter 161, and the output terminal is connected to the input terminal of the inverter 163. The input terminal of the inverter 163 is connected to the output terminal of the inverter 162, and the output terminal is connected to the second input terminal of the NAND gate 170. The first input terminal of the NAND gate 170 is connected to the output terminal of the inverter 150, the second input terminal is connected to the output terminal of the inverter 163 of the delay circuit 160, and the output terminal is the inverter 180. Is connected to the input terminal. The input terminal of the inverter 180 is connected to the output terminal of the NAND gate 170, and the output terminal is connected to the switch circuit 220 of the refresh control signal generation circuit 200.

The refresh control signal generation circuit 200 includes an inversion circuit 210, a switch circuit 220, a latch circuit 230, an inverter 240, and a NAND gate 250. The inversion circuit 210 includes inverters 211 and 212. An input terminal of the inverter 211 receives a signal PCF, and an output terminal is connected to the transfer gate 221 of the switch circuit 220. An input terminal of the inverter 212 receives a signal PWRCF, and an output terminal is connected to the transfer gate 223 of the switch circuit 220. The switch circuit 220 includes transfer gates 221 and 223 and an inverter 222. The transfer gate 221 has a current path formed between the inverter 211 and the latch 230a and gates connected to input / output terminals of the inverter 222, respectively. An input terminal of the inverter 222 receives a signal PRP, and an output terminal is connected to one gates of the transfer gates 221 and 223. The transfer gate 223 has a current path formed between the inverter 212 and the latch 230b and gates connected to input / output terminals of the inverter 222, respectively.

The latch circuit 230 includes latches 230a and 230b. The latch 230a includes inverters I1 and I2 connected to the input / output terminals to cross each other. The latch 230b includes inverters I3 and I4 connected to the input / output terminals so that they cross each other. The input terminal of the inverter 240 is connected to the latch 230b, and the output terminal is connected to the second input terminal of the NAND gate 250. The first input terminal of the NAND gate 250 is connected to the latch 230a, the second input terminal is connected to the output terminal of the inverter 240, and the output terminal outputs the signal PRFHB.

3 and 4, the operation of the refresh control circuit of the DRAM device according to the present invention will be described.

Referring back to FIGS. 1 and 2, the refresh control circuit of the DRAM device according to the present invention is a switch control signal that is activated during a predetermined predetermined period from when the internal clock PCLK is activated and before the internal clock is deactivated. By generating (PRP), malfunction of the refresh operation in which the voltage level of the refresh control signal PRFHB is varied is prevented. The refresh control circuit outputs a refresh control signal PRFHB indicating a refresh operation mode among the operations of the DRAM device. The refresh control signal PRFHB is generated when the signals PRP and PCF are at a logic high period and the signal PWRCF is at a logic low period. The signals TRAS, PCS, PCF, and PWRCF are generated by a combination of a row address strobe signal RABB, a column address strobe signal CASB, a write enable signal WEB, and a chip select signal CSB. .

When the row address strobe signal (RASB), the column address strobe signal (CASB), and the chip select signal (CSB) are at the logic high level, and the write enable signal (WEB) is at the logic low level, the signal of the logic high level (TRAS) When is input, the inverter 110 inverts the logic level of the signal TRAS to a low level. Thereafter, when the logic high level internal clock PCLK is input, the logic low level signal TRAS is stored in the latch 130 through the transfer gate 122 of the switch circuit 120. The signal TRAS stored in the latch 130 is combined at the NAND gate 140 together with the internal clock PCLK and the signal PCS. In this case, since the internal clock PCLK and the signals PCS and TRAS have a logic high level, the output signal from the NAND gate 140 has a logic low level.

The inverter 150 inverts the output signal from the NAND gate 140 to a logic high level. The delay circuit 160 inverts and delays the output signal inverted by the inverter 150. The output signal of the logic high level inverted by the inverter 150 and the delay signal of the logic high level from the delay circuit 160 are combined in the NAND gate 170 and output as the output signal of the logic low level. The output signal from the NAND gate 170 is inverted by the inverter 180 and output as a switch control signal PRP. The output signal from the inverter 150 delayed and inverted by the delay circuit 160 is supplied to the NAND gate 170 after a predetermined delay time. As a result, the logic low level output signal from the NAND gate 170 transitions to the logic high level after a time corresponding to the delay time of the delay circuit 160.

Inverters 211 and 212 of the inverting circuit 210 in the refresh control signal generation circuit 200 may generate a logic high level signal PCF and a logic low level signal PWRCF, respectively, at a logic low level and a logic high level. Invert to At this time, the transfer gates 221 and 223 of the switch circuit 220 are turned on by the control of the logic high level switch control signal PRP, so that the logic low and logic high level signals PCF and PWRCF are applied. The latches 230a and 230b of the latch circuit 230 are latched. In addition, the logic low level signal PWRCF stored in the latch 230b is transitioned back to the logic high level by the inverter 240. The NAND gate 250 outputs a logic low level refresh control signal PRFHB obtained by NAND gating the logic high level signals PCF and PWRCF from the latch 230a.

As described above, the refresh control circuit of the DRAM device according to the present invention generates a switch control signal PRP that is activated during a predetermined predetermined period from when the internal clock PCLK is activated and before the internal clock is deactivated. The malfunction of the refresh operation in which the voltage level of the refresh control signal PRFHB is varied is prevented.

In the above, the refresh control circuit of the DRAM device according to the present invention has been shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications are possible without departing from the technical spirit of the present invention. .

As described above, malfunction of the DRAM device is prevented by generating a switch control signal that is activated for a predetermined period to prevent the refresh control signal from being changed.

Claims (3)

In the refresh control circuit of a DRAM device: Switch control signal generating means for receiving first and second input signals informing the refresh operation mode and generating a switch control signal that is activated when the internal clock is activated in response to an internal clock having a predetermined frequency; A refresh control signal generation circuit for generating a refresh control signal in combination with third and fourth input signals informing the refresh operation mode in response to the switch control signal, The switch control signal, And a predetermined period of time before the internal clock is deactivated. The method of claim 1, The switch control circuit, A first inverter for inverting the first input signal; A switch circuit for selectively transferring said first input signal inverted by said first inverter in response to said internal clock; A latch for latching the first input signal transmitted through the switch circuit; A first NAND gate outputting a first combined signal obtained by NAND combining the internal clock, the second input signal, and the first input signal stored in the latch; A second inverter for inverting the combined signal from the first NAND gate; A delay circuit for delaying the first combined signal inverted by the inverter; A second NAND gate outputting a second combined signal obtained by NAND combining the first combined signal inverted by the inverter and the first combined signal delayed by the delay circuit; And a third inverter for inverting the second combined signal from the second NAND gate and outputting the second combined signal as the switch control signal. The method of claim 2, The delay circuit, And an odd number of inverters connected in series between the output terminal of the second inverter and the second NAND gate.