KR100430582B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100430582B1 KR100430582B1 KR10-2001-0081499A KR20010081499A KR100430582B1 KR 100430582 B1 KR100430582 B1 KR 100430582B1 KR 20010081499 A KR20010081499 A KR 20010081499A KR 100430582 B1 KR100430582 B1 KR 100430582B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 이 방법은 반도체기판의 상부면과 하부면에 각각 순차적 적층된 패드절연막 및 하드 마스크막을 형성하고, 반도체 기판의 상부면에 형성된 하드 마스크막 및 패드절연막을 패터닝하고 반도체기판을 소정 깊이로 식각해서 트렌치를 형성하고, 반도체 기판의 트렌치를 절연물질로 갭필하고 그 표면을 평탄화하고, 반도체 기판의 상부면에 있는 하드 마스크막 및 패드절연막을 제거하여 반도체 기판에 트렌치 구조의 소자분리막을 형성하고, 반도체 기판 상부 전면에 희생 박막을 형성하고 이온 주입을 실시하고, 반도체 기판의 하부면에 있는 하드 마스크막을 제거한 후에 어닐링을 실시하여 반도체 기판내에 주입된 이온을 확산시켜 웰을 형성한다. 그러므로, 본 발명은 기판 하부면에 남아 있는 하드 마스크 질화막과 실리콘 기판의 인장력 차이로 인한 실리콘 격자 결함과 활성 영역의 보이드 생성을 미연에 방지할 수 있어 반도체 소자의 전기적인 특성 및 수율을 높일 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the method includes forming a pad insulating film and a hard mask film sequentially stacked on the top and bottom surfaces of a semiconductor substrate, and forming a hard mask film and a pad formed on the top surface of the semiconductor substrate. A trench is formed by patterning an insulating film and etching the semiconductor substrate to a predetermined depth, gap fill the trench of the semiconductor substrate with an insulating material, planarize its surface, and remove the hard mask film and the pad insulating film on the upper surface of the semiconductor substrate. A device isolation film having a trench structure is formed on the substrate, a sacrificial thin film is formed on the entire upper surface of the semiconductor substrate, ion implantation is performed, and after removal of the hard mask layer on the lower surface of the semiconductor substrate, annealing is performed to ions implanted in the semiconductor substrate. Diffusion to form wells. Therefore, the present invention can prevent the generation of voids in the active region and silicon lattice defects due to the difference in tensile force between the hard mask nitride film and the silicon substrate remaining on the lower surface of the substrate, thereby improving the electrical characteristics and yield of the semiconductor device. .
Description
본 발명은 반도체 제조 방법에 관한 것으로서, 특히 반도체 기판의 하부면에 있는 하드 마스크 질화막으로 인한 결함을 미연에 방지하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for manufacturing a semiconductor device that prevents defects due to a hard mask nitride film on a lower surface of a semiconductor substrate.
도 1 내지 도 5는 종래 기술에 의한 반도체 소자의 제조 방법을 설명하기 위한 공정 순서도이다.1 to 5 are process flowcharts illustrating a method for manufacturing a semiconductor device according to the prior art.
우선 도 1에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(10)에 패드절연막(12)과 하드 마스크막을 적층한다. 이때, 패드절연막(12)은 산화막이며 하드 마스크막은 질화막(14)과 TEOS(TetraEtyleOrthoSilicate)막(16)이 적층된 구조를 갖는데, 이들 패드절연막(12)과 하드 마스크용 질화막(14) 및 TEOS막(16)은 실리콘 기판(10)의 상부면(A)과 하부면(B)에 각각 형성된다. 그리고 실리콘 기판(10)의 상부면(A)에 있는 하드 마스크용 TEOS막(16) 및 질화막(14)을 패터닝하고 실리콘 기판(10)을 소정 깊이로 식각하여 트렌치(18)를 형성한다.First, as shown in FIG. 1, a pad insulating film 12 and a hard mask film are laminated on a silicon substrate 10 as a semiconductor substrate. At this time, the pad insulating film 12 is an oxide film and the hard mask film has a structure in which a nitride film 14 and a TEE (TetraEtyleOrthoSilicate) film 16 are stacked, and the pad insulating film 12, the hard mask nitride film 14 and the TEOS film are stacked. 16 is formed on the upper surface A and the lower surface B of the silicon substrate 10, respectively. In addition, the hard mask TEOS film 16 and the nitride film 14 on the upper surface A of the silicon substrate 10 are patterned, and the silicon substrate 10 is etched to a predetermined depth to form a trench 18.
도 2에 도시된 바와 같이, 트렌치(18)에 화학기상증착법(Chemical Vapor Deposition)으로 절연물질로서 TEOS막(20)을 갭필하여 증착한다. 그리고 화학기계적연마(Chemical Mechanical Polishing)를 실시하여 하드 마스크 질화막(14) 상부가 드러나도록 TEOS막(20, 16) 표면을 연마한다.As shown in FIG. 2, the trench 18 is deposited by gapfilling the TEOS film 20 as an insulating material by chemical vapor deposition. Then, the chemical mechanical polishing is performed to polish the surfaces of the TEOS films 20 and 16 so that the top of the hard mask nitride film 14 is exposed.
그리고 도 3에 도시된 바와 같이, 트렌치(18)에 갭필된 TEOS막(20)을 어닐링하여 밀도를 높이고 실리콘 기판(10) 상부면(A)의 하드 마스크 질화막(14)을 제거하고 세정 공정으로 패드절연막(12)을 제거한다. 이로 인해 실리콘 기판(10) 상부면(A)에는 소자의 활성 영역과 비활성 영역을 정의하는 STI형 소자분리막(20a)이 형성된다.As shown in FIG. 3, annealing of the TEOS film 20 gap-filled in the trench 18 increases the density, and removes the hard mask nitride film 14 of the upper surface A of the silicon substrate 10. The pad insulating film 12 is removed. As a result, an STI type device isolation layer 20a is formed on the upper surface A of the silicon substrate 10 to define active and inactive regions of the device.
그 다음 도 4에 도시된 바와 같이, 실리콘 기판(10) 상부 전면에 희생 박막으로서 산화막(22)을 성장시키고 P-웰(well) 또는 N-웰 이온 주입을 실시한다. 그리고 퍼니스에서 고온 어닐링을 실시하여 실리콘 기판(10)내에 주입된 이온을 확산시켜 P-웰(26) 또는 N-웰(28)을 형성한다.Then, as shown in FIG. 4, the oxide film 22 is grown as a sacrificial thin film on the upper surface of the silicon substrate 10 and P-well or N-well ion implantation is performed. The furnace is subjected to high temperature annealing to diffuse the ions implanted into the silicon substrate 10 to form the P-well 26 or the N-well 28.
그런데, 종래 기술은 반도체 제조 공정 중에서 웰의 이온 주입후에 고온의 어닐링을 진행하게 된다. 이때, 소자 분리막 제조 공정시 실리콘 기판(10)의 하부면(B)에 형성된 하드 마스크용 질화막(14)은 실리콘 기판(10)에 비해 인장력이 크다. 실리콘 기판(10)과 기판 하부면에 계속 남아있는 질화막(14) 사이에서 인장력 차이가 발생하게 되면, 웰을 위한 고온의 어닐링 공정에서 실리콘 기판 표면의 격자 결함을 유발하고 이 격자 결함은 활성 영역에 보이드(void)의 생성 원인으로 된다. 이와 같이, 실리콘 기판(10) 표면에 격자 결함 및 보이드가 생성될 경우 반도체 소자의 전기적인 특성 및 수율이 저하되는 문제점이 있었다.By the way, the prior art proceeds the high temperature annealing after the ion implantation of the well in the semiconductor manufacturing process. In this case, the nitride film 14 for a hard mask formed on the lower surface B of the silicon substrate 10 during the device isolation process may have a higher tensile force than that of the silicon substrate 10. If a tensile force difference occurs between the silicon substrate 10 and the nitride film 14 remaining on the bottom surface of the substrate, a lattice defect on the surface of the silicon substrate occurs in the high temperature annealing process for the well, and the lattice defects This causes the void to be generated. As such, when lattice defects and voids are formed on the surface of the silicon substrate 10, there is a problem in that electrical characteristics and yield of the semiconductor device are deteriorated.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 웰을 위한 어닐링 공정전 소자 분리막 제조 공정에서 실리콘 기판의 하부면에 형성된 하드 마스크 질화막을 제거함으로써 기판 하부면에 남아 있는 하드 마스크 질화막과 실리콘 기판의 인장력 차이로 인한 실리콘 격자 결함과 활성 영역의 보이드 생성을 미연에 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.An object of the present invention is to remove the hard mask nitride film and silicon remaining on the lower surface of the substrate by removing the hard mask nitride film formed on the lower surface of the silicon substrate in the device isolation film manufacturing process before the annealing process for the well to solve the problems of the prior art The present invention provides a method of manufacturing a semiconductor device capable of preventing a silicon lattice defect and void generation of an active region due to a difference in tensile force of a substrate.
이러한 목적을 달성하기 위하여 본 발명은 반도체기판에 트렌치 구조의 소자분리막 및 웰을 형성함에 있어서, 반도체기판의 상부면과 하부면에 각각 순차적 적층된 패드절연막 및 하드 마스크막을 형성하는 단계와, 반도체 기판의 상부면에 형성된 하드 마스크막 및 패드절연막을 패터닝하고 반도체기판을 소정 깊이로 식각해서 트렌치를 형성하는 단계와, 반도체 기판의 트렌치를 절연물질로 갭필하고 그 표면을 평탄화하는 단계와, 반도체 기판의 상부면에 있는 하드 마스크막 및 패드절연막을 제거하여 반도체 기판에 트렌치 구조의 소자분리막을 형성하는 단계와, 반도체 기판 상부 전면에 희생 박막을 형성하고 이온 주입을 실시하는 단계와, 반도체 기판의 하부면에 있는 하드 마스크막을 제거한 후에 어닐링을 실시하여 반도체 기판내에 주입된 이온을 확산시켜 웰을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of forming a device isolation film and a well having a trench structure in a semiconductor substrate, the method including forming a pad insulating film and a hard mask film sequentially stacked on the upper and lower surfaces of the semiconductor substrate, Patterning the hard mask film and the pad insulating film formed on the upper surface of the substrate and etching the semiconductor substrate to a predetermined depth to form a trench; gap filling the trench of the semiconductor substrate with an insulating material and planarizing the surface thereof; Removing the hard mask film and the pad insulating film on the upper surface to form a trench isolation device isolation layer on the semiconductor substrate, forming a sacrificial thin film on the upper surface of the semiconductor substrate and performing ion implantation, and a lower surface of the semiconductor substrate After removing the hard mask film on the semiconductor substrate, annealing is performed to Diffusing ions to form the wells.
도 1 내지 도 5는 종래 기술에 의한 반도체 소자의 제조 방법을 설명하기 위한 공정 순서도,1 to 5 are process flowcharts illustrating a method for manufacturing a semiconductor device according to the prior art;
도 6 내지 도 11은 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 순서도.6 to 11 are process flowcharts for explaining a method for manufacturing a semiconductor device according to the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 반도체 기판 102 : 패드절연막100 semiconductor substrate 102 pad insulating film
104 : 하드 마스크 질화막 106 : 하드 마스크 TEOS막104: hard mask nitride film 106: hard mask TEOS film
108 : 트렌치 110 : 갭필 절연물질108: trench 110: gap fill insulating material
110a : 소자 분리막 112 : 희생 박막110a: device isolation layer 112: sacrificial thin film
114 : N-웰 116 : P-웰114: N-well 116: P-well
A : 반도체 기판 상부면 B : 반도체 기판 하부면A: semiconductor substrate upper surface B: semiconductor substrate lower surface
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 6 내지 도 11은 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 순서도이다.6 to 11 are process flowcharts illustrating a method of manufacturing a semiconductor device according to the present invention.
도 6에 도시된 바와 같이, 반도체 기판으로서 실리콘 기판(100)에 패드절연막(102)과 하드 마스크막(104, 106)을 적층한다. 이때, 패드절연막(102)은 산화막이며 하드 마스크막은 질화막(104)과 TEOS막(106)이 적층된 구조를 갖는데, 이들 패드절연막(102)과 하드 마스크용 질화막(104) 및 TEOS막(106)은 실리콘 기판(100)의 상부면(A)과 하부면(B)에 각각 형성된다. 그리고 실리콘 기판(100)의 상부면(A)에 있는 하드 마스크용 TEOS막(106) 및 질화막(104)을 패터닝하고 실리콘 기판(100)을 소정 깊이로 식각하여 트렌치(108)를 형성한다.As shown in FIG. 6, the pad insulating film 102 and the hard mask films 104 and 106 are laminated on the silicon substrate 100 as a semiconductor substrate. In this case, the pad insulating film 102 is an oxide film and the hard mask film has a structure in which the nitride film 104 and the TEOS film 106 are laminated. The pad insulating film 102, the hard mask nitride film 104 and the TEOS film 106 are formed. Are formed on the upper surface A and the lower surface B of the silicon substrate 100, respectively. The trench 108 is formed by patterning the TEOS film 106 and the nitride film 104 for the hard mask on the upper surface A of the silicon substrate 100 and etching the silicon substrate 100 to a predetermined depth.
도 7에 도시된 바와 같이, 트렌치(108)에 화학기상증착법으로 절연물질로서TEOS막(110)을 갭필하여 증착한다. 그리고 화학기계적연마 공정을 실시하여 하드 마스크 질화막(104) 상부가 드러나도록 TEOS막(110, 106) 표면을 연마한다.As shown in FIG. 7, the trench 108 is deposited by gapfilling the TEOS film 110 as an insulating material by chemical vapor deposition. Then, the chemical mechanical polishing process is performed to polish the surfaces of the TEOS films 110 and 106 so that the top of the hard mask nitride film 104 is exposed.
이어서 도 8에 도시된 바와 같이, 트렌치(108)에 갭필된 TEOS막(20)을 어닐링하여 밀도를 높이고 실리콘 기판(100) 상부면(A)의 하드 마스크 질화막(104)을 제거하고 세정 공정으로 패드절연막(102)을 제거한다. 이로 인해 실리콘 기판(100) 상부면(A)에는 소자의 활성 영역과 비활성 영역을 정의하는 STI형 소자분리막(110a)이 형성된다.Subsequently, as shown in FIG. 8, the trench 108 is annealed with a gapfilled TEOS film 20 to increase the density, and the hard mask nitride film 104 of the upper surface A of the silicon substrate 100 is removed and then cleaned. The pad insulating film 102 is removed. As a result, an STI type device isolation layer 110a defining an active region and an inactive region of the device is formed on the upper surface A of the silicon substrate 100.
그 다음 도 9에 도시된 바와 같이, 실리콘 기판(100) 상부 전면에 희생 박막으로서 산화막(112)을 성장시키고 P-웰(well) 또는 N-웰 이온 주입을 실시한다.Next, as shown in FIG. 9, the oxide film 112 is grown as a sacrificial thin film on the upper surface of the silicon substrate 100 and P-well or N-well ion implantation is performed.
그런 다음 도 10에 도시된 바와 같이, 실리콘 기판(100)의 하부면(B)에 있는 하드 마스크용 TEOS막(106) 및 질화막(104)을 제거한다. 이때 식각 공정은 HF 케미컬로 30℃∼80℃에서 상부면 영향없이 하부면만 습식 식각을 진행한다.Then, as shown in FIG. 10, the TEOS film 106 and the nitride film 104 for a hard mask on the lower surface B of the silicon substrate 100 are removed. At this time, the etching process is wet etching only the lower surface without affecting the upper surface at 30 ℃ ~ 80 ℃ by HF chemical.
이에 따라, 본 발명은 실리콘 기판(100)의 하부면(B)에 형성된 하드 마스크용 질화막(104)이 습식 식각 공정으로 식각되어 없어지기 때문에 이후 웰의 이온 확산을 위한 어닐링 공정시 질화막(104)과 실리콘 기판(10) 사이의 인장력 차이로 인한 실리콘 기판 표면의 격자 결함 및 활성 영역의 보이드(void) 생성 원인을 제거한다.Accordingly, in the present invention, since the hard mask nitride film 104 formed on the lower surface B of the silicon substrate 100 is etched away by a wet etching process, the nitride film 104 is used during an annealing process for ion diffusion of the well. The lattice defects on the silicon substrate surface and the cause of void generation in the active region due to the difference in tensile force between the silicon substrate 10 and the silicon substrate 10 are eliminated.
그리고나서 도 11에 도시된 바와 같이, 퍼니스에서 고온 어닐링을 실시하여 실리콘 기판(100)내에 주입된 이온을 확산시켜 P-웰(114) 또는 N-웰(116)을 형성한다.Then, as shown in FIG. 11, high temperature annealing is performed in the furnace to diffuse the ions implanted into the silicon substrate 100 to form the P-well 114 or the N-well 116.
이상 설명한 바와 같이, 본 발명은 웰을 위한 어닐링 공정시 소자 분리막 제조 공정에 사용된 하드 마스크 질화막을 제거함으로써 기판 하부면에 남아 있는 하드 마스크 질화막과 실리콘 기판의 인장력 차이로 인한 실리콘 격자 결함과 활성 영역의 보이드 생성을 미연에 방지할 수 있어 반도체 소자의 전기적인 특성 및 수율을 높일 수 있다.As described above, the present invention provides a silicon lattice defect and an active region due to the difference in tensile force between the hard mask nitride film and the silicon substrate remaining on the lower surface of the substrate by removing the hard mask nitride film used in the device isolation fabrication process during the annealing process for the well. It is possible to prevent the generation of voids in advance, thereby increasing the electrical characteristics and yield of the semiconductor device.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5994852A (en) * | 1982-11-22 | 1984-05-31 | Nec Corp | Manufacture of semiconductor device |
| KR19980060898A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Method for manufacturing field oxide film of semiconductor device |
| KR19990030830A (en) * | 1997-10-06 | 1999-05-06 | 윤종용 | Manufacturing Method of Semiconductor Device |
| KR19990060842A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Field oxide film formation method of a semiconductor device |
| US5933748A (en) * | 1996-01-22 | 1999-08-03 | United Microelectronics Corp. | Shallow trench isolation process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5994852A (en) * | 1982-11-22 | 1984-05-31 | Nec Corp | Manufacture of semiconductor device |
| US5933748A (en) * | 1996-01-22 | 1999-08-03 | United Microelectronics Corp. | Shallow trench isolation process |
| KR19980060898A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Method for manufacturing field oxide film of semiconductor device |
| KR19990030830A (en) * | 1997-10-06 | 1999-05-06 | 윤종용 | Manufacturing Method of Semiconductor Device |
| KR19990060842A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Field oxide film formation method of a semiconductor device |
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