KR100567022B1 - Method for forming isolation layer of semiconductor device using trench technology - Google Patents

Method for forming isolation layer of semiconductor device using trench technology Download PDF

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KR100567022B1
KR100567022B1 KR1019990064492A KR19990064492A KR100567022B1 KR 100567022 B1 KR100567022 B1 KR 100567022B1 KR 1019990064492 A KR1019990064492 A KR 1019990064492A KR 19990064492 A KR19990064492 A KR 19990064492A KR 100567022 B1 KR100567022 B1 KR 100567022B1
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film
oxide film
trench
substrate
nitride film
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정이선
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON

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Abstract

반도체장치의 STI(shallow trench isolation)형 소자분리막 형성방법에 대해 개시한다. 본 발명의 소자분리 공정은 반도체기판에 패드 산화막 및 질화막을 순차적으로 적층하고 소자분리마스크를 이용한 사진 및 식각 공정을 진행하여 질화막과 패드 산화막을 패터닝한 후에 기판에 소정 깊이까지 트렌치를 형성하고, 기판의 트렌치 내측에 측벽 산화막 및 라이너 질화막을 순차 형성한 후에 750∼1200℃의 온도와 O2 분위기에서 어닐링 공정을 실시하여 라이너 질화막 표면을 질산화하고, 기판의 트렌치에 갭필 산화막을 채워넣고 이를 평탄화한 후에, 질화막을 제거하고 세정공정을 실시하여 기판내에 갭필 산화막으로 이루어진 소자분리막을 형성한다. 따라서, 본 발명은 고온의 열처리 공정을 실시하여 라이너질화막 표면을 갭필 산화막과의 결합이 우수한 질산화막(SiON)으로 형성함으로써 갭필 산화막 증착시 라이너 질화막의 블루잉-업 현상을 막고 균일하게 산화막을 증착할 수 있다.A method of forming a shallow trench isolation (STI) device isolation film in a semiconductor device is disclosed. In the device isolation process of the present invention, a pad oxide film and a nitride film are sequentially stacked on a semiconductor substrate, and a photolithography and etching process using a device isolation mask is performed to pattern the nitride film and the pad oxide film, and then trenches are formed in the substrate to a predetermined depth. After the sidewall oxide film and the liner nitride film are sequentially formed inside the trench of the trench, an annealing process is performed at a temperature of 750 to 1200 ° C. and an O 2 atmosphere to nitrate the surface of the liner nitride film, fill the gap fill oxide film in the trench of the substrate, and planarize it. The nitride film is removed and a cleaning process is performed to form a device isolation film made of a gap fill oxide film in the substrate. Accordingly, the present invention forms a surface of the liner nitride film as a nitride oxide (SiON) having excellent bonding with the gapfill oxide film by performing a high temperature heat treatment process, thereby preventing the bluing-up phenomenon of the liner nitride film during deposition of the gapfill oxide film and depositing the oxide film uniformly. can do.

Description

반도체소자의 트렌치를 이용한 소자분리막 형성방법{Method for forming isolation layer of semiconductor device using trench technology} Method for forming isolation layer of semiconductor device using trench technology             

도 1은 종래 기술에 의한 STI형 소자분리막 제조 공정 중에서 트렌치에 라이너 질화막을 형성한 후에 갭필 산화막을 형성할 경우 발생하는 라이너 질화막의 블루잉-업 현상을 나타낸 단면도, 1 is a cross-sectional view illustrating a bluing-up phenomenon of a liner nitride film generated when a gap fill oxide film is formed after forming a liner nitride film in a trench in a STI type isolation film manufacturing process according to the prior art;

도 2a 내지 도 2g는 본 발명에 따른 STI형 소자분리막 제조 공정을 설명하기 위한 공정 순서도. Figure 2a to 2g is a process flow chart for explaining the STI type device isolation film manufacturing process according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

100 : 실리콘기판 102 : 패드 산화막100 silicon substrate 102 pad oxide film

104 : 패드 질화막 106 : 트렌치104: pad nitride film 106: trench

108 : 희생 산화막 110: 측벽 산화막108: sacrificial oxide film 110: sidewall oxide film

112 : 라이너 산화막 114 : 갭필 산화막112 liner oxide film 114 gap fill oxide film

ISO : 소자분리막ISO: Device Separator

본 발명은 반도체장치의 소자분리막 형성방법에 관한 것으로서, 특히 고집적 반도체장치에서 소자분리 영역과 활성 영역을 정의하기 위한 STI형 소자분리막 제조 공정시 트렌치 내측의 라이너 질화막과 갭필 산화막의 접착을 개선할 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and in particular, to improve adhesion between a liner nitride film and a gapfill oxide film inside a trench during an STI type device isolation film manufacturing process for defining device isolation regions and active regions in a highly integrated semiconductor device. It is a skill.

최근 반도체장치의 제조기술의 발달과 메모리소자의 응용분야가 확장되어 감에 따라 대용량의 메모리소자의 개발이 진척되고 있는데, 이러한 메모리소자의 대용량화는 각 세대마다 2배로 진행하는 미세공정기술을 기본으로 한 메모리셀 연구에 의해 추진되어 오고 있다. 특히 소자간을 분리하는 소자분리막의 축소는 메모리소자의 미세화 기술에 있어서 중요한 항목중의 하나로 대두되고 있다.Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, the development of large-capacity memory devices has been progressed. It has been promoted by a memory cell study. In particular, the reduction of the device isolation film that separates the devices has emerged as one of the important items in the miniaturization technology of the memory device.

종래의 소자분리기술로는 반도체기판상에 두꺼운 산화막을 선택적으로 성장시켜 소자분리막을 형성하는 로커스(LOCal Oxidation of Silicon: 이하 LOCOS라 함) 기술이 최근까지 주종을 이루었다. 그러나, 상기 LOCOS 기술은 소자분리막의 측면확산 및 버즈비크(bird's beak)에 의해 소자분리영역의 폭을 감소시킬 수 없었다. 따라서, 소자설계치수가 서브미크론(submicron) 이하로 줄어드는 대용량의 메모리소자에 있어서는 LOCOS 기술의 적용이 불가능하기 때문에 새로운 소자분리 기술이 필요하게 되었다.Conventional device isolation technology has mainly been a LOCal Oxidation of Silicon (LOCOS) technology to selectively grow a thick oxide film on the semiconductor substrate to form a device isolation film. However, the LOCOS technique cannot reduce the width of the device isolation region due to side diffusion and bird's beak of the device isolation layer. Therefore, the LOCOS technology cannot be applied to a large-capacity memory device whose device design dimension is reduced to submicron or less, so a new device isolation technology is required.

이에 따라, 새로운 소자분리기술의 필요성과 식각(etching) 기술의 발달로 반도체기판에 폭 1Å이하, 깊이가 수십 내지 수백Å 정도의 트렌치를 형성하여 소자간을 전기적으로 분리할 수 있는 트렌치(trench) 구조의 소자분리 기술이 나오게 되었다. 이 트렌치를 이용한 소자분리기술은 종래의 LOCOS 기술에 비해 80%에 가까운 소자분리영역의 축소가 가능해졌다.As a result, a trench capable of electrically separating devices by forming trenches having a width of about 1Å or less and a depth of several tens to hundreds of Å on a semiconductor substrate due to the necessity of a new device isolation technology and the development of etching technology. Device isolation technology has emerged. The device isolation technology using this trench can reduce the device isolation region by nearly 80% compared to the conventional LOCOS technology.

더욱이, 최근에는 웨이퍼기판에 가해지는 스트레스를 크게 줄이면서 트렌치 소자분리막의 문제점을 개선한 STI(Shallow Trench Isolation) 공정이 등장하게 되었다. 즉, STI 공정은 반도체기판에 일정한 깊이를 갖는 트렌치를 형성하고 이 트렌치에 화학기상증착법으로 산화막을 증착하고서 화학적기계적연마(Chemical Mechanical Polishing) 공정으로 불필요한 산화막을 식각하여 소자분리막을 형성하는 기술이다.Moreover, recently, the STI (Shallow Trench Isolation) process, which greatly reduces the stress applied to the wafer substrate and improves the problem of the trench isolation layer, has emerged. In other words, the STI process is a technique of forming a device isolation film by forming a trench having a predetermined depth in a semiconductor substrate, depositing an oxide film on the trench by chemical vapor deposition, and etching an unnecessary oxide film by a chemical mechanical polishing process.

그러나, STI 공정은 접합 누설 전류 특성이 양호해지도록 트렌치 내부면에 존재하는 식각 손상을 제거해야만 한다. 기판내의 트렌치 식각시 발생되는 손상을 보상하면서 안정적인 식각 표면과 소자 분리막간 계면의 프로파일을 얻기 위해서는 대개 두 번의 고온 산화 공정을 실시하게 한다. 즉, 1차로 산화 공정을 실시하여 기판의 트렌치에 희생 산화막을 형성하고 이를 제거한 후에 다시 2차로 산화 공정을 실시하여 측벽 산화막을 형성하여 트렌치 내부의 기판 표면에 있는 식각 손상을 보상해준다.However, the STI process must remove the etch damage present on the inner surface of the trench to improve the junction leakage current characteristics. In order to compensate for the damage generated during the trench etching in the substrate and to obtain a profile of the interface between the etching surface and the device isolation layer, two high temperature oxidation processes are usually performed. That is, the sacrificial oxide film is formed in the trench of the substrate by first oxidizing and removing the sacrificial oxide film, and then the second oxidation process is performed again to form the sidewall oxide film to compensate for the etching damage on the substrate surface inside the trench.

도 1은 종래 기술에 의한 STI형 소자분리막 제조 공정 중에서 트렌치에 라이너 질화막을 형성한 후에 갭필 산화막을 형성할 경우 발생하는 라이너 질화막의 블루잉-업 현상을 나타낸 단면도이다.FIG. 1 is a cross-sectional view illustrating a bluing-up phenomenon of a liner nitride film generated when a gap fill oxide film is formed after forming a liner nitride film in a trench in the STI type isolation film manufacturing process according to the prior art.

이를 참조하여 종래 기술의 STI형 소자분리막 제조 공정을 설명한다.Referring to this, the manufacturing process of the STI type device isolation film of the prior art will be described.

우선, 반도체기판으로서 실리콘기판(10) 상부에 패드산화막(12)을 형성하고, 그 위에 질화막(14)을 적층한다. 소자분리 마스크를 이용한 사진 및 식각 공정으로 질화막(14) 및 패드 산화막(12)을 패터닝하고 패터닝된 막에 의해 노출된 기판을 식각하여 소정 깊이의 트렌치를 형성한다. First, a pad oxide film 12 is formed over a silicon substrate 10 as a semiconductor substrate, and a nitride film 14 is stacked thereon. The nitride layer 14 and the pad oxide layer 12 are patterned by a photolithography and an etching process using a device isolation mask, and the substrate exposed by the patterned layer is etched to form trenches having a predetermined depth.

그리고, 트렌치 식각 손상을 보상하기 위하여 트렌치내에 희생 산화막을 150∼200Å정도 형성시킨 후에 성장된 희생 산화막을 제거한다. 그 다음, 트렌치 내측에 측벽 산화막(16)을 150∼200Å정도 성장시킨다. In order to compensate for the trench etch damage, the sacrificial oxide film formed after the formation of the sacrificial oxide film in the trench is about 150 to 200 占 퐉 and the grown sacrificial oxide film is removed. Next, the sidewall oxide film 16 is grown to about 150 to 200 ∼ inside the trench.

그리고, 트렌치 내부를 절연막으로 채우기전에 보이드 발생을 억제하기 위하여 기판 전면에 라이너 질화막(18)을 증착한다.The liner nitride film 18 is deposited on the entire surface of the substrate in order to suppress the generation of voids before the inside of the trench is filled with the insulating film.

그 다음, 고밀도 플라즈마(High Density Plasma) 방법을 이용하여 트렌치 내부를 갭필 산화막으로 완전히 매립하고, 질화막(14)을 식각 정지막으로 삼아 화학적 기계적 연마공정으로 상기 갭필 산화막(20)을 평탄화한다. 그리고, 질화막을 제거하고 세정 공정을 실시하면 기판의 트렌치에 갭필 산화막(20)이 매립된 소자분리막이 형성된다.Then, the gap fill oxide 20 is completely filled with a gap fill oxide film using a high density plasma method, and the nitride fill film 14 is used as an etch stop film to planarize the gap fill oxide film 20 by a chemical mechanical polishing process. When the nitride film is removed and the cleaning process is performed, an isolation layer in which the gap fill oxide film 20 is embedded in the trench of the substrate is formed.

그러나, 상기와 같은 STI형 소자분리공정에 있어서, 증착 특성이 우수한 고밀도 플라즈마 방식으로 갭필 산화막 증착시 압축 응력이 약 220Mpa 정도로 크게 걸리게 된다. 이렇게 응력이 크게 걸리더라도 트렌치내에 형성된 라이너 질화막(18)에 의해 다음과 같은 이점이 있다.However, in the STI type device separation process as described above, the compressive stress of the gap fill oxide film is largely about 220 Mpa due to the high density plasma method having excellent deposition characteristics. In this way, even if the stress is large, the liner nitride film 18 formed in the trench has the following advantages.

즉, 고밀도 플라즈마의 갭필 산화막 증착시 실리콘산화막에 걸리는 응력은 인장 응력이 걸리고 질화막에는 그 반대의 응력이 걸리기 때문에 라이너 질화막(18)은 응력을 약 10Mpa정도 감소시키는 역할을 한다. 그리고, 이후 콘택 식각시 소자분리막의 라이너 질화막이 마스킹 역할을 하기 때문에 소자분리막 가장자리의 식각 손실을 줄여 접합 누설을 방지할 수 있다.That is, since the stress applied to the silicon oxide film during the deposition of the gap fill oxide film of the high density plasma is subjected to the tensile stress and the opposite stress to the nitride film, the liner nitride film 18 serves to reduce the stress by about 10 MPa. In addition, since the liner nitride layer of the device isolation layer acts as a mask during the contact etching process, it is possible to reduce the etch loss of the edge of the device isolation layer to prevent the junction leakage.

하지만, 라이너 질화막(18)은 이러한 장점에도 불구하고 고밀도 플라즈마 방식의 갭필 산화막 증착시 질화막(18)과 갭필 산화막(20)의 화학적 결함이 약해 도 1에서와 같이 라이너 질화막(18)의 블루잉-업(blowing-up) 현상(b)을 유발하게 된다. 이러한 블루잉-업 현상은 갭필 산화막(20)의 증착이 불균일하게 되어 결국 소자분리막의 폭이 감소되므로 소자의 수율이 떨어지는 문제점이 있었다.However, the liner nitride film 18 has a weak chemical defect between the nitride film 18 and the gap fill oxide film 20 in the deposition of a high density plasma type gap fill oxide film despite the above-mentioned advantages. It causes a blowing-up phenomenon (b). This bluing-up phenomenon has a problem in that the yield of the device is lowered because the deposition of the gap fill oxide film 20 becomes uneven and the width of the device isolation film is reduced.

본 발명의 목적은 상기 종래기술의 문제점을 해결하기 위하여 갭필 산화막을 증착하기전에 라이너 질화막이 형성된 기판에 고온의 열처리 공정을 실시하여 라이너질화막 표면을 갭필 산화막과의 결합이 우수한 질산화막(SiON)으로 형성함으로써 갭필 산화막 증착시 라이너 질화막의 블루잉-업 현상을 막고 균일하게 산화막을 증착할 수 있어 소자분리공정의 수율을 높일 수 있는 반도체소자의 트렌치를 이용한 소자분리막 형성방법을 제공하는데 있다.
An object of the present invention is to perform a high temperature heat treatment process on a substrate on which a liner nitride film is formed before depositing the gap fill oxide film in order to solve the problems of the prior art. The present invention provides a device isolation film forming method using a trench of a semiconductor device that can prevent the bluing-up phenomenon of the liner nitride film and uniformly deposit the oxide film when the gap fill oxide film is deposited.

상기 목적을 달성하기 위해 본 발명은 반도체기판에 소자의 활성 영역 및 분 리 영역을 정의하기 위한 트렌치 구조의 소자분리막을 형성함에 있어서, 반도체기판에 패드 산화막 및 질화막을 순차적으로 적층하는 단계와, 소자분리마스크를 이용한 사진 및 식각 공정을 진행하여 상기 질화막과 패드 산화막을 패터닝한 후에 기판에 소정 깊이까지 트렌치를 형성하는 단계와, 기판의 트렌치 내측에 측벽 산화막을 형성하는 단계와, 측벽산화막이 형성된 기판 전면에 라이너 질화막을 형성하는 단계와, 라이너 질화막이 형성된 기판에 750∼1200℃의 온도와 O2 분위기에서 어닐링 공정을 실시하여 상기 라이너 질화막 표면을 질산화하는 단계와, 기판의 트렌치에 갭필 산화막을 채워넣고 이를 평탄화하는 단계와, 질화막을 제거하고 세정공정을 실시하여 기판내에 갭필 산화막으로 이루어진 소자분리막을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for forming a device isolation film having a trench structure for defining an active region and an isolation region of a device on a semiconductor substrate, the method comprising sequentially depositing a pad oxide film and a nitride film on the semiconductor substrate, Forming a trench to a predetermined depth in the substrate after patterning the nitride layer and the pad oxide layer by performing a photolithography and an etching process using a separation mask; forming a sidewall oxide layer inside the trench of the substrate; Forming a liner nitride film on the entire surface, performing an annealing process on the substrate on which the liner nitride film is formed at a temperature of 750 to 1200 ° C. in an O 2 atmosphere, and nitrifying the surface of the liner nitride film, and filling a gap fill oxide film in the trench of the substrate Inserting and planarizing the substrate, removing the nitride film, and performing a cleaning process to Forming a device isolation film made of a gapfill oxide film therein.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따른 STI형 소자분리막 제조 공정을 설명하기 위한 공정 순서도로서, 이를 참조하면 본 발명의 소자분리막 제조 방법은 다음과 같다.2A to 2G are process flow charts for explaining the STI type device isolation film manufacturing process according to the present invention. Referring to this, the device isolation film manufacturing method of the present invention is as follows.

우선, 도 2a에 도시된 바와 같이, 실리콘기판(100)에 얇은 패드 산화막(102)과 두꺼운 질화막(104)을 순차적으로 적층한다. 그리고, 소자분리마스크를 이용한 사진 및 식각 공정을 진행하여 질화막(104) 및 패드 산화막(102)을 패터닝하고, 패 터닝된 막에 의해 노출된 기판(100)내에 소정 깊이의 트렌치(106)를 형성한다. 이때, 트렌치(106) 식각 깊이는 적용 디바이스의 디자인 룰에 따라 차이가 있으나 약 2000∼4000Å정도로 한다.First, as shown in FIG. 2A, a thin pad oxide film 102 and a thick nitride film 104 are sequentially stacked on the silicon substrate 100. Then, the photolithography and etching processes using the device isolation mask are performed to pattern the nitride film 104 and the pad oxide film 102, and the trenches 106 having a predetermined depth are formed in the substrate 100 exposed by the patterned film. do. At this time, the trench 106 etching depth is different depending on the design rules of the application device is about 2000 ~ 4000Å.

그 다음, 기판의 트렌치 내측에 트렌치 식각 손상을 보상하기 위하여 희생 산화막을 성장시킨 후에 상기 희생 산화막을 제거한다.Next, the sacrificial oxide film is removed after the sacrificial oxide film is grown inside the trench of the substrate to compensate for the trench etching damage.

그 다음, 도 2b 및 도 2c에 도시된 바와 같이, 트렌치(106) 내측에 측벽 산화막(108)을 150∼200Å정도 성장시킨다. 그리고, 트렌치 내부를 절연막으로 채우기전에 보이드 발생을 억제하기 위하여 기판 전면에 라이너 질화막(110)을 증착한다. 이때, 라이너 질화막(110)의 두께는 후속 공정의 스트레스를 완화시키기 위하여 30∼500Å정도로 한다. Next, as shown in FIGS. 2B and 2C, the sidewall oxide film 108 is grown in the trench 106 by about 150 to 200 Å. The liner nitride film 110 is deposited on the entire surface of the substrate to suppress the generation of voids before the inside of the trench is filled with the insulating film. At this time, the thickness of the liner nitride film 110 is about 30 to 500 kPa in order to relieve the stress of the subsequent process.

그 다음, 도 2d에 도시된 바와 같이, 고밀도 플라즈마(High Density Plasma) 방법을 이용하여 트렌치 내부를 갭필 산화막으로 매립하기 전에, 750∼1200℃의 온도와 O2 분위기에서 어닐링 공정을 실시하여 라이너 질화막(110) 표면을 질산화한다. 여기서, 어닐링 공정은 급속 열처리 방식(rapid thermal anneal)을 이용하되 1∼5분 동안 실시하거나, 또는 전기로(furnace)에서 실시할 경우 20∼200분 동안 실시한다. 바람직하게는 어닐링 공정의 적정 온도는 900∼1100℃이다. Next, as shown in FIG. 2D, the annealing process is performed at a temperature of 750 to 1200 ° C. and an O 2 atmosphere before filling the trench inside with a gapfill oxide film using a high density plasma method. (110) Nitrify the surface. Here, the annealing process is carried out for 1 to 5 minutes using a rapid thermal anneal (or thermal thermal anneal), or 20 to 200 minutes if carried out in a furnace (furnace). Preferably, the proper temperature of the annealing process is 900 to 1100 ° C.

그 다음, 도 2e에 도시된 바와 같이, 어닐링 공정에 의해 표면이 질산화된 라이너 질화막(110)이 형성된 기판의 트렌치에 고밀도 플라즈마(High Density Plasma) 방법으로 갭필 산화막(112)을 매립한다. 이때, 표면이 질산화된 라이너 질화막(110)에 의해 블루잉-현상이 최소화되어 갭필 산화막(112)과 질산화막의 결합력이 커서 갭필 산화막(112)의 초기 증착이 균일해진다.Next, as shown in FIG. 2E, the gapfill oxide film 112 is buried in the trench of the substrate on which the liner nitride film 110 whose surface is nitrified by the annealing process is formed by a high density plasma method. At this time, the bluing-phenomena is minimized by the liner nitride film 110 whose surface is nitridated, and thus the initial deposition of the gap fill oxide film 112 is uniform because the bonding force between the gap fill oxide film 112 and the nitric oxide film is large.

계속해서, 도 2f에 도시된 바와 같이, 균일하게 트렌치에 매립된 갭필 산화막(112)을 평탄화 공정으로 연마하되, 질화막(104)이 드러날 때까지 진행한다. 그리고, 전면 식각공정으로 평탄화된 갭필 산화막(112')을 질화막(104) 보다 낮도록 소정량 식각한 후에 인산 용액으로 질화막(104)을 제거한다.Subsequently, as shown in FIG. 2F, the gapfill oxide film 112 uniformly embedded in the trench is polished by a planarization process, and the process proceeds until the nitride film 104 is exposed. The nitride film 104 is removed using a phosphoric acid solution after etching the gap fill oxide film 112 ′ planarized by the entire surface etching process to be lower than the nitride film 104.

그리고, 도 2g에 도시된 바와 같이, 세정 공정을 실시하면 기판의 트렌치에 갭필 산화막(112')이 매립되어 소자의 분리영역(ISO)을 정의하는 STI형 소자분리막(114)이 형성된다.As shown in FIG. 2G, when the cleaning process is performed, the gapfill oxide film 112 ′ is embedded in the trench of the substrate to form the STI type device isolation film 114 defining the isolation region ISO of the device.

상술한 바와 같이, 본 발명은 갭필 산화막을 증착하기전에 라이너 질화막이 형성된 기판에 고온의 열처리 공정을 실시하여 라이너질화막 표면을 갭필 산화막과의 결합이 우수한 질산화막(SiON)으로 형성함으로써 갭필 산화막 증착시 라이너 질화막의 블루잉-업 현상을 막고 균일하게 산화막을 증착할 수 있다.As described above, the present invention performs a high temperature heat treatment process on the substrate on which the liner nitride film is formed before depositing the gap fill oxide film to form the surface of the liner nitride film as a nitride oxide (SiON) having excellent bonding with the gap fill oxide film. The bluing-up phenomenon of the liner nitride film can be prevented and the oxide film can be deposited uniformly.

이에 따라, 본 발명은 소자분리막의 폭을 정확하게 확보할 수 있으며 소자분리공정의 수율을 높일 수 있는 이점이 있다.Accordingly, the present invention can secure the width of the device isolation film accurately and has the advantage of increasing the yield of the device isolation process.

Claims (4)

반도체기판에 소자의 활성 영역 및 분리 영역을 정의하기 위한 트렌치 구조의 소자분리막을 형성함에 있어서,In forming a device isolation film having a trench structure to define an active region and an isolation region of a device on a semiconductor substrate, 반도체기판에 패드 산화막 및 질화막을 순차적으로 적층하는 단계;Sequentially depositing a pad oxide film and a nitride film on a semiconductor substrate; 소자분리마스크를 이용한 사진 및 식각 공정을 진행하여 상기 질화막과 패드 산화막을 패터닝한 후에 상기 기판에 소정 깊이까지 트렌치를 형성하는 단계;Performing a photolithography and etching process using a device isolation mask to pattern the nitride layer and the pad oxide layer, and then forming a trench in the substrate to a predetermined depth; 상기 기판의 트렌치 내측에 측벽 산화막을 형성하는 단계; Forming a sidewall oxide film inside the trench of the substrate; 상기 측벽산화막이 형성된 기판 전면에 라이너 질화막을 형성하는 단계;Forming a liner nitride film on an entire surface of the substrate on which the sidewall oxide film is formed; 상기 라이너 질화막이 형성된 기판에 750∼1200℃의 온도와 O2 분위기에서 어닐링 공정을 실시하여 상기 라이너 질화막 표면을 질산화하는 단계; Nitrifying the surface of the liner nitride layer by performing an annealing process on a substrate having the liner nitride layer formed at a temperature of 750 to 1200 ° C. and an O 2 atmosphere; 상기 기판의 트렌치에 갭필 산화막을 채워넣고 이를 평탄화하는 단계; 및 Filling a gap fill oxide film into the trench of the substrate and planarizing it; And 상기 질화막을 제거하고 세정공정을 실시하여 기판내에 갭필 산화막으로 이루어진 소자분리막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 트렌치를 이용한 소자분리막 형성방법. Removing the nitride film and performing a cleaning process to form a device isolation film made of a gapfill oxide film in the substrate. 제 1항에 있어서, 상기 라이너 질화막의 두께는 30∼500Å으로 하는 것을 특징으로 하는 반도체소자의 트렌치를 이용한 소자분리막 형성방법.The method of claim 1, wherein the liner nitride film has a thickness of 30 to 500 kPa. 제 1항에 있어서, 상기 어닐링 공정은 급속 열처리 방식을 이용하되 1∼5분 동안 실시하는 것을 특징으로 하는 반도체소자의 트렌치를 이용한 소자분리막 형성방법.The method of claim 1, wherein the annealing process is performed using a rapid heat treatment method for 1 to 5 minutes. 제 1항에 있어서, 상기 어닐링 공정은 전기로에서 실시되며 20∼200분 동안 실시하는 것을 특징으로 하는 반도체소자의 트렌치를 이용한 소자분리막 형성방법.The method of claim 1, wherein the annealing process is performed in an electric furnace and is performed for 20 to 200 minutes.
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