KR100425487B1 - Apparatus Of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel that can reduce the number of switch elements to lower power consumption.

The driving apparatus of the plasma display panel according to the present invention includes a first electrode driver for supplying a scan pulse to the first electrode to select a cell in the reset period and a setup / down pulse in the reset period; A first driving unit connected in a push-pull form to apply a voltage signal to the first electrode, a setup driving unit for supplying a positive waveform setup signal having a ramp waveform to the first electrode during a reset period; A set-down driver for supplying a negative polarity signal having a ramp waveform to the first electrode after the polarity setup signal is supplied; A first switch connected between the energy recovery circuit, the setup driver and the scan driver for switching the setdown pulse and the sustain pulse, and a scan voltage connected between the scan driver and the scan voltage source to supply the scan voltage to the scan driver in the address period. A second switch connected between the supply unit, the scan voltage supply unit, and the set-down driver unit to perform a control operation for supplying a set-down pulse having a voltage level below ground level and a scan pulse of the address period, and formed between the setup driver and the first switch. And a charge / discharge path connecting a first node, a scan voltage supply unit, and a second node formed between the second switch.

Description

Apparatus Of Driving Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a driving apparatus of a plasma display panel which reduces power consumption by reducing the number of switch elements used in a driving circuit of a plasma display panel.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of inert mixed gases such as He + Xe, Ne + Xe and Ne + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 30Y and a common sustain electrode 30Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The scan / sustain electrode 30Y and the common sustain electrode 30Z each have a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and are formed on one edge region of the transparent electrode. Electrodes 13Y and 13Z. The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (hereinafter, referred to as “ITO”). The metal bus electrodes 13Y and 13Z are usually formed of metal such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce the voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, and Ne + Ne + Xe for discharging is injected into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into a reset and an address period and a sustain period. Here, the reset and address periods of each subfield are the same for each subfield, while the sustain period increases at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. do. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

Such a driving method of the PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted by the address discharge in the address period. First, the selective write driving method turns off the full screen in the reset period, and then turns on the selected discharge cells in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge.

In the selective erasing driving method, the entire screen is turned on by writing discharge in the reset period, and then the selected discharge cells are turned off in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells not selected by the address discharge.

Since the selective erasing method is a discharge for removing wall charges in the cell, the scanning pulse width is narrower than that of the selective writing method, that is, the addressing time can be reduced. The drive waveform of the selective writing method reduces the contrast as the number of lamp pulses increases, so the quality of the driving waveform becomes weaker as it is used more. Accordingly, in the driving method of the PDP, as shown in FIG. 3, one frame is composed of the selective write subfields SF1 through SF6 and the selective erase subfields SF7 through SF12 to configure the selective write and erase method. Drive in parallel.

Referring to FIG. 3, in the method of driving a three-electrode alternating surface discharge PDP, one frame includes subfields SF1 through SF6 of selective writing and subfields SF7 through SF12 of selective erasing. The first subfield SF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining discharge for the discharge cell selected by the address discharge, and an erasing period for canceling the sustain discharge. . Each of the second to fifth subfields SF2 to SF5 is divided into an optional write address period, a sustain period, and an erase period. The sixth subfield SF6 is divided into an optional write address period and a sustain period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2n in each subfield (n = 0, 1, 2, 3, 4). Is increased by 5). The seventh through twelfth subfields SF7 through SF12 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without a full surface writing period in which the full screen is lit. Divided into periods. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 25 to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must have the previous subfield turned on to turn off unnecessary discharge cells whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. To this end, the cells turned on in the sixth subfield WSF, which is the last selective write subfield WSF, must be turned on by the sustain discharge in order for the selective erase subfield ESF to be used. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off cells that are turned on in the previous subfield without front lighting.

4 is a diagram illustrating a driving waveform according to the PDP driving method illustrated in FIG. 3.

Referring to FIG. 4, in the reset period of the first selective write subfield SW1, the reset pulse RP of the ramp-down waveform is followed by the reset pulse RP of the ramp-up waveform in the scan electrode lines Y. It is supplied sequentially. At this time, the reset pulse (-RP) of the ramp-down waveform drops to the negative scan reference voltage (-Vw). In addition, the scan electrode voltage DCSC having a positive polarity is supplied to the sustain electrode lines Z.

In the address period of the selective write subfield SW1, the negative polarity is applied to the scan electrode lines Y and the address electrode lines X while the positive scan DC voltage DCSC is supplied to the sustain electrode lines Z. A negative selective write scan pulse (-SWSP) and a positive polarity (+) selective write data pulse (SWDP) are supplied to be synchronized with each other. The address discharge is performed by the selective write scan pulse SWSP and the optional data pulse SWDP as described above.

Sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z so that sustain discharge occurs for the cells turned on by the address discharge of the selective write subfield SW. . At the end of the second selective write subfield SW2, the erase pulse EP is supplied to the scan electrode lines Y to erase the sustain discharge.

The reset period of the selective erase subfield SE is omitted. In the address period of the selective erase subfield SE, a negative selective erase scan pulse (-SESP) and a positive polarity (-) for turning off a cell in each of the scan electrode lines (Y) and the address electrode lines (X). The selective erase data pulses SEDP of +) are supplied to be synchronized with each other. The selective erase scan pulse (-SESP) drops to the selective erase scan voltage (-Ve) higher than the scan reference voltage (-Vw).

Sustain pulses SUSPy and SUSPz are alternately supplied to scan electrode lines Y and sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by the address discharge of the selective erase subfield SE. do. When the next subfield is a selective erase field SE, a sustain pulse SUSPy having a relatively large pulse width is supplied to the scan electrode lines Y at the end of the current selective erase subfield SE. The erase pulse EP and the ramp signal RAMP are supplied to the scan electrode lines Y and the sustain electrode lines Z in the last selective erase subfield in which the next subfield is the selective write subfield SW. Clear the sustain discharge of the cells.

FIG. 5 schematically illustrates a driving apparatus of a general PDP, and has been described with reference to the selective write and erase scheme shown in FIG. 4.

Referring to FIG. 5, the PDP driving apparatus drives the Y driving unit 100 for driving the m scan / sustain electrode lines Y1 to Ym and the m common sustain electrode lines Z1 to Zm. And a Z driver 102 for driving the n address electrode lines X1 to Xn.

The Y driver 100 initializes the full screen by supplying the setup / down waveforms RPSY and -RPSY in the selective write subfield WSF, and in the selective write subfield WSF and the selective erase subfield SEF. Different scan pulses -SWSCN and -SESCN are sequentially supplied to the scan / sustain electrode lines Y1 to Ym. In addition, the Y driver 100 supplies sustain pulses SUSY in the selective write subfield WSF and the selective erase subfield ESF to generate sustain discharge.

The Z driver 102 is commonly connected to the common sustain electrode lines Z1 to Zm to apply the setdown waveform (-RPSZ), the scan DC voltage, and the sustain pulse (SUSZ) to the Z electrode lines Z1 to Zm. It serves to supply sequentially.

The X driver 104 supplies the write data pulse SWD or the erase data pulse SED to the address electrode lines X1 to Xn to be synchronized with the scan pulses -SWSCN and -SESCN.

6 illustrates the Y driver 100 in detail to explain the configuration and operation of the Y driver 100.

Referring to FIG. 6, the Y driver 100 includes a fourth switch Q4 connected between an energy recovery circuit 41 and a driver integrated circuit (hereinafter, referred to as IC) 42. A scan reference voltage supply unit 43 and a scan voltage supply unit 44 connected between the fourth switch Q4 and the driver IC 42 to generate the scan pulses -SWSCN and -SESCN, and the fourth switch Q4. And a setup supply 45 and a set down supply 46 connected between the scan reference voltage supply 43 and the scan voltage supply 44 to generate setup / down waveforms RPSY and -RPSY, and a setup supply 45 And a fifth switch Q5 connected between the set-down supply 46 and for switching the setup / down waveform. Also connected between the setup voltage source Vsetup and the energy recovery circuit 41, between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vs constant. A second capacitor C2 connected in series is provided.

The driver IC 42 is connected in a push-pull form and includes eleventh and twelfth switches Q11 and Q12 to which a voltage signal is input from the energy recovery circuit 41, the scan reference voltage supply 43, and the scan voltage supply 44. It is composed of

The output line between the eleventh and twelfth switches Q11 and Q12 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 41 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q15 and Q16 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a first switch Q1 connected between the sustain voltage supply source Vs and the second node n2, and a second; The second switch Q2 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 41 will be described below. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the fifteenth switch Q15 is turned on, the voltage charged in the external capacitor CexY is supplied to the driver IC 42 via the fifteenth switch Q15, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 42. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The first switch Q1 is turned on at the resonance point of the resonant waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q1 is turned off and the sixteenth switch Q16 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the sixteenth switch Q16 is turned off and the second switch Q2 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

A fourth switch for forming a current path between the energy recovery circuit 41 and the driver IC 42 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by the energy recovery circuit 41. Q4 and the fifth switch Q5 remain on.

In this way, the energy recovery circuit 41 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym by using the external capacitor CexY. The energy recovery circuit 41 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period.

The scan reference voltage supply unit 43 includes a seventh switch Q7 connected between the third node n3 and the selective write scan voltage source -Vyw, and a scan voltage source (-) with the third node n3 and the selective erase. It consists of the 8th and 9th switches Q8 and Q9 connected in series between Vye. The seventh switch Q7 is switched in response to the control signal yw supplied in the address period of the selective write subfield WSF to supply the selective write scan voltage -Vyw to the driver IC 42. do. The eighth and ninth switches Q8 and Q9 are switched in response to the control signal ye supplied in the address period of the selective erasing subfield ESF to thereby convert the selective erasing scan voltage -Vye to the driver IC 42. To serve.

The scan voltage supply 44 is composed of a thirteenth switch Q13 connected in series between the scan voltage source Vsc and the fourth node n4. The thirteenth switch Q13 is switched in response to the control signal SC supplied in the address periods of the selective write subfield WSF and the selective erase subfield ESF to transfer the scan voltage Vsc to the driver IC 42. It serves to supply. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows different voltage levels to be created in the erase scheme.

The setup supply 45 is composed of a fourth diode D3, a resistor R and a third switch Q3 connected between the setup voltage source Vsetup and the third node n3. The third diode D3 blocks the reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The third switch Q3 serves to supply the setup waveform RPSY. The slope of this setup waveform RPSY is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the third switch Q3, that is, the gate terminal. Therefore, the slope of the setup waveform RPSY is adjusted by adjusting the resistance value of the variable resistor R1.

The set-down supply 46 includes a sixth switch Q6 connected between the third node n3 and the selective write scan voltage source -Vyw. The sixth switch Q6 serves to supply the setdown waveform -RPSY. The slope of the set-down waveform (-RPSY) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the sixth switch Q6, that is, the gate terminal. Therefore, the slope of the set-down waveform -RPSY is adjusted by adjusting the resistance value of the variable resistor R2.

The Y driver 100 includes a tenth switch Q10 connected to the scan reference voltage supply unit 43 and the scan voltage supply unit 44 via the third node n3 and the fourth node n4, respectively. The tenth switch Q10 switches the scan voltage Vsc supplied to the driver IC 42 in response to the control signal Dic_updn.

Since the fifth switch Q5 is supplied with the negative polarity eye to the sustain down part in the set down and addressing operations, the fifth switch Q5 is to prevent the short circuit from the ground through the second switch Q2 in the energy recovery circuit 41.

6, the operation of the Y driving unit 100 will be described.

In the reset period of the selective write subfield WSF, the setup waveform RPSY and the setdown waveform -RPSY are successively supplied to the scan / sustain electrode line Y. To this end, the third, fifth and sixth switches Q3, Q5 and Q6 are sequentially turned on in response to the control signals setup and setdn, respectively. Then, the positive set-up voltage Vsetup and the negative scan reference voltage (-Vyw) are passed through the third, fifth and sixth switches Q3, Q5 and Q6 and the twelfth switch Q12 of the driver IC 42. ) Is sequentially supplied to the scan / sustain electrode line (Y). The setup waveform RPSY rises to the setup voltage Vsetup and the set-down waveform -RPSY falls to the negative scan reference voltage -Vyw. Here, the setup voltage Vsetup is set to 240 to 260 (V) higher than the sustain voltages 170 to 190 V supplied in the sustain period. The negative scan reference voltage (-Vyw) is set to approximately -140 to -160 (V). Since the setup waveform RPSY rises to the setup voltage Vsetup at a predetermined slope, the setup waveform RPSY generates wall charges required in the scan without causing a large discharge in the cell. In the falling section of the setup waveform RPSY, the inclination of the energy recovery circuit 41 operates so that its inclination is smoothly adjusted. Since the falling slope of the setup waveform (RPSY) is gentle, the cells are not self-erased and the voltage margin of the set-down waveform (-RPSZ) supplied to the common sustain electrode lines (Z1 to Zm) is widened. do.

In the address period of the selective write subfield WSF, the thirteenth and fourteenth switches Q13 and Q14 are turned on and the tenth switch Q10 is turned off to transmit the scan voltage Vsc to the driver IC 42. Supply. The seventh switch Q7 is turned on so that the selective write scan voltage -Vyw is supplied to the driver IC 42. The write scan pulse -SWSCN is then sequentially supplied to the scan / sustain electrode lines Y1 to Ym. The voltage level of this write scan pulse (-SWSCN) is set to 60 to 80 (V). In synchronization with this write scan pulse (-SWSCN), a write video data pulse (SWD) having a logic value of '1' is supplied. As a result, writing discharge occurs in the selected discharge cell due to the voltage difference between the write scan pulse (-SWSCN) and the write video data pulse (SWD) having a large pulse width. Wall charges and space charges are generated in the discharge cells in which the lighting discharges are generated. The discharge cells selected by the wall charges and the space charges are charged with the wall voltage at which the discharge can occur by the sustain pulses supplied in the subsequent sustain period. The tenth switch Q10 maintains the off state while the scan pulse (−SWSCN) is supplied, and maintains the on state during other periods.

In the sustain period of the selective write subfield WSF, the first sustain pulse SUSY1 having a large pulse width is supplied to the scan / sustain electrode line Y, and then the normal sustain pulse SUSY2 having a small pulse width and the pulse width are supplied. The large last sustain pulse SUSY3 is supplied continuously. At this time, the energy recovery circuit 41 supplies the resonance waveform to the driver IC 42 by using the voltage charged in the external capacitor CexY and the LC resonance, and then turns on the first switch Q1 to maintain the sustain voltage. (Vs) is supplied to the driver IC 42. The discharge cells in which the writing discharge is generated in the address period are sustained by the number of sustain pulses SUSY1, SUSY2, and SUSY3. In the discharge cells in which writing discharge has not occurred in the address period, even when the sustain voltage Vs is supplied by the sustain pulses SUSY1, SUSY2, and SUSY3, the discharge does not occur because the wall voltage is almost absent. The first sustain pulse SUSY1 has a pulse width of approximately 20 s so that the sustain discharge starts stably. The second sustain pulse SUSy2 has a pulse width of approximately 2.5 to 5 ms. The third sustain pulse SUSy3 is set to a pulse width of 5 m or more so that the sustain discharge is not self-erased.

At the end of the selective write subfield (WSF), the erase pulse (ERSPY) or the reset pulse (RSTP with a large pulse width) is large depending on whether the next subsequent subfield is the selective write subfield (WSF) or the selective erase subfield (ESF). ) Is supplied. If the next subfield that follows is the selective write subfield WSF, the pair of erase pulses ERSPZ and ramp waveforms RAMP supplied to the common sustain electrode line Z at the end of the current selective write subfield WSF are combined. The erase pulse ERSPY is supplied to the scan / sustain electrode line Y. The pair of erasing pulses ERSPY and ERSPZ and the ramp waveform RAMP thus suppress the sustain discharge of the selected discharge cells by continuously generating a weak discharge. The erase pulses ERSPY and ERSPZ and the ramp waveform RAMP continuously generate as few discharges as possible, so that the wall voltages are uniformly accumulated in the cells of the full screen at the initial point of the subsequent selective write subfield WSF. . The erase pulses ERSPY and ERSPZ are narrow square waves having a pulse width of approximately 1 ms, and the ramp waveform RAMP is set to a pulse width of approximately 20 Hz. On the other hand, if the next subsequent subfield is the selective erasure subfield ESF, the third sustain pulse SUSY3, which is a square wave having a large pulse width, is supplied at the end of the current selective write subfield WSF. The third sustain pulse SUSY3 generates sufficient wall charge in the cells that are currently turned on to enable stable address operation in the subsequent selective erase subfield (ESF).

On the other hand, if the next subsequent subfield is the selective erase subfield (ESF), the pulse supplied at the end of the current selective write subfield (WSF) can be supplied with a pulse having a wide pulse width and the voltage level is greater than the normal sustain pulse. It may be set. In addition, if the next subfield is the selective erasing subfield (ESF), the pulse supplied at the end of the current selective write subfield (WSF) has a wider pulse width and a higher voltage level than the sustain pulse supplied in the sustain period. It may be supplied.

The reset period is omitted in the selective erase subfield (ESF). This means that if the next subfield is an optional erase subfield (ESF), the last sustain pulse (SUSY3 or SUS5) generated at the end of the current optional write subfield (WSF) or selective erase subfield (ESF) is the next selective erase subfield. This is because it plays a role in turning on the cell at (ESF). Therefore, the address period is set at the beginning of the selective erasing subfield (ESF).

In the address period of the selective erase subfield ESF, the thirteenth and fourteenth switches Q13 and Q14 are turned on to supply the scan voltage Vs to the driver IC 42. The eighth and ninth switches Q8 and Q9 are turned on to supply the selective erasing scan voltage -Vye to the driver IC 42. Then, the erase scan pulse -SESCN is sequentially supplied to the scan / sustain electrode lines Y1 to Ym. Here, the voltage level of the erase scan pulse (-SESCN) is set to approximately 60 to 80 (V). In synchronization with this erase scan pulse (-SESCN), an erase video data pulse SED having a logic value of "0" is supplied. As a result, a weak writing discharge occurs in the selected discharge cell due to the voltage difference between the erase scan pulse (-SESCN) and the erase video data pulse (SED) having a narrow pulse width. By this discharge, wall charges and space charges in the discharge cells are recombined and erased. Accordingly, since the discharge cells generated by the erase scan pulse (-SESCN) and the erase video data pulse (SED) are not charged as much as the voltage required for the discharge, no discharge occurs even when the sustain pulse is supplied. The tenth switch Q10 maintains the off state while the scan pulse (-SESCN) is supplied, and maintains the on state during other periods.

In the sustain period of the selective erasing subfield ESF, the normal sustain pulse SUSY4 having a pulse width of approximately 2.5 ms to 5 ms is supplied. At this time, the energy recovery circuit 41 supplies the resonance waveform to the driver IC 42 by using the voltage charged in the external capacitor CexY and the LC resonance, and then turns on the first switch Q1 to maintain the sustain voltage. (Vs) is supplied to the driver IC 42. Since the discharge cells in which the erase discharge has occurred in the address period have almost no internal wall voltage, discharge does not occur even when the sustain voltage Vs is supplied by the sustain voltage pulse SUSY4. On the other hand, the discharge cells which do not have erase discharge in the address period are charged to the voltage at which discharge can occur because the charged wall voltage and the sustain voltage Vs are added during the reset period or the setup period. Therefore, the discharge cells in which no erasure discharge occurs in the address period are discharged by the number of sustain pulses SUSY4.

At the end of the selective erase subfield (ESF), a sustain pulse (SUSY5) having a large pulse width or a small pulse width is erased depending on whether the next subsequent subfield is the selective erase subfield (ESF) or the selective write subfield (WSF). The pulse ERSPY is supplied. If the next subfield that follows is the selective erasing subfield (ESF), a sustain pulse SUSUS5 having a large pulse width is supplied to turn on the discharge cells at the end of the current selective erasure subfield (ESF). If the next subfield that follows is the selective write subfield WSF, the erase pulse ERSPZ and ramp waveform RAMP supplied to the common sustain electrode lines Z1 to Zm at the end of the current selective erase subfield ESP are A pair of erase pulses ERSPY are supplied to the scan / sustain electrode lines Y1 to Ym. The erase pulses ERSPY and ERSPZ and the ramp waveform RAMP continuously generate a weak discharge so that the wall voltage is uniform in the full screen cells at the initial point of the next selective write subfield WSF. By the erase pulses ERSPY and ERSPZ and the ramp waveform RAMP, uniform wall charges and space charges are accumulated in the discharge cells of the full screen. Operations relating to them are explained by the drive waveform and the switch control signal shown in FIG.

However, since the reset voltage and the sustain voltage pass through the fourth switch Q4 and the fifth switch Q5, the switch must be a high breakdown voltage above the reset voltage for applying the setup waveform. A total of 10 FETs are used to protect the circuit using 5 units each. This increases the cost of using a large number of FETs and also has the disadvantage of generating a lot of energy loss.

Accordingly, an object of the present invention is to provide a driving device of a plasma display panel which can reduce the number of switch elements and reduce energy loss.

1 is a perspective view showing a typical three-electrode alternating surface discharge plasma display panel.

2 is a diagram showing a frame structure of a conventional plasma display panel.

3 is a view showing another configuration of one frame of a conventional plasma display panel.

FIG. 4 is a diagram illustrating a driving waveform of the PDP driving method according to the selective writing and erasing scheme of FIG. 3.

5 is a view schematically showing a driving apparatus of a general PDP.

6 is a view showing in detail the scan / sustain electrode driver according to the prior art;

FIG. 7 is a view for explaining a driving waveform and a switch control signal according to the driving unit shown in FIG. 6;

8 is a view illustrating in detail the scan / sustain electrode driver in the driving apparatus of the PDP according to the present invention;

FIG. 9 is a diagram for explaining driving waveforms and switching operations of a selective write subfield in the driving circuit shown in FIG. 8; FIG.

10 is a view showing a driving circuit for detecting the setdown level shown in FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan / sustain electrode

30Z: common sustain electrode 41, 51: energy recovery circuit

42,52: driver integrated circuit 43,53: scan reference voltage supply

44,54: Scan voltage supply part 45,55: Setup voltage supply part

46,56: set down voltage supply part 57: bridge rectification circuit

100: Y drive unit 102: Z drive unit

104: X drive part

In order to achieve the above object, the driving apparatus of the plasma display panel of the present invention is to drive the plasma by dividing it into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining the discharge of the selected cell. A driving device for a display panel, comprising: an energy recovery circuit for recovering energy from a first electrode of the panel, the scan pulse corresponding to a setup / down pulse during the reset period and a selective write for selecting the cell in the address period And a first electrode driver for supplying a scan pulse corresponding to selective erasure to the first electrode; The first electrode driver is connected in the form of a push-pull scan driver for applying a voltage signal to the first electrode, and a setup driver for supplying a positive waveform setup signal having a ramp waveform to the first electrode during the reset period. And a set-down driver configured to supply a negative waveform signal having a ramp waveform to the first electrode after the positive setup signal is supplied to the first electrode. A first switch connected between the energy recovery circuit, the setup driver and the scan driver for switching a setdown pulse and a sustain pulse, and between the scan driver and the scan voltage source to provide a scan voltage in an address period of a selective write and erase field. A switch for supplying a scan voltage supply unit to supply the scan driver to the scan driver, and a control operation of supplying a scan pulse of an address period and a setdown pulse having a voltage level below the ground level connected between the scan voltage supply unit and the setdown driver; And a charge / discharge path for connecting a first node formed between the setup driver and the first switch and a second node formed between the scan voltage supply unit and the second switch.

The present invention includes an energy recovery circuit for recovering energy from the second electrode of the panel alternately with the first electrode driver, and a second electrode for supplying a DC voltage to the second electrode during selective writing and selective erasing. It is characterized by including a drive unit.

In the present invention, data for supplying any one of selective write data for selectively turning on the cell and selective erase data for selectively turning off the cell to the third electrode orthogonal to the first and second electrodes in an address period. It further comprises a drive unit.

In the present invention, it is further characterized by a set-down voltage detector for controlling the second switch to have a voltage level below the ground level.

In the present invention, the down voltage detector includes a first resistor connected to the scan driver, a second resistor and a third resistor connected to the first resistor to distribute the voltage across the first resistor, and the second resistor; A zener diode connected between a third resistor to maintain a voltage rough to the first resistor, fourth and fifth resistors connected in series between an external voltage source and ground to distribute an external voltage at a constant magnification; A signal derived from between the third node between the second and third resistors and the fourth node between the fourth and fifth resistors to compare the voltage across the third and fourth nodes to control the switching operation of the second switch. And a comparator for outputting.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 and 10.

The driving apparatus of the PDP according to the present invention includes a Y driver 100 for driving m scan / sustain electrode lines Y1 to Ym and m common sustain electrode lines Z1 to Zm as shown in FIG. 5. And a Z driver 102 for driving the N-axis, and an X driver 104 for driving the n address electrode lines X1 to Xn, which will be described based on a selective write and erase method.

The Y driver 100 initializes the full screen by supplying the setup / down waveforms RPSY and -RPSY in the selective write subfield WSF, and in the selective write subfield WSF and the selective erase subfield SEF. Different scan pulses -SWSCN and -SESCN are sequentially supplied to the scan / sustain electrode lines Y1 to Ym. In addition, the Y driver 100 supplies sustain pulses SUSY in the selective write subfield WSF and the selective erase subfield ESF to generate sustain discharge.

The Z driver 102 is commonly connected to the common sustain electrode lines Z1 to Zm to apply the setdown waveform (-RPSZ), the scan DC voltage, and the sustain pulse (SUSZ) to the Z electrode lines Z1 to Zm. It serves to supply sequentially.

The X driver 104 supplies the write data pulse SWD or the erase data pulse SED to the address electrode lines X1 to Xn to be synchronized with the scan pulses -SWSCN and -SESCN.

8 illustrates the Y driver 100 in detail to explain the configuration and operation of the Y driver 100 in the driving apparatus of the PDP according to the present invention.

Referring to FIG. 8, the Y driver 100 includes a fourth switch Q4 connected between the energy recovery circuit 51 and the driver IC 52, and a fourth switch Q4 and the driver IC 52. Connected between the scan reference voltage supply section 53 and the scan voltage supply section 54 and the fourth switch Q4 and the scan voltage supply section 54 for generating scan pulses (-SWSCN, -SESCN) And a setup supply 55 and a set down supply 56 for generating the down waveforms RPSY and -RPSY. Also connected between the setup voltage source Vsetup and the energy recovery circuit 51, between the first capacitor C1 and the scan voltage source Vsc and the third node n4 for keeping the setup voltage Vs constant. A second capacitor C2 connected in series is provided.

The driver IC 52 is connected in a push-pull form and includes tenth and eleventh switches Q10 and Q11 to which a voltage signal is input from the energy recovery circuit 51, the scan reference voltage supply unit 53, and the scan voltage supply unit 54. It consists of

The output line between the tenth and eleventh switches Q10 and Q11 is connected to any one of the scan / sustain electrode lines Y1 to Ym.

The energy recovery circuit 51 includes external capacitors CexY for charging the voltage recovered from the scan / sustain electrode lines Y1 to Ym, switches Q13 and Q14 connected in parallel to the external capacitors CexY, An inductor L_y connected between the first node n1 and the second node n2, a first switch Q1 connected between the sustain voltage supply source Vs and the second node n2, and a second The second switch Q2 is connected between the node n2 and the ground terminal GND.

The operation of the energy recovery circuit 51 will be described below. It is assumed that the external capacitor Cex_y is charged with the voltage Vs / 2. When the thirteenth switch Q13 is turned on, the voltage charged in the external capacitor CexY is supplied to the driver IC 52 via the thirteenth switch Q13, the first diode D1, and the inductor L_y. And supplied to the scan / sustain electrode lines Y1 to Ym through an internal diode (not shown) of the driver IC 52. At this time, since the inductor L_y forms a series LC resonant circuit together with the capacitance C in the cell, the resonant waveform is supplied to the scan / sustain electrode lines Y1 to Ym. The first switch Q1 is turned on at the resonance point of the resonance waveform to supply the sustain voltage Vs to the scan / sustain electrode lines Y1 to Ym. Then, the voltage level of the scan / sustain electrode lines Y1 to Ym maintains the sustain voltage Vs. After a predetermined time, the first switch Q1 is turned off and the fourteenth switch Q14 is turned on. . At this time, the voltages of the scan / sustain electrode lines Y1 to Ym are recovered to the external capacitor Cex_y. Subsequently, when the fourteenth switch Q14 is turned off and the second switch Q2 is turned on, the voltage of the scan / sustain electrode lines Y1 to Ym maintains the ground potential.

The fourth switch to form a current path between the energy recovery circuit 51 and the driver IC 52 while the voltage of the scan / sustain electrode lines Y1 to Ym is charged and discharged by the energy recovery circuit 51. Q4 remains on.

In this way, the energy recovery circuit 51 recovers the voltage discharged from the scan / sustain electrode lines Y1 to Ym by using an external capacitor CexY. The energy recovery circuit 51 supplies the recovered voltage to the scan / sustain electrode lines Y1 to Ym to reduce excessive power consumption during discharge of the setup period and the sustain period.

The scan reference voltage supply unit 53 includes a sixth switch Q6 connected between the third node n3 and the selective write scan voltage source -Vyw, and a scan voltage source for the selective erase with the third node n3. The seventh and eighth switches Q7 and Q8 connected in series between Vye. The sixth switch Q6 is switched in response to the control signal yw supplied in the address period of the selective write subfield WSF, thereby supplying the selective write scan voltage -Vyw to the driver IC 52. do. The seventh and eighth switches Q7 and Q8 are switched in response to the control signal ye supplied in the address period of the selective erasing subfield ESF to thereby convert the selective erasing scan voltage (-Vye) into the driver IC 52. To serve.

The scan voltage supply unit 54 is composed of a twelfth switch Q12 connected in series between the scan voltage source Vsc and the fourth node n4. The twelfth switch Q12 is switched in response to the control signal SC supplied in the address periods of the selective write subfield WSF and the selective erase subfield ESF to transfer the scan voltage Vsc to the driver IC 52. It serves to supply. At this time, the second capacitor C2 connected between the scan voltage source Vsc and the third node n3 charges the scan voltage from the scan voltage source Vsc and maintains the charged voltage at a floating level. Allows different voltage levels to be created in the erase scheme. The second capacitor C2 is connected between the scan voltage source Vsc and the setup supply unit 55 to maintain a constant scan voltage.

The setup supply 55 is composed of a third diode D3, a resistor R and a third switch Q3 connected between the setup voltage source Vsetup and the fourth node n4. The third diode D3 blocks the reverse current flowing from the fourth node n4 toward the setup voltage source Vsetup. The third switch Q3 serves to supply the setup waveform RPSY. The slope of this setup waveform RPSY is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the third switch Q3, that is, the gate terminal. Therefore, the slope of the setup waveform RPSY is adjusted by adjusting the resistance value of the variable resistor R1. In addition, the first capacitor C1 is connected between the setup voltage source Vsetup and the energy recovery circuit 51 to keep the setup waveform RPSY constant.

The set-down supply 56 includes a fifth switch Q5 connected between the third node n3 and the selective write scan voltage source -Vyw. The fifth switch Q5 serves to supply the setdown waveform -RPSY. The slope of the set-down waveform -RPSY is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the fifth switch Q5, that is, the gate terminal. Therefore, the slope of the set-down waveform -RPSY is adjusted by adjusting the resistance value of the variable resistor R2.

The Y driver 100 includes a ninth switch Q9 connected to the scan reference voltage supply unit 53 and the scan voltage supply unit 54 via the third node n3 and the fourth node n4, respectively. The ninth switch Q9 switches the scan voltage Vsc supplied to the driver IC 52 in response to the control signal Dic_updn.

FIG. 9 illustrates driving waveforms and switching operations of the selective write subfield in the driving circuit of FIG. 8. Referring to FIGS. 8 and 9, the operation of the Y driver 100 will be described as follows.

In the reset period of the selective write subfield WSF, the setup waveform RPSY and the setdown waveform -RPSY are successively supplied to the scan / sustain electrode line Y. To this end, the third, fourth and fifth switches Q3, Q4 and Q5 are sequentially turned on in response to the control signals setup and setdn, respectively. Then, the positive setup voltage Vsetup and the negative scan reference voltage (-Vyw) are passed through the third, fourth and fifth switches Q3, Q4 and Q5 and the eleventh switch Q11 of the driver IC 52. ) Is sequentially supplied to the scan / sustain electrode line (Y). The setup waveform RPSY rises to the setup voltage Vsetup and the set-down waveform -RPSY falls to the negative scan reference voltage -Vyw. The set-down waveform (-RPSY) is driven by dividing the voltage operation section above ground and the voltage operation section below ground based on the time point P.

In the T1 section, a setdown operation is performed through an internal diode of the fourth switch Q4, the fifth switch Q5, the ninth switch Q9, and the tenth switch Q10 in the driver IC 52. After the P point, the set-down operation is continued by turning off the ninth switch Q9 and turning on the eleventh switch Q11 in the T2 section. After that, when the set-down waveform becomes the selection clause write reference voltage (-Vw), the reset operation is completed.

As described above, driving the divided sections causes the fourth node n4 to be lowered to the ground or less when the setdown operation is continuously performed through the ninth switch Q9. This is because a short circuit with the ground is performed through the internal diodes of the fourth switch Q4 and the second switch Q2. In addition, when the set-down operation is performed through the eleventh switch Q11, there is a problem that the breakdown voltage that the driver IC 52 can withstand is exceeded through the sustain voltage Vs and the selective write reference voltage (-Vyw) before the start of the setdown. .

Here, the setup voltage Vsetup is set to 240 to 260 (V) higher than the sustain voltages 170 to 190 V supplied in the sustain period. The negative scan reference voltage (-Vyw) is set to approximately -140 to -160 (V). Since the setup waveform RPSY rises to the setup voltage Vsetup at a predetermined slope, the setup waveform RPSY generates wall charges required in the scan without causing a large discharge in the cell. In the falling section of the setup waveform RPSY, the inclination of the energy recovery circuit 51 is operated to smoothly adjust the slope. Since the falling slope of the setup waveform (RPSY) is gentle, the cells are not self-erased and the voltage margin of the set-down waveform (-RPSZ) supplied to the common sustain electrode lines (Z1 to Zm) is widened. do.

In the address period of the selective write subfield WSF, the twelfth switch Q12 is turned on and the ninth switch Q9 is turned off to supply the scan voltage Vsc to the driver IC 52. The sixth switch Q6 is turned on so that the selective write scan voltage -Vyw is supplied to the driver IC 52. The write scan pulse -SWSCN is then sequentially supplied to the scan / sustain electrode lines Y1 to Ym. The voltage level of this write scan pulse (-SWSCN) is set to 60 to 80 (V). In synchronization with this write scan pulse (-SWSCN), a write video data pulse (SWD) having a logic value of '1' is supplied. As a result, writing discharge occurs in the selected discharge cell due to the voltage difference between the write scan pulse (-SWSCN) and the write video data pulse (SWD) having a large pulse width. Wall charges and space charges are generated in the discharge cells in which the lighting discharges are generated. The discharge cells selected by the wall charges and the space charges are charged with the wall voltages at which discharges can occur by the sustain pulses supplied in the subsequent sustain periods. The ninth switch Q9 maintains the off state while the set-down pulse (-RPSY) is supplied with a voltage below ground level and while the scan pulse (-SWSCN) is supplied, and remains on for other periods. .

In the sustain period of the selective write subfield WSF, the first sustain pulse SUSY1 having a large pulse width is supplied to the scan / sustain electrode line Y, and then the normal sustain pulse SUSY2 having a small pulse width and the pulse width are supplied. The large last sustain pulse SUSY3 is supplied continuously. At this time, the energy recovery circuit 51 supplies the resonance waveform to the driver IC 52 using the voltage charged in the external capacitor CexY and the LC resonance, and then turns on the first switch Q1 to sustain the voltage. (Vs) is supplied to the driver IC 52. The discharge cells in which the writing discharge is generated in the address period are sustained by the number of sustain pulses SUSY1, SUSY2, and SUSY3. In the discharge cells in which writing discharge has not occurred in the address period, even when the sustain voltage Vs is supplied by the sustain pulses SUSY1, SUSY2, and SUSY3, the discharge does not occur because the wall voltage is almost absent. The first sustain pulse SUSY1 has a pulse width of approximately 20 s so that the sustain discharge starts stably. The second sustain pulse SUSY2 has a pulse width of approximately 2.5 to 5 ms. The third sustain pulse SUSY3 is set to a pulse width of 5 m or more so that the sustain discharge is not self-erased.

At the end of the selective write subfield (WSF), the erase pulse (ERSPY) or the reset pulse (RSTP with a large pulse width) is large depending on whether the next subsequent subfield is the selective write subfield (WSF) or the selective erase subfield (ESF). ) Is supplied. If the next subfield that follows is the selective write subfield WSF, the pair of erase pulses ERSPZ and ramp waveforms RAMP supplied to the common sustain electrode line Z at the end of the current selective write subfield WSF are combined. The erase pulse ERSPY is supplied to the scan / sustain electrode line Y. The pair of erasing pulses ERSPY and ERSPZ and the ramp waveform RAMP thus suppress the sustain discharge of the selected discharge cells by continuously generating a weak discharge. The erase pulses ERSPY and ERSPZ and the ramp waveform RAMP continuously generate as few discharges as possible, so that the wall voltages are uniformly accumulated in the cells of the full screen at the initial point of the subsequent selective write subfield WSF. . The erase pulses ERSPY and ERSPZ are narrow square waves having a pulse width of approximately 1 ms, and the ramp waveform RAMP is set to a pulse width of approximately 20 Hz. On the other hand, if the next subsequent subfield is the selective erasure subfield ESF, the third sustain pulse SUSY3, which is a square wave having a large pulse width, is supplied at the end of the current selective write subfield WSF. The third sustain pulse SUSY3 generates sufficient wall charge in the cells that are currently turned on to enable stable address operation in the subsequent selective erase subfield (ESF).

On the other hand, if the next subsequent subfield is the selective erase subfield (ESF), the pulse supplied at the end of the current selective write subfield (WSF) can be supplied with a pulse having a wide pulse width and the voltage level is greater than the normal sustain pulse. It may be set. In addition, if the next subfield is the selective erasing subfield (ESF), the pulse supplied at the end of the current selective write subfield (WSF) has a wider pulse width and a higher voltage level than the sustain pulse supplied in the sustain period. It may be supplied.

The reset period is omitted in the selective erase subfield (ESF). This means that if the next subfield is an optional erase subfield (ESF), the last sustain pulse (SUSY3 or SUS5) generated at the end of the current optional write subfield (WSF) or selective erase subfield (ESF) is the next selective erase subfield. This is because it plays a role in turning on the cell at (ESF). Therefore, the address period is set at the beginning of the selective erasing subfield (ESF).

In the address period of the selective erase subfield ESF, the twelfth switch Q12 is turned on to supply the scan voltage Vs to the driver IC 52. The seventh and eighth switches Q7 and Q8 are turned on to supply the selective erasing scan voltage -Vye to the driver IC 52. Then, the erase scan pulse -SESCN is sequentially supplied to the scan / sustain electrode lines Y1 to Ym. Here, the voltage level of the erase scan pulse (-SESCN) is set to approximately 60 to 80 (V). In synchronization with this erase scan pulse (-SESCN), an erase video data pulse SED having a logic value of "0" is supplied. As a result, a weak writing discharge occurs in the selected discharge cell due to the voltage difference between the erase scan pulse (-SESCN) and the erase video data pulse (SED) having a narrow pulse width. By this discharge, wall charges and space charges in the discharge cells are recombined and erased. Accordingly, since the discharge cells generated by the erase scan pulse (-SESCN) and the erase video data pulse (SED) are not charged as much as the voltage required for the discharge, no discharge occurs even when the sustain pulse is supplied. The ninth switch Q9 maintains the off state while the scan pulse (-SESCN) is supplied, and maintains the on state during other periods.

In the sustain period of the selective erasing subfield ESF, the normal sustain pulse SUSY4 having a pulse width of approximately 2.5 ms to 5 ms is supplied. At this time, the energy recovery circuit 51 supplies the resonance waveform to the driver IC 52 using the voltage charged in the external capacitor CexY and the LC resonance, and then turns on the first switch Q1 to sustain the voltage. (Vs) is supplied to the driver IC 52. Since the discharge cells in which the erase discharge has occurred in the address period have almost no internal wall voltage, discharge does not occur even when the sustain voltage Vs is supplied by the sustain voltage pulse SUSY4. On the other hand, the discharge cells which do not have erase discharge in the address period are charged to the voltage at which discharge can occur because the charged wall voltage and the sustain voltage Vs are added during the reset period or the setup period. Therefore, the discharge cells in which no erasure discharge occurs in the address period are discharged by the number of sustain pulses SUSY4.

At the end of the selective erase subfield (ESF), a sustain pulse (SUSY5) having a large pulse width or a small pulse width is erased depending on whether the next subsequent subfield is the selective erase subfield (ESF) or the selective write subfield (WSF). The pulse ERSPY is supplied. If the next subfield is a selective erasure subfield ESF, a sustain pulse SUSY5 having a large pulse width is supplied at the end of the current selective erasure subfield ESF to turn on the discharge cells. If the next subfield is a selective write subfield (WSF), the erase pulse (ERSPZ) and ramp waveform (RAMP) supplied to the common sustain electrode lines (Z1 to Zm) at the end of the current selective erase subfield (ESF) and A pair of erase pulses ERSPY are supplied to the scan / sustain electrode lines Y1 to Ym. The erase pulses ERSPY and ERSPZ and the ramp waveform RAMP continuously generate a weak discharge so that the wall voltage is uniform in the full screen cells at the initial point of the next selective write subfield WSF. By the erase pulses ERSPY and ERSPZ and the ramp waveform RAMP, uniform wall charges and space charges are accumulated in the discharge cells of the full screen.

FIG. 10 is a diagram illustrating a driving circuit for detecting the setdown level illustrated in FIG. 9.

Referring to FIG. 10, the set-down voltage detection circuit 60 according to the present invention is connected between the driver IC 52 and the ninth switch Q9 so that the ninth switch Q9 based on the point P of FIG. 9 is shown. It serves to control the switching operation of the comparator 62, Zener diode (ZD), and consists of five resistors (R1, R2, R3, R4, R5).

Looking at these configurations, the first resistor R1 formed between the driver IC 52 and the ninth switch Q9 and a voltage connected to the first resistor R1 and passed through the first resistor R1 are distributed. A zener diode ZD connected between the second and third resistors R2 and R3, the second resistor R2 and the third resistor R3 to maintain a constant voltage, and an external voltage source Vcc A fifth node between the fourth and fifth resistors R4 and R5 and the second and third resistors R2 and R3 connected in series between the ground GND to distribute the external voltage Vcc at a constant magnification. (n5) and the sixth node (n6) between the fourth and fifth resistors (R4, R5) is connected to the reference voltage (Vr) and the set-down voltage () from the fifth and sixth nodes (n5, n6) And a comparator 62 for comparing Vd) and outputting a comparison signal. At this time, the setdown voltage Vd at the fifth node n5 is set to have a value near the ground GND by the third resistor R3, and after detecting the setdown voltage Vd, the ninth switch Q9 is turned on. Allows switching from turn-on to turn-off.

As described above, the driving apparatus of the plasma display panel according to the present invention is not limited to the first embodiment, but may be applied to the embodiments of the selective writing method.

In addition, the driving device of the plasma display panel according to the present invention is a driving element required for driving the PDP by changing the connection method between the setup driver and the driver IC between the energy recovery device and the driver IC to supply the scan voltages respectively supplied to the subfields. The number of can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A driving apparatus of a plasma display panel for driving electrodes divided into a reset period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of a selected cell, An energy recovery circuit for recovering energy from the first electrode of the panel, comprising: a setup / down pulse in the reset period, a scan pulse corresponding to selective write to select the cell in the address period, and a scan pulse corresponding to selective erase. A first electrode driver for supplying the first electrode to the first electrode; A scan driver connected to the first electrode driver in a push-pull form to apply a voltage signal to the first electrode; A setup driver for supplying a positive setup signal in the form of a ramp waveform to the first electrode during the reset period; A set-down driver configured to supply a negative waveform signal having a ramp waveform to the first electrode after the positive setup signal is supplied; A first switch connected between the energy recovery circuit and the setup driver and the scan driver for switching a setdown pulse and a sustain pulse; A scan voltage supply unit connected between the scan driver and a scan voltage source to supply a scan voltage to the scan driver in an address period of a selective write and erase field; A second switch connected between the scan voltage supply unit and the setdown driver to perform a control operation of supplying a setdown pulse having a voltage level below ground level and a scan pulse of an address period; And a charge / discharge path connecting the first node formed between the setup driver and the first switch and the second node formed between the scan voltage supply unit and the second switch. The method of claim 1, And an energy recovery circuit for recovering energy from the second electrode of the panel, alternating with the first electrode driver, and having a second electrode driver for supplying a DC voltage to the second electrode during selective writing and selective erasing. Driving device for a plasma display panel, characterized in that. The method of claim 1, And a sustain driver for supplying sustain pulses having different pulse widths to the first electrode during the sustain period. The method of claim 1, And the first electrode driver sets a reference voltage of a scan pulse corresponding to the selective write and a reference voltage of the scan pulse corresponding to the selective erasure differently. The method of claim 1, A first capacitor connected between the energy recovery circuit and a setup voltage source to maintain a constant lamp pulse voltage level and to generate a lamp pulse; And a second capacitor connected between the scan voltage source and the scan driver to maintain a constant scan pulse voltage level and to adjust a voltage supplied to the scan driver. The method of claim 2, The second electrode driver may include: a setdown driver configured to supply a negative waveform setdown signal having a ramp waveform to the second electrode during the reset period; A scan driver for supplying any one of a positive DC voltage and a ground voltage to the second electrode according to the selective write subfield and the selective erase subfield in the address period; A sustain driver for supplying sustain pulses having different pulse widths to the second electrode in the sustain period; And a lamp driver for driving when the next subfield is a selective write subfield to supply a ramp waveform at the end of the sustain period. The method of claim 2, The first and second electrode drivers alternately supply narrow pulses having a pulse width within 1 μm to the first and second electrodes alternately at the end of the sustain period when the next subfield is a selective write subfield. Driving apparatus for a plasma display panel, characterized in that. The method of claim 2, The first electrode driver supplies a square wave pulse having a wider pulse width to the first electrode than a normal sustain pulse supplied in the sustain period of the last time point when the next subfield is a selective erasure subfield. Drive. The method of claim 1, A data driver for supplying one of selective write data for selectively turning on the cell and selective erase data for selectively turning off the cell to the third electrode orthogonal to the first and second electrodes in the address period And a plasma display panel drive device. The method of claim 1, And a set-down voltage detector configured to control the second switch so as to have a voltage level below the ground level. The method of claim 10, The set down voltage detector includes a first resistor connected to the scan driver; Second and third resistors connected to the first resistor to distribute the voltage across the first resistor; A zener diode connected between the second resistor and the third resistor to maintain a rough voltage across the first resistor; Fourth and fifth resistors connected in series between the external voltage source and the ground to distribute the external voltage at a constant magnification; Comparing the voltage applied to the third and fourth nodes derived from the third node between the second and third resistors and the fourth node between the fourth and fifth resistors to control the switching operation of the second switch. And a comparator for outputting a signal.