KR100577762B1 - Device for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a plasma display panel, and more particularly, to a driving apparatus of a plasma display panel.

The present invention relates to an energy recovery circuit for maintaining a potential of a plasma display panel at a sustain voltage or ground, b) a voltage applying unit including a first selector and a second selector for applying a driving waveform to the plasma display panel; And a setup supply unit for applying the rising ramp waveform formed by backing the sustain voltage to the plasma display panel through the second selection unit.

The present invention can simplify the circuit configuration by reducing the expensive switching element and the setup voltage source (Vsetup) by connecting the set-down supply and the scan voltage supply between the sustain voltage back-up and energy recovery circuit and the second voltage interrupter. The production cost can be reduced.

Description

Device for driving plasma display panel {Device for Driving Plasma Display Panel}

1 illustrates a structure of a general plasma display panel.

2 is a circuit diagram of a driving apparatus of a conventional plasma display panel.

3 is a circuit diagram of a driving apparatus of a plasma display panel according to the present invention.

4A is a circuit diagram for explaining formation of a rising ramp waveform according to the operation of the driving apparatus of the plasma display panel of the present invention.

4B is a circuit diagram for explaining formation of a falling ramp waveform, a scan reference voltage waveform, and a write scan waveform according to the operation of the driving apparatus of the plasma display panel of the present invention.

The present invention relates to a plasma display panel, and more particularly, to a driving apparatus of a plasma display panel.

The present invention relates to a plasma display panel, and more particularly, to a driving apparatus of a plasma display panel.

1 illustrates a structure of a general plasma display panel. As shown in FIG. 1, the plasma display panel displays an image including characters or graphics by emitting phosphors by 147 nm ultraviolet rays generated when a He + Xe or Ne + Xe gas is discharged.

The plasma display panel is not only thin and large in size, but also greatly improved in image quality due to recent technology development. In particular, the three-electrode AC surface discharge type plasma display panel lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge. .

The discharge cell of the three-electrode AC surface discharge type plasma display panel includes a scan electrode 30Y and a sustain electrode 30Z formed on the upper substrate 10, and an address electrode 20X formed on the lower substrate 18. do.

Each of the scan electrode 30Y and the sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrodes 13Y, which are formed at one edge of the transparent electrode, respectively. 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 on which the scan electrode 30Y and the sustain electrode 30Z are formed. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 protects the upper dielectric layer 14 from sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The address electrode 20X is formed in the direction crossing the scan electrode 30Y and the sustain electrode 30Z. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed.

The phosphor layer 26 is formed on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 is formed to be parallel to the address electrode 20X to physically distinguish the discharge cells, and prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges.

2 is a circuit diagram of a driving apparatus of a conventional plasma display panel.

The fifth switch Q5 and the seventh switch Q7 are turned on during the setup period. At this time, the sustain voltage Vs is supplied from the energy recovery circuit 40. The sustain voltage Vs supplied from the energy recovery circuit 40 is scanned via the internal diode of the sixth switch Q6, the seventh switch Q7 and the second selector Q15 of the drive integrated circuit 52. Supplied to the electrodes. Thus, the voltage of the scan electrodes rises rapidly to Vs.

On the other hand, since the sustain voltage Vs is supplied to the negative terminal of the second capacitor C2, the second capacitor C2 supplies the voltage of Vs + Vsetup to the fifth switch Q5. The fifth switch Q5 supplies the voltage supplied from the second capacitor C2 to the first node point n1 with a predetermined slope while the channel width is adjusted by the first variable resistor VR1 installed at the front end thereof. do.

The voltage applied with the predetermined slope to the first node point n1 is supplied to the scan electrodes via the seventh switch Q7 and the second selector Q15 of the drive integrated circuit 52. In this case, a rising ramp waveform Ramp-up is supplied to the scan electrodes.

After the rising ramp waveform Ramp-up is supplied to the scan electrodes, the fifth switch Q5 is turned off. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the energy recovery circuit 40 is applied to the first node point n1, so that the voltage of the scan electrodes drops rapidly to Vs.

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set down period. The tenth switch Q10 adjusts the channel width by the second variable resistor VR2 provided at the front end thereof, and writes the voltage of the second node n2 as a write scan voltage (-Vw) (or a setdown voltage source). Descend with a slope. At this time, the ramp ramp down (Ramp-down) is supplied to the scan electrode lines (Y1 to Ym).

Here, the seventh switch Q7 includes an internal diode in a direction different from that of the sixth switch Q6, so that voltages applied to the second node n2 are applied to the internal diode and the fourth switch of the sixth switch Q6. It is prevented from being supplied to the ground potential GND via the internal diode of Q4).

The scan reference voltage supply unit 50 is a third capacitor C3 connected between the reference voltage source Vsc and the second node n2, and an eighth connected between the reference voltage source Vsc and the second node n2. A switch Q8 and a ninth switch Q9 are provided.

The eighth switch Q8 and the ninth switch Q9 are supplied by the control signal supplied from the timing controller during the selective write and erase address periods to supply the voltage of the reference voltage source Vsc to the drive integrated circuit 52. The third capacitor C3 adds the voltage applied to the second node n2 and the voltage value of the reference voltage source Vsc to the eighth switch Q8.

At this time, since the magnitude of the voltage at which the rising ramp waveform reaches and the rising time are long, the current flowing to the fifth switch Q5 also gradually increases to generate heat. Therefore, the fifth switch Q5 must withstand high voltage and high current.

Therefore, the fifth switch Q5 should be an expensive switching element having a very good performance, and the operation of the fifth switch Q5 also adversely affects the switch elements in the vicinity of the vicinity. In addition, a problem arises in that the sixth switch Q6 and the seventh switch Q7 must be separately installed to insulate the fifth switch Q5 and the adjacent switches.

The seventh switch Q7 includes an internal diode in a direction different from that of the sixth switch Q6, so that a voltage applied to the second node n2 is applied to the internal diode and the fourth switch Q4 of the sixth switch Q6. It is prevented from being supplied to the ground potential GND via the internal diode of.

On the other hand, a voltage of Vs is applied to the first node n1 and a write scan voltage (-Vw) is applied to the second node n2 during the set-down period. Here, if the voltage of Vs is set to approximately 180V and the write scan voltage (-Vw) is set to -70V, the seventh switch Q7 should have a breakdown voltage of approximately 250V (300V in consideration of the actual driving voltage margin). That is, in the related art, since the switching element having a high breakdown voltage must be provided as the seventh switch Q7, a manufacturing cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and to provide a driving apparatus of a plasma display panel having a simple configuration, low manufacturing cost, and stable operation.

In order to achieve the above object, the present invention includes a) an energy recovery circuit that maintains a potential of the plasma display panel at a sustain voltage or ground, and b) a first selector and a second selector for applying a driving waveform to the plasma display panel. And a setup supply unit for applying the rising ramp waveform formed by backing the sustain voltage to the plasma display panel through the second selection unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a driving apparatus of a plasma display panel according to the present invention. As shown in FIG. 3, the driving apparatus of the plasma display panel according to the present invention includes an energy recovery circuit 300, a voltage applying unit 320, a setup supply unit 340, a set down supply unit 360, and a scan reference voltage supply unit ( 380 and a scan voltage supply unit 400.

<Energy recovery circuit>

The energy recovery circuit 300 supplies and recovers energy to the plasma display panel C through resonance with the inductor L1, and maintains the potential of the plasma display panel C as the sustain voltage Vs or ground. .

<Voltage application part>

The voltage applying unit 320 includes a first selector Q14 and a second selector Q15 that apply a driving waveform to the plasma display panel. Such a voltage applying unit is a scan driver IC.

〈Setup Supply Unit〉

The setup supply unit 340 applies the rising ramp waveform formed by using the voltage backed up by applying the sustain voltage Vs to the plasma display panel through the second selector Q15 of the voltage applying unit 320.

Since the sustain voltage Vs applied by the energy recovery circuit 300 is applied to the plasma display panel C through the third switch Q3 and the second selector Q15 of the voltage applying unit 320, a setup capacitor. The sustain voltage Vs is applied to one end of (C2). The sustain voltage Vs is also applied to the other end of the second capacitor C2, which is a setup capacitor.

Accordingly, the fifth switch Q5, which is a setup switch, forms the rising ramp waveform using the sustain voltage Vs, rather than forming the rising ramp waveform using the setup voltage source Vsetup as in the related art.

Accordingly, the final driving waveform applied to the plasma display panel C through the second selector Q15 is the plasma display panel through the third switch Q3 and the second selector Q15 of the voltage applying unit 320. It is formed by the superposition of the sustain voltage Vs applied to (C), the sustain voltage Vs, and the rising ramp waveform formed by the fifth switch Q5 which is a setup switch.

As described above, the driving device of the present invention forms a rising ramp waveform by backing the sustain voltage Vs rather than using a separate setup voltage source Vsetup, thereby simplifying the circuit configuration and reducing the manufacturing cost.

Such a setup supply unit 340 includes a first voltage interrupter 345. The first voltage blocking unit 345 is a diode connected in common with one end of the second capacitor C2, which is the setup capacitor, and one end of the fifth switch Q5, which is the setup switch, and the anode end is the sustain voltage. Is connected to (Vs). The first voltage blocking unit 345 connected as described above blocks the voltage applied to the second capacitor C2 from being applied to the sustain voltage Vs.

In addition, the setup supply unit 340 includes a sixth switch Q6 which is a second voltage blocking unit which prevents the voltage applied to the plasma display panel C from being applied to the energy recovery circuit 300 as in the related art.

〈Set Down Supply Part〉

The set-down supply unit 360 applies the falling ramp waveform to the plasma display panel through the second selection unit Q15 of the voltage applying unit 320 by using the write scan voltage (-Vw) after the rising ramp waveform is applied. The set-down supply unit 360 forms a falling ramp waveform having a predetermined slope by the operation of the set-down switch Q10 operating in the active region.

In this case, the set-down supply unit 360 is connected between the energy recovery circuit 300 and the sixth switch Q6, which is a second voltage cutoff unit. Therefore, the seventh switch Q7 which insulates the energy recovery circuit 300 and the set-down supply unit 360 is not required as in the conventional driving apparatus.

<Scan reference voltage supply part>

The scan reference voltage supplier 380 supplies the scan reference voltage to the plasma display panel C through the first selector Q14 during scanning. In this case, the scan reference voltage supply unit 380 includes a third voltage blocking unit 385 for preventing a voltage applied to the plasma display panel C from being supplied to the scan reference voltage Vsc. The third voltage blocking unit 385 is a diode, the anode terminal is connected to the scan reference voltage Vsc, and the cathode terminal is connected to one end of the first selector Q14.

<Scan voltage supply part>

The scan voltage supply unit 400 supplies a write scan voltage (-Vw) for addressing each scan electrode to the plasma display panel C through the second selector Q15 during scanning.

Next, the operation of the driving apparatus in the plasma display panel of the present invention will be described in detail with reference to the drawings.

4A is a circuit diagram for explaining formation of a rising ramp waveform according to the operation of the driving apparatus of the plasma display panel of the present invention. As shown in FIG. 4A, the third switch Q3, the sixth switch Q6, and the second selector Q15 are turned on. As a result, the potential of the plasma display panel C rapidly rises to the sustain voltage Vs.

Subsequently, the fifth switch Q5 which is a setup switch is turned on. A rising ramp waveform is formed according to the operation of the fifth switch Q5 operating in the active region. At this time, since the sustain voltage Vs is also applied to the second capacitor C2, the rising ramp waveform is formed by the sustain voltage C2.

Through such a back voltage process of the sustain voltage, the rising ramp waveform of the driving apparatus of the present invention can be formed without the setup voltage source Vsetup existing in the conventional driving apparatus.

4B is a circuit diagram for explaining formation of a falling ramp waveform, a scan reference voltage waveform, and a write scan waveform according to the operation of the driving apparatus of the plasma display panel of the present invention. As shown in FIG. 4B, after the ramp rising waveform is applied, the tenth switch 10, the sixth switch Q6, and the fifteenth switch Q15 are turned on. Accordingly, the falling ramp waveform is formed by the operation of the tenth switch Q10 operating in the active region.

Next, when the first selector Q14 is turned on, the scan reference voltage supply unit 380 applies the scan reference voltage Vsc to the plasma display panel C through the first selector Q14F. In addition, the scan voltage supply unit 400 applies the write scan voltage (-Vw) to the plasma display panel C by turning on the eleventh switch Q11, the sixth switch Q6, and the fifteenth switch Q15. .

The conventional driving device includes the seventh switch Q7, the eighth switch Q8 and the eighth switch shown in FIG. 9 switch Q9 was required, but the drive device of the present invention does not require such a switch.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

As described above, the present invention simplifies the circuit configuration by reducing the expensive switching element and the set-up voltage source (Vsetup) by connecting the set-down supply unit and the scan voltage supply unit between the sustain voltage back pressure and energy recovery circuit and the second voltage interrupter. Can reduce the production cost.

Claims (9)

An energy recovery circuit for maintaining the potential of the plasma display panel at a sustain voltage or ground; A voltage applying unit including a first selection unit and a second selection unit to apply a driving waveform to the plasma display panel; And And a setup supply unit configured to apply a rising ramp waveform formed by backing the sustain voltage to the plasma display panel through the second selector. The method of claim 1, The setup supply unit includes a setup capacitor and a setup switch, And the sustain voltage is applied through one end of the setup capacitor and a common end with one end of the setup switch. The method of claim 2, And a first voltage blocking unit connected between the sustain voltage and the common terminal. The method of claim 3, The first voltage blocking unit includes a diode, And an anode terminal of the diode is connected to the sustain voltage, and a cathode terminal of the diode is connected to the common terminal. The method of claim 1, The setup supply unit includes a second voltage blocking unit which prevents a voltage applied to the plasma display panel from being applied to the energy recovery circuit. And a set-down supply unit connected between the energy recovery circuit and the second voltage blocking unit to form a falling ramp waveform. The method of claim 1, And a scan reference voltage supply unit configured to supply a scan reference voltage to the plasma display panel through the first selector. The method of claim 6, And the scan reference voltage supply unit includes a third voltage blocking unit which prevents the voltage applied to the plasma display panel from being supplied to the scan reference voltage. The method of claim 7, wherein The third voltage blocking unit includes a diode, And an anode terminal of the diode is connected to the scan reference voltage and a cathode terminal is connected to one end of the first selector. The method of claim 5, The apparatus for driving the plasma display panel further includes a scan voltage supply unit configured to supply a write scan voltage for addressing each scan electrode to the plasma display panel through the second selector during scanning, And the scan voltage supply unit is connected between the energy recovery circuit and the second voltage blocking unit.

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