KR100395908B1 - Method for manufacturing an alignment key of semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing an alignment key of a semiconductor device. The method includes forming an etch stop layer on an upper surface of a semiconductor substrate, etching the etch stop layer and the substrate to form a trench, and filling the trench with a predetermined thickness to form an alignment key. Forming a first photoresist pattern only on the alignment key of the first region in the resultant, forming a second photoresist pattern in which the first photoresist pattern is opened and the alignment key of the second region is opened; The first and second photoresist patterns are etched to simultaneously form the first alignment key and the second alignment key by filling layers having different steps and remaining in the trenches of the first and second regions, respectively. Therefore, according to the present invention, the alignment key used differently for each step can be secured by adjusting the depth etched with respect to each alignment key by double-using and exposing the photoresist when the alignment key is opened. In consideration of the loss of the oxide film, it is possible to maintain a constant alignment key step.

Description

Method for manufacturing an alignment key of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly, to an alignment of a semiconductor device capable of preventing defects of an alignment occurring during an exposure process and ensuring an appropriate overlay value by adjusting the depth of an alignment key that varies with each step during a semiconductor process. It relates to a key manufacturing method.

Photolithography technology and etching process are the most important to improve the integrated density of integrated circuits in semiconductor manufacturing process, and this photolithography technology is required to minimize the pattern and overlap between layers due to the high integration of devices. In response to the improvement of the accuracy, the demand for the exposure apparatus, the resist material, the manufacturing, and the like has been advanced.

Among the various conditions of the photolithography technology, in particular, central management of wafer to wafer and shot to shot (chip to chip) is essential as the exposure apparatus types and exposure methods of the exposure apparatus are diversified. to be. That is, in response to the diversification and complexity of the semiconductor size, it is essential to precisely match the center of the reticle mask and the wafer with the center of the exposure machine with high accuracy. To do this, an alignment key is formed on the wafer to align the position with the reticle. That is, when the laser beam at the alignment portion of the stepper is irradiated and reflected on the alignment key formed on the wafer substrate, the detection unit recognizes the intensity of the interference fringe formed by the unevenness of the alignment key. Alignment is achieved by adjusting the position of the wafer and the reticle.

Meanwhile, the device isolation layer according to the related art is manufactured in the form of LOCOS (LOCal Oxidation of Silicon), but the width of the device isolation region cannot be reduced due to the side diffusion and the bird's beak, and a flat surface cannot be obtained. . Therefore, the LOCOS technology cannot be applied to a large-capacity memory device whose device design dimension is reduced to submicron or less, and thus, a device isolation technology having a shallow trench isolation (STI) structure is used.

After the conventional STI process, since the device isolation layer is formed and then planarized by chemical mechanical polishing (CMP), the step difference on the surface of the semiconductor substrate is removed so that an alignment key for a subsequent photolithography process is not formed.

However, since the ASMLNICON exposure apparatus requires about 1200 kW of the alignment key, there is a concern that the wafer alignment defect and the uniformity against the overlay value may occur during the exposure process.

In the STI process of the prior art, an alignment key is collectively formed into a step required by an exposure apparatus by applying a key open mask that is performed after CMP (Chemical Mechanical Polishing). . However, there was a risk of alignment misalignment in the key open mask that proceeds after the STI CMP, and a problem of etching damage may occur in the alignment key used because the step of about 1200 ms during the key opening is formed without considering the loss of the oxide film. In addition, there is a possibility that alignment defects may occur in some processes because each process has a different depth of alignment key.

An object of the present invention is to use a different coating for each step by adjusting the depth etched for each alignment key by double-coating the photoresist at the time of opening the alignment key in order to solve the problems of the prior art as described above The present invention provides an alignment key manufacturing method of a semiconductor device capable of securing an alignment key and maintaining a constant level of an alignment key in consideration of loss of an oxide film generated at each step.

1 to 8 are process flowcharts sequentially showing an alignment key manufacturing process of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor substrate 12 etching barrier film

14: filling film 18: first photoresist

18 ': first photoresist pattern 20: second photoresist

20 ': second photoresist pattern 24: first alignment key

26: second alignment key 100: first alignment key area

200: second alignment area

In order to achieve the above object, the present invention provides a method for forming an alignment key of a semiconductor device, the method comprising: forming an trench to form an etch stop layer on an upper surface of a semiconductor substrate and etching the etch stop layer and the substrate; Forming an alignment key in the resultant, forming a first photoresist pattern only on the alignment key of the first region in the resultant, opening the first photoresist pattern and opening the alignment key in the second region. Forming a second photoresist pattern, and etching the first and second photoresist patterns, respectively, in the trenches of the first and second regions and filling the first alignment key and the first alignment key by a filling film having different steps. Simultaneously forming two alignment keys.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 8 are process flowcharts sequentially illustrating a process of manufacturing an alignment key of a semiconductor device according to the present invention. In the drawings, reference numeral 100 denotes a first region in which a first alignment key to be used in a process after the gate mask is formed, and 200 denotes a second region in which a second alignment key to be used in a general process is formed.

As shown in FIG. 1, in the STI process, a nitride film is formed as an etch stop layer 12 on the semiconductor substrate 10, which is a wafer, and the etch stop layer 12 and the substrate 10 are etched to form trenches. An alignment key 16 is formed in the first and second regions 100 and 200 by filling a trench with a high density plasma (HDP) oxide film as a filling film 14 at a predetermined thickness, for example, 5000 mW. The alignment key 16 is not a problem for measuring alignment in the exposure equipment because there is a step of the HDP oxide film 14 embedded in the trench. However, in the prior art, since the HDP oxide film 14 is planarized by CMP after the STI process, there is a possibility of causing alignment defects during the exposure process.

Accordingly, the present invention overcomes these problems by the following process.

As shown in FIG. 2, the first photoresist 18 is coated on the entire surface of the resultant formed alignment key 16. In this case, the first photoresist 18 is a negative photoresist. Subsequently, in order to use the alignment key of the first region 100 after the gate mask process in the etching process, the etching amount is reduced by using the negative photoresist. The thickness of the first photoresist 18 of the present invention is preferably as thin as possible, for example, about 1000 kPa or less. This is because the etching depth of the first region 100 and the second region 200 is adjusted differently in the subsequent etching process.

As shown in FIG. 3, the first photoresist 18 is exposed and developed to form the first photoresist pattern 18 ′ only on the alignment key of the first region 100. As a result, the alignment key of the first region 100 is masked by the first photoresist pattern 18 ′. In this case, the width of the first photoresist pattern 18 ′ is adjusted in consideration of the overlay margin to be subsequently exposed.

The reason why the negative photoresist is first coated is to prevent the first photoresist from being melted by the solvents contained in the photoresist during the second coating. If the photoresist is first coated to form a pattern and then the negative photoresist is coated, the positive photoresist formed by the solvent contained in the negative photoresist melts, but when the negative photoresist is formed, the negative photoresist reacts once This is because the pattern is not dissolved in the solvent.

Next, as shown in FIG. 4, the second photoresist 20 is coated on the entire surface of the resultant on which the first photoresist pattern 18 ′ is formed. As shown in FIG. 5, the first photoresist pattern 18 ′ is opened and the alignment key of the second region 200 is opened by exposing and developing the second photoresist 20. 2 photoresist pattern 20 'is formed. In this case, the second photoresist 20 uses a positive photoresist for general key opening. Here, reference numeral 22a, which is not described, indicates an open portion of the first region 100 and 22b represents an open portion of the second region 200. In the present invention, the interval between the second photoresist pattern 20 'is smaller than the width of the first photoresist pattern 18'.

As shown in FIG. 6, the first and second photoresist patterns 18 ′ and 20 ′ are removed by etching. In this case, the etching process is performed until the filling film 14 of the substrate having no trench is exposed. As a result, since the first photoresist pattern 18 ′ is present at the open portion of the first region 100, the depth to be etched is different from that of the second region 200. This etching difference takes into account the thickness of the oxide film (about 500 GPa) to be lost before the gate mask.

As shown in FIG. 7, the first alignment key 24 and the second alignment are formed by filling layers having different steps, respectively, remaining in the trenches of the first and second regions 100 and 200 by the etching process. The keys 26 are formed at the same time.

Then, as shown in FIG. 8, the resultant formed with the first alignment key 24 and the second alignment key 26 is polished by CMP to remove all of the filling film 14 ′ remaining on the etch stop layer 12. Remove

Therefore, the present invention uses the alignment keys 16 of the first and second regions 100 and 200 having a step of about 1200 ms before the gate mask and the first and second regions after the gate mask process. By using the first and second alignment keys 24 and 26 having different steps (1200 μs or more) at 100 and 200, respectively, and considering the loss of oxide film, it is possible to prevent the alignment defect and the uniformity against the overlay value in the exposure equipment. .

As described above, the manufacturing method according to the present invention may form the alignment key step required by the exposure apparatus by introducing a key open mask to etch only the alignment key.

In addition, the present invention performs a key opening process before the CMP in order to prevent alignment defects that occur during the key open mask due to wafer planarization after the STI CMP.

Conventionally, all the alignment keys are kept constant so that the key depths varying for each step may not be satisfied. However, in the present invention, alignment keys varying for each step may be prevented to prevent alignment defects and poor uniformity of overlay values. In addition, the present invention has the effect of producing an alignment key having a predetermined step in consideration of the loss of the oxide film generated for each step in the alignment key manufacturing process.

Claims (4)

In the method of forming the alignment key of the semiconductor element, Forming an etch stop layer on the semiconductor substrate and etching the etch stop layer and the substrate to form a trench; Filling the trench with a predetermined thickness in the trench to form an alignment key; Forming a first photoresist pattern as a negative photoresist only on the alignment key of the first region in the resultant; Forming a second photoresist pattern having a width greater than the width of the photoresist pattern as a positive resist in which the first photoresist pattern is opened and the alignment key of the second region is opened; And Etching the first and second photoresist patterns to simultaneously form a first alignment key and a second alignment key by filling layers having different steps and remaining in the trenches of the first and second regions, respectively. Method for manufacturing an alignment key of a semiconductor device, characterized in that made. delete delete The semiconductor device of claim 1, further comprising, after forming the first alignment key and the second alignment key, grinding the resultant with CMP to remove the filling layer remaining on the etch stop layer. Method of manufacturing the alignment key.