KR100339523B1 - Wide screen data detector - Google Patents

Abstract

PURPOSE: A wide screen data detector is provided to detect the aspect ratio of a program transmitted from a broadcasting station to automatically expand a screen according to the detected aspect ratio. CONSTITUTION: A wide screen data detector includes a synchronous signal separator(101) for separating a synchronous signal from an input composite video signal to output a video composite synchronous signal, a line detection unit(102) for detecting the twenty-third line of a horizontal retrace line period from the video composite synchronous signal, and a data detection unit(100) for detecting wide screen data from the input composite video signal according as the twenty-third line exists or not. The wide screen data detector further includes a clock generator(103) for generating control signals and 5MHz clock and outputting locking data, a start code search unit(104) searches a start code in input lock data according to the control signals and the clock, and a biphase decoder(105) for decoding biphase data from the input lock data. The detector also has a system controller(106) for controlling transmission of the biphase data, a serial/parallel converter(107) for converting the biphase data of the biphase decoder into parallel data, a data storage(108) for storing the parallel data, and an interface(109) for transmitting the data stored in the data storage into a microcomputer.

Description

Optical Screen Data Detector

The present invention relates to the detection of optical screen data of a wideband TV (TV) receiver. More particularly, a 4: 3 program and a 16: 9 program are mixed in a broadcasting station to transmit a 16: 9 or 16: 9 program. The present invention relates to an optical screen data detection device for automatically expanding a screen by detecting 4: 3.

In general, in accordance with the trend of wide-screen TV receivers spreading, a combination of 4: 3 programs and 16: 9 programs are transmitted to each broadcasting station for coexistence of 4: 3 TV receivers and wide TV receivers. Is growing.

Therefore, there is a need to detect whether the program transmitted from each broadcasting station is 16: 9 or 4: 3, and notify the TV receiver, and also there is a need to transmit a status of service improvement of each broadcasting station.

Accordingly, the European Telecommunications Standards Institute (ETSI) has standardized the regulations for wide screen signaling (WSS), and all broadcasters are following these regulations.

According to the optical screen signal (WSS) standard definition, the optical screen signal (WSS) is transmitted on the 23rd line in the 625-line system in the horizontal retrace period, and the amplitude of the signal is 500 mV at the black level.

The optical screen signal WSS is filtered in the form of sin ² and transmitted from the broadcasting station, and the data rate is transmitted at a speed of 5M bps (bps; bit per sec).

The 5 Mbps clock is also locked at line frequency and transmitted.

1 shows the location of optical screen signal (WSS) data on line 23 in the general optical screen signal standard specification.

As shown in FIG. 1, a synchronization signal and a color burst signal are carried in an 11 μs section, and an optical screen signal WSS like a second degree is carried in an 27.4 μs section.

And, as shown in FIG. 2, the data transmitted from the broadcasting station is composed of 137 elements when viewed at 5 MHz clock, the first 29 elements are run-in data for clock recovery, and the next 24 elements. Is transmitted as a start code, and the remaining 84 elements are composed of 14 data bits by encoding 6 elements into 1 bit of biphase data as shown in FIG.

In this way, the receiver should detect the optical screen signal (WSS) indicating whether it is a 4: 3 program or a 16: 9 program from the broadcasting station and automatically expand the screen on the widescreen TV receiver or display the original screen as it is. In the current 4: 3 TV receiver or 16: 9 wide TV receiver, the viewer simply determines whether the 4: 3 signal or the 16: 9 signal is determined by viewing the screen state without the system for detecting the optical screen signal. There was a problem to be switched manually.

Accordingly, an object of the present invention is to provide a broad TV by detecting whether or not an optical screen signal is transmitted at the receiving side when a 4: 3 program and a 16: 9 program are mixed and transmitted from a broadcasting station in view of such a conventional problem. The present invention provides an optical screen data detection apparatus for informing a receiver to automatically expand a screen.

Means for achieving the object of the present invention includes a synchronous separation means for separating the synchronous signal from the input composite video signal to output the video composite synchronous signal, and the optical screen from the synchronous separation means according to the input clock signal Line detection means for detecting the 23rd line of the horizontal retrace period in the video composite synchronous signal carrying the signal, and data detection means for detecting the optical screen data in the input composite video signal depending on whether or not the line detection means detects the 23 lines. And a clock for generating a clock of 5 MHz and output locking data by the control signal for the optical screen data obtained by the data detection means, the control signal for 23 lines obtained by the line detection means, and the video composite synchronization signal of the synchronous separation means. Generation means and control signals obtained from the line detection means and clocks obtained from the clock generation means. A start code search means for searching for the presence or absence of a start code from the input locking data according to the number of blocks; and a pair for deciphering the paired phase data from the input locking data according to the start signal and the clock signal of the start code search means. A phase decoding means, a system control means for controlling transmission of pair data in accordance with a clock signal and a control signal obtained from said start code retrieval means, a pair phase decoding means, and a line detection means, and a pair according to a control signal of said system control means. Serial / parallel conversion means for converting pair data of phase decoding means into parallel data, and data for storing error bits and data by searching for parity errors in parallel data of serial / parallel conversion means by control signals of the system control means. The storage means and the data of the data storage means by the control signal of the system control means. To be achieved as constituted by any interface means for sending to, or less will be described in detail based on the accompanying drawings, the present invention.

4 is a block diagram of the optical screen data detection device according to the present invention. As shown in FIG. 4, a video composite synchronous signal (VCS) is separated from a composite video signal (CVBS) transmitted from a broadcasting station by excluding a video signal. ) And a video composite synchronization signal (VCS) on which the optical screen signal (WSS) from the synchronization separation unit (101) is loaded in accordance with the synchronization separation unit (101) for outputting and the locking clock signal (LCLOCK) input. A line detector 102 which detects the 23rd line of the retrace period and outputs the corresponding color burst blanking signal CBB and line control signal L23, a line control signal L23 of the line detector 102, and The data detector 100 detects and outputs the optical screen data SDATA from the input composite image signal CVBS according to the color burst blanking signal CBB, and the optical screen data SDATA detected by the data detector 100. And line detector (1 According to the line control signal (L23) of the 02), the color burst blanking signal (CBB) and the video composite synchronization signal (VCS) of the synchronization separation unit 101 generates a lock clock (LCLOCK) of 5MHz and lock data (LDATA) According to the clock generator 103 to output the line control signal L23 and the lock clock LCLOCK of the clock generator 103 to output the start code from the input lock data LDATA. Decoding the phase-phased data from the input lock data (LDATA) in accordance with the start code search unit 104 for searching for the presence and the start signal (START) and the lock clock (LCLOCK) of the start code search unit 104 A double phase decoding unit 105 to be output, a lock clock LCLOCK and a double clock BCLK 'input from the start code search unit 104, the double phase decoding unit 105, and the line detection unit 102, respectively; The system controller 106 controls the transmission of the pair data BDATA according to the line control signal L23 and provides the pair clock BCLK to the pair phase decoding unit 105. And a serial / parallel conversion unit 107 for converting pair data BDATA input from the dual phase decoding unit 105 into parallel data according to the clock BCLOCK generated by the system control unit 106; According to the clock (MCLOCK) generated from the system controller 106, the parallel / converted converter 107 converts the parity error from the inputted data, sets the error bits, and compares the current pair data with previous data. The data storage unit 108 compares and outputs the data, and the data of the data storage unit 108 are transmitted to the microcomputer 110 by the transmission signal PL of the system controller 106, and the microcomputer ( And an interface unit 109 for receiving the enable signal EN and the control signal CP from 11O) and clearing the data storage unit 108. In the drawing, reference numeral INT denotes a data storage unit ( 108) the interrupt signal generated The CLR is a clear signal input to the data storage unit 108, and the CTRL is a control signal generated by the interface unit 109 and input to the system controller 106.

Thus, the operational effects of the present invention configured as described in detail with reference to FIGS. 4 to 6 as follows.

First, when the composite video signal CVBS carrying the optical screen signal WSS is transmitted from a broadcasting station and inputted to the data detector 100 and the synchronization separator 101 of the optical screen data detection apparatus, the synchronization separator ( In step 101, the inputted composite video signal CVBS is divided into an image portion and a synchronization level portion, and then the image portion is removed, and only the synchronization level is converted into a video composite synchronization signal (VCS) as shown in FIG. The output is inputted to the clock generator 103 and the line detector 102.

The line detector 102 simultaneously receives a 5 MHz clock LCLOCK line-locked to the video composite synchronization signal VCS from the clock generator 103, and the horizontal synchronization width of the video composite synchronization signal VCS. The 23rd line of the horizontal retrace period is detected by counting the equalization pulse width and the number of the equalization pulses.

At this time, if the bootie 23rd line is detected by the video composite synchronous signal (VCS), the system control unit 106 generates a line control signal L23 having a high level of signal as shown in (b) of FIG. 5 only during the 23rd line. And a color burst blanking signal CBB having a high level of signal level only during the color burst period of the 23rd line, as shown in (c) of FIG. 5 to generate the data detection unit 100 and the start code search unit (CBB). 104).

The data detection unit l00 detects data of the optical screen signal WSS from the composite video signal CVBS transmitted from a broadcasting station and inputs the detected data to the line control signal L23 of the line detection unit 102. The clock generator 103 is supplied and blocked according to the color burst blanking signal CBB.

That is, when the composite video signal CVBS is input, the maximum value and the minimum value of the composite video signal CVBS are detected and the intermediate value of the two values is the reference level. And, if the reference level or more, the high potential is input to the clock generation unit 103 as the optical screen data (SDATA), wherein the line control signal (L23) as shown in (b) of FIG. When the color burst blanking signal CBB as shown in FIG. 5C is input, the optical screen signal data SDATA is not output during the color burst blanking signal CBB.

The clock generator 103 generates a clock of 5 MHz using a phase-locked loop circuit in itself and transmits the clock of 5 MHz to the line frequency of the video composite synchronization signal VCS. Lock to 15.625 KHz) and input the system clock lock clock (LCLOCK) to the start code search unit 104, and also store the data SDATA of the optical screen signal WSS detected by the data detection unit 100. The lock data LDATA as shown in FIG. 6A is input to the start code search unit 104 together with the lock clock LCLOCK only during the 23rd line period by locking the clock LCLOCK.

The start code search unit 104 receives the lock data LDATA and the lock clock LCLOCK from the clock generation unit 103 and searches whether the start code pattern is input while shifting the lock data LDATA. If a start code pattern such as 2 degrees is input, the lock inputted from the clock generation unit 103 together with the start signal START as shown in FIG. 6 (B) indicating that the lock data LDATA is biphasic data. The data LDATA and the lock clock LCLOCK are output to the biphasic decoding unit 105.

When the start signal START shown in FIG. 6B is input to the start code search unit 104, the bi-phase decoding unit 105 synchronizes the lock data LDATA with the input lock clock LCLOCK. After shifting and latching, high / low potentials are input to the serial / parallel conversion unit 107 by the data clock BCLK inputted from the system controller 106 according to the pattern. In addition, the data clock BCLK 'is provided to the system controller 106 to inform.

On the other hand, the system controller 106 generates and outputs the data clock BCLK using the lock clock LCLOCK input from the start code search unit 104, and also latches the pair data BDATA in series. When the clock BCLOCK and the last pair data BDATA are input, the clock MCLOCK is generated to output the data of the data storage unit 108 to the interface unit 109.

Therefore, the serial / parallel converter 107 stores the data by shifting the pair data BDATA input from the upper phase decoding unit 105 in parallel with the clock BCLOCK input from the system controller 106. Input to the unit 108, where 14 bits are input to the data storage unit 108.

The data storage unit 108 checks a parity error in 14 bits of data inputted from the serial / parallel conversion unit 107, sets an error bit, and compares the current input data with previous data. When the update is performed, the update bit is set and the interrupt signal INT is output to the microcomputer 110 at a low potential through the interrupt line to notify the external microcomputer 110 that the updated data has been input and entered. Two bits are added to the data to input 16 bits to the interface unit 109.

The interface unit 109 is configured in the data storage unit 108 according to the enable signal EN and the control signal C and the control signal PL of the system controller 106 input from the microcomputer 110. The input 16-bit data is transmitted to the microcomputer 110.

When the data transfer is completed, a clear signal CLR is generated and inputted to the data storage unit 08.

Accordingly, the data storage unit 108 is in the standby state to reset the current error bit and the update bit and receive new data.

As described in detail above, according to the present invention, when a 4: 3 program and a 16: 9 program from a broadcasting station are mixed and transmitted, the reception side detects the presence or absence of the optical screen signal and automatically outputs it from the widescreen TV receiver. By notifying the user to expand the screen, the dissatisfaction of viewing that requires manual operation by viewing the screen status is eliminated, and the optical screen data can be detected and various processing can be performed using this data. It can be applied to the above and there is an effect that the data processing is simple.

1 is a diagram showing the position of the optical screen data on the 23rd line of the general horizontal retrace period.

2 is a format configuration diagram of the optical screen data of FIG.

3 is a diagram showing a state in which the bit phase data of FIG. 2 is encoded.

4 is a block diagram of the optical screen data detection apparatus of the present invention.

5 is an output waveform diagram of each part of FIG.

(A) is the video composite sync signal extracted from the sync separator,

(B) is the 23rd horizontal line detected by the line detector,

(C) is a color beet blanking signal extracted from the line detection unit.

FIG. 6 is an input / output waveform diagram of a starting code detector of FIG.

(A) is locking data inputted to the start code search unit,

(B) is the start signal of the start code search unit.

**** Explanation of symbols for the main parts of the drawing ****

100: data detection unit 101: synchronization separation unit

102: line detection unit 103: clock generation unit

104: start code search unit 105: dual phase decoding unit

106: system control unit 107: serial / parallel conversion unit

108: data storage unit 109: interface unit

Claims (9)

Decoupling means for separating the synchronous signal from the input composite video signal and outputting it as a video composite synchronous signal, and detecting the 23rd line of the horizontal retrace period from the video composite synchronous signal obtained from the synchronous separating means according to the input clock signal. A line detecting means for detecting the data, and a data detecting means for detecting the optical screen data from the input composite video signal according to whether or not the line detecting means detects 23 lines, and 23 lines obtained from the optical screen data and the line detecting means obtained by the data detecting means. Clock generation means for generating a clock of 5 MHz and output locking data according to the control signal for the video signal and the synchronization signal of the synchronous separation means; and an input lock according to the clock signal obtained from the control signal and the clock generation means obtained from the line detection means. A start code search means for searching for the presence or absence of a start code in the data, and the start code Pair-phase decoding means for decoding the data phased from the input lock data according to the start signal and the clock signal of the search means, and the clock signal and the control signal obtained from the start code search means, the bi-phase decoding means and the line detection means. System control means for controlling the transmission of pair data, serial / parallel conversion means for converting the pair data of the dual phase decoding means into parallel data according to the control signal of the system control means, and the control signal of the system control means. Data storage means for storing parallel data of the serial / parallel conversion means and interface means for transmitting the data of the data storage means to a microcomputer by means of a control signal of a system control means. Device. The optical screen data detection device according to claim 1, wherein the line detecting means detects the 23rd line by counting the horizontal synchronization width, the equalization pulse width, and the number of equalization pulses of the video composite synchronization signal. The optical screen data detecting apparatus according to claim 1 or 2, wherein the line detecting means generates the color burst blanking signal only during the color burst of the 23rd line. The method of claim 1, wherein the data detecting means detects the maximum value and the minimum value of the composite video signal, sets the intermediate value of the two values as the reference level, compares the reference level with the composite video signal, and outputs the resultant data accordingly. Optical screen data detection device. 2. The clock generating means according to claim 1, wherein the clock generating means locks the 5 MHz clock to the line frequency of the input video composite synchronization signal to generate a system clock, and locks the data of the data detecting means to the system clock and outputs only the 23 th line period. Optical screen data detection device, characterized in that. 2. The apparatus of claim 1, wherein the biphase decoding means shifts the data obtained by the start code detecting means six times. 2. The system of claim 1, wherein the system control means uses a lock clock of the start code retrieval means to store the data clock of the dual phase decryption means, a clock to latch the data in parallel, and the data of the data storage means at the last data input. Optical screen data detection device, characterized in that for generating a clock to be provided to the outside. The data storage unit of claim 1, wherein the data storage unit searches for a parity error of data obtained by the serial / parallel conversion unit, sets an error bit, compares the input data with previous data, and notifies the microcomputer as an interrupt signal if the update data is updated. Optical screen data detection device characterized in that. 9. The optical screen data detection apparatus according to claim 1 or 8, wherein the data storage means transmits two bits to the microcomputer by adding two bits to the data when update data is provided from the serial / parallel conversion means.