KR890000591B1 - Receive device at a digital wireless communication - Google Patents

Abstract

The device for receiving mixed transmitting signals of a channel, a different line, an alram, and a remote loop back signal comprises a freq. converting and power amplifying cct. (1), a QPSK modulator (2), decoders (3,3'), clock reproducing and phase fixing ccts. (4,4'), a bidirectional phase generator (5), a clock selector (6), phase detectors (7,15), low-pass filters (8,16), voltage controlled oscillators (9,17), a frame detector (10), freq. converters (11,11'), bit ratio converters (12,12'), bit detector control ccts. (13,13'), a 16-dividing cct. (14), a 15-dividing cct. (18), a desputtering cct. (19), a first (20) and a second (21) desputtering ccts., and a channel bit desputtering cct. (22).

Description

Receiver in Digital Wireless Communication Device

1 is a schematic block diagram of a receiving apparatus according to the present invention.

FIG. 2 is a block diagram showing in detail one channel portion of the receiving device shown in FIG.

3 is a block diagram showing a channel determination circuit section of a receiving apparatus according to the present invention.

* Explanation of symbols for the main parts of the drawings

1: frequency conversion and amplification circuit 2: mapping demodulation circuit

3,3 ': decoding circuit 4,4': clock reproducing and phase fixing circuit

5: bidirectional pulse generator 6: clock extraction circuit

7,15: phase detector 8,16: low pass filter (LPF)

9,17: voltage controlled oscillator 10: frame detection circuit

11,11 ': frequency conversion circuit 12,12': bit rate conversion circuit

13, 13 ': bit detection control circuit 14: 16 division circuit

18: 15 dividing circuit 19: First de-stamping circuit

20: de-stamping control circuit 21: second de-stuffing control circuit

22: Channel Bit De-Stuffing Circuit 23: Data Rate Conversion Circuit

24: light clock circuit 25: lead clock circuit

26,32: data combining circuit 27: logic switch circuit

28: channel identification circuit 29: channel information processing circuit

30: channel determination circuit 31: other short-circuit data output circuit

33: D / A converter 34: Power control signal confirmation circuit

35: power control signal separation circuit 36: power alarm signal determination circuit

37: remote loopback signal determination circuit 38, 39: descrambling circuit

TECHNICAL FIELD The present invention relates to a digital wireless communication device, and more particularly, to channel asynchronous data signals of two channels and distinguish the asynchronous data signals of two channels from the channeled signals. The present invention relates to a receiving apparatus for receiving a transmission signal in which a back loop (Remote Loop Back) signal is combined and demodulating these signals.

In the prior art, the digital wireless communication apparatus uses a synchronous modulation and demodulation circuit, a detection circuit, etc., but requires a separate synchronization arrangement for controlling the transmission time between each transmitting and receiving station. In order to demodulate a digital signal, a signal identification method for demodulating the signal is a method of forming a frame made up of a plurality of input bits. The receiver has jitter components between the sending and receiving stations due to undesired phase shifting and demodulation during the stuffing or destuffing process. In this case, it is difficult to identify information by bit error rate.

In addition, two channels of asynchronous demodulators are used in a digital wireless communication device. The wireless communication device demodulates this signal at a receiving device by using a quaternary PSK (QPSK) signal to identify data signals of two channels. In the process of detecting and comparing this signal, it is known to have a different frequency difference or a difference in a frame pattern with respect to the reference frequencies of two channels. However, "1" or scrambled bit information is known. If "0" is repeated repeatedly, the scramble information is not only difficult to descramble, but also causes a bit error, which causes data error and difficult time control due to frequency difference, resulting in time loss, and generating discrete frequency in the transmitter. There are disadvantages such as limiting the transmission line.

The present invention has been made to solve this disadvantage, so that the asynchronous signal of the two channels have an extra bit (Overhead Bit), respectively, and the high (H) signal in one channel and the other channel as a sync channel identification bit in this extra bit. It has a low (L) signal, and the power control signal generating circuit combines the power alarm signal and the remote loopback signal and detects the frame bits included in the bit string to identify their demodulation signals. This signal is used as a channel switching signal by detecting the channel identification code. Therefore, the logic switch operates to separate the signals of the two channels, and simultaneously extracts the complex power alarm signal and the remote loopback signal from the bit string. While separating the power alarm signal and the remote loopback signal, these signals can be set for a certain time to prevent malfunction due to bit error rate. It is an object of the present invention to provide a receiving device in a digital wireless communication device that determines a control signal by comparing and determining a delay.

Therefore, the transmission apparatus applied to the present invention uses the clock generated by the clock regeneration circuit by inputting the data signal of the channel in an asynchronous state of 1.544 Mb / S as described in detail in the 85-8927 filed by the applicant of the present application. A scrambling circuit for scrambling each channel data, a frequency conversion circuit for generating the scrambling signal as a clock of 1.647 MHz having an accurate phase relationship with a clock reproduced by a phase locked loop (PLL) circuit, and the clock of 1.647 MHz A bit rate change circuit for converting a data rate to 1.647 Mb / S using a read clock divided by two and a write clock divided by two 1.544 MHz; The high (H) signal and the low (L) signal having a period of 155 μs are determined by the frame bits of the "1100" pattern by judging the stuffed bits in the frame generation circuits of the two channels with the increased extra bits. A / D converter which converts analog signal of order wire data having 19.4μs period in one channel to digital signal, A channel display bit of 38.8μs period and 38.8μs period in other channel A mixer for outputting as a data string a mixed control signal having a 38.8 μs period generated from a B channel display bit and a remote monitoring control data bit station control signal generation circuit according to a control signal by a mixer control circuit, respectively; An encoding circuit for outputting a coded data string according to a change of a high (H) signal and a low (L) signal of a data, which includes a mapping modulation circuit for performing a QPSK modulation on the coded data string. And a frequency conversion and power amplification circuit for frequency converting and amplifying the mapping modulated signal.

Accordingly, a main object of the present invention is to detect the frame bits included in the bit string for identifying the signals of the 1.647 Mb / S asynchronous main data T1 of two channels, and to detect the channel identification code synchronized with the channel bits to identify the channel. The channel switching circuit determined by the ratio operates the logic switch to separate the asynchronous main data (T ₁ ) signals of the two channels, and extracts the complex alarm signal and the remote loopback signal from the bit string of the data. It is an object of the present invention to provide a receiving apparatus in a digital wireless communication apparatus which determines a control signal by delaying a predetermined time and then comparing and determining to prevent a malfunction due to a low bit error rate while separating.

Hereinafter, the configuration and the effect of the present invention will be described in detail by the accompanying drawings.

The present invention generates a zero-modulation demodulation circuit (2) for performing QPSK demodulation on the output signal of the frequency conversion and power amplification circuit (1) in the transmission apparatus into channel information bits of I and Q data, and generates a clock of 1.647 MHz. At the same time, clock reproduction and phase fixing circuits 4 and 4 'which remove and output the shake component of this clock signal and I and Q data of each channel are input to generate the original data before encoding. (3), (3 ') and frame detection for reproducing error-free data and stuffed data synchronized with regular "1100" frames inserted in the decoding circuits (3) and (3'). Circuits 10 and 10, and frequency conversion circuits 11 and 11 'generating a clock of 1.544 MHz synchronized with an input clock of 1.647 MHz to lower the data rate to the original 1.544 Mb / S; Using a read clock dividing the 1.544 MHz clock and a write clock dividing the 1.647 MHz The channel identification bits of the I and Q data detected by the bit rate conversion circuits 12 and 12 'and the bit detection control circuits 13 and 13' for converting the data rate to 1.544 Mb / S data. A channel identification circuit 28 for operating the logic switch circuit 27 according to the channel switching signal determined by comparing the signals, and a descrambling circuit 38 for descrambling the main data T ₁ to return to the original signal. 39), a batting line data output circuit 31 which separates the batting line data on the extra bit of the A channel and converts it into an analog signal, and a power control signal for preventing malfunction of international languages due to a low bit error rate. When the input is delayed for a predetermined time, the power control signal confirmation circuit 34 for separating and outputting the remote loopback signal as a power alarm signal.

The receiving device of the present invention configured as described above operates as follows.

Since the receiver of the present invention frequency-converts the data string input from the frequency conversion and power amplifier circuit 1 and applies it to the mapping demodulation circuit 2, the data string input to the mapping demodulation circuit 2 is transferred to the A channel I. The data is demodulated to the B channel Q data, and the A channel I data is supplied to the decoding circuits 3 (3 '), the clock reproduction and phase fixing circuits (4) and (4'). Here, the clock regeneration and phase lock circuit 4 includes a bidirectional pulse generator 5, a clock extraction circuit 6, a phase detector 7, a low pass filter 8 and a voltage controlled generator 37 as shown in FIG. The bidirectional pulse generator 5 performs an OR function at a non-return zero (NRZ) point of the input data in order to extract a clock of 1.64 MHz from the input I and Q data strings. The clock extraction circuit 6 generates a clock pulse of 1.647 MHz with the resonance circuit of 1.647 MHz by the tank circuit in itself. The phase detector 7 generates pulses that are proportional at a 1.647 MHz phase with jitter and a 1.647 MHz phase difference from the voltage controlled generator 9. The low pass filter 8 generates a voltage proportional to the pulse from the phase detector 7. The voltage controlled oscillator 9 generates a frequency in accordance with the voltage of the low pass filter 8. In addition, the decoding circuit 3 has an inverse function of the encoding circuit of the transmitting apparatus and generates original data. The frame detection circuit 10 then extracts a frame of "1100" input from the input data from the voltage controlled generator 9. Accordingly, the output from the clock regeneration and phase lock circuit 4 is separately applied to the frequency conversion circuit 11, and separately to the original data bitrate conversion circuit 12 from the decoding circuit 3, and the frame detection is performed. The frame signal in the form of "1100" from the circuit 10 is individually controlled by the bit detection control circuit 13. The frequency conversion circuit 11 is composed of a 16 division circuit 14, a phase detector 15, a low pass filter 16, a voltage controlled oscillator 17 and a 15 division circuit 18. ) Divides the frequency of the 1.647 MHz pulse from the voltage control generator 9 of the clock regeneration and phase lock circuit 4 by 16 frequency conversion, outputs the signal, and drives the de-stamping control circuit 20 described later. Phase detector 15 converts an input clock pulse of 1.647 MHz into a frequency of 1.544 MHz from the output pulse (1.647 MHz × 1/16) of the 16 division circuit 14 and the 15 division circuit 18 described later. Generates a pulse proportional to the phase difference of the output (1.544 MHz x 1/15). The low pass filter 16 generates a DC voltage proportional to the pulse from the phase detector 15.

The voltage controlled oscillator 17 generates a frequency signal of 1.544 MHz according to the DC voltage control of the low pass filter 16. The 15 division circuit 18 divides the clock pulse of 1.544 MHz into 15 in order to compare the frequency from the voltage controlled oscillator 17 with the output of the 16 division circuit 14. The bit detection control circuit 13 includes the de-stamping control circuit 20, the first de-stuffing circuits Bit ₂ and 19, and the second de-stuffing circuits Bit ₂ and 21 and the channel bit de-stamping. The circuit 22 is configured, and the de-stamping control circuit 20 generates a signal synchronized with the frame to extract the extra bits stuffed into the input data string, thereby controlling all the de-stuffing circuits described later. The first de-stamping circuit 19 extracts and outputs an A-order order wire signal or a B-channel monitoring control signal from the input data string from the decoding circuit 3. The second de-stuffing circuit 21 extracts and outputs the other short circuit signal of the A channel or the power alarm signal of the B channel from the input data string. The channel bit de-stamping circuit 22 detects the channel information bit (I) of the A channel or the channel information bit (Q) of the B channel in the input data string and outputs one bit of the high (H) or low (L) signal. do. In addition, the bitrate conversion circuit 12 is composed of a data rate conversion circuit 23, a light clock circuit 24, a read clock circuit 25 and a data combining circuit 26, the light clock circuit 24 is 1.647MHz Generate the clock frequency by dividing the frequency into two. The lead clock circuit 25 generates a frequency of 1.544 MHz divided by two as a read clock. The data rate conversion circuit 23 converts the light clock and the read clock from the data rate input from the write and read clock circuits 24 and 25 from 1.647 Mb / S to 1.544 Mb / S. The data combining circuit 26 combines the two divided data from the data rate converting circuit 23 in one data string and outputs a channel I signal or a channel Q signal.

Therefore, the de-stamped Bit ₁ signal, the de-stamped Bit ₂ signal, the channel bit signal, and the data output signal of the channel I or Q are outputted from the channels A and B, as shown in FIG. Input to the channel identification circuit 28. Here, the logic switch circuit 27 is a semiconductor switch circuit controlled by the channel identification circuit 28, and the channel identification circuit 28 is for identifying the channel bit I or Q signal, and the channel information processing circuit 29 The channel determination circuit 30 is inputted. In the channel information processing circuit 29, the channel information bit signals of the I and Q data are inputted, and these signals are compared so that the channel due to the bit error rate prevents the misjudgment. Since the (H) signal is supplied to the channel determination circuit 54 by the low (L) signal on the Q channel side, the channel determination circuit 30 composed of a logic circuit generates a channel switching signal in accordance with the channel information of the I and Q data. The logic switch circuit 27 is controlled. The demistered Bit ₁ and Bit ₂ signals are then supplied to the other short-circuit data output circuit 31 via the logic switch circuit 27. The other short-circuit data output circuit 31 is composed of a data combining circuit 32 and a D / A converter 33. The data combining circuit 32 separates the bit ₁ signal and the bit ₂ signal and combines the other short-line data into one. To 51.42 Kb / s of data.

The D / A converter 33 converts the digital mash line bit into analog data and outputs it as a mash line signal. Power control signal confirmation circuit 34 is composed of power control signal separation circuit 35, power alarm signal determination circuit 36 and the remote loopback signal determination circuit 37, power control signal confirmation circuit 34 is Separates the alarm and remote loopback signals from the control bits, delays them for a certain period of time, and rechecks and outputs the control request signal. The power station alarm signal determination circuit 36 extracts and outputs only the power station alarm signal, and the remote loopback signal determination circuit 37 extracts and outputs only the remote loopback signal. In addition, the data string of the A channel is descrambled by the descrambling circuit 39 and output as a digital signal, and the data string of the B channel is descrambled by the descrambling circuit 39 and output as a digital signal.

As described above, the present invention detects a frame included in a bit string to identify two asynchronous main data T ₁ signals, and operates a logic switch according to a channel identification bit synchronized with the main data T ₁ to separate the two main data T ₁ . The circuit consists of circuits for effectively separating service information of extra bits of each channel and preventing malfunction due to low bit error rate.

Claims (2)

A receiving apparatus in a digital radio communication apparatus which demodulates and outputs a signal of a transmitter into two channels of I and Q data in a mapping demodulation circuit, which generates a clock of 1.647 MHz and removes a shake component of the clock signal. Clock reproduction and phase fixing circuits 4 and 4 'to be outputted, and decoding circuits 3 and 3' for inputting I, Q data of each channel to generate original data before encoding; Frame detection circuits 10 and 10 'for error-free reproduction of previous data and stuffed data synchronized with regular "1100" frames inserted in the decoding circuits 3 and 3'; The frequency conversion circuit generates a clock of 1.544 MHz that is synchronized to an input clock of 1.647 MHz to lower the data rate from 1.647 MHz to 1.544 Mb / S, which is synchronized to the input clock. ), (11 ') and a clock divided into two parts at 1.544 MHz Bit rate conversion circuits 12 and 12 'for converting a data rate into 1.544 Mb / S data using a clock, a light clock divided by 1.647 MHz, and a light clock divided by 1.647 MHz, and bit detection A channel identification circuit 28 for operating the logic switch 27 according to the channel switching signal determined by comparing the panel identification bits of the I and Q data detected by the control circuits 13 and 13 'and the main data are decoded. Descrambling circuits 38 and 39 for scrambling to return to the original signal, and other short-circuit data output circuit 31 for converting and outputting the short-circuit data on the extra bits of the A channel into analog signals, and In order to prevent malfunction of the power control by the bit error rate, when the power control signal is input, the power control signal confirmation circuits 34 are configured to separate and output the power alarm signal and the remote loopback signal after a predetermined time delay. D Receiver in digital wireless communication device. 2. The clock regeneration and phase lock circuit (4) according to claim 1, comprising a bidirectional pulse generator (5), a clock extraction circuit (6), a phase detector (7), a low pass filter (8) and a voltage controlled generator (9). And a clock pulse of 1.647 MHz, and the frequency conversion circuit 11 includes a 16 division circuit 14, a phase detector 11, a low pass filter 16, a voltage controlled oscillator 17 and a 15 division circuit 18. The clock pulse of 1.647 MHz is divided by 15/16 to generate a clock pulse of 1.544 MHz, and the bit detection control circuit 13 includes the first de-stamping circuit 19 and the second de-stamping circuit 21. ), The de-stamping control circuit 20 is composed of a channel bit de-stamping circuit 22 for controlling the channel identification information bits mixed on the extra bits in the I and Q data strings, the station control signal and the other short-circuit signal. The bit rate conversion circuit 12 controls the data rate conversion circuit 23, the light clock circuit 24, and the lead clock according to the circuit 20. Circuit 25 consists of a data combining circuit 26, and outputs the main data (T ₁₎ of the respective channels I, Q data, a channel discrimination circuit 28, a channel information processing circuit 29 and the channel discrimination circuit (30 Switch control of the logic switch circuit 27 according to the channel information bit, and the other short-circuit data output circuit 31 is composed of the data combining circuit 3 and the D / A converter 33 to convert the other short-circuit signal. Extraction and output as an analog signal, power control signal confirmation circuit 34 is composed of a power control signal separation circuit 35, power alarm signal determination circuit 36 and the remote loopback signal determination circuit 37 A receiving device in a digital wireless communication device, characterized in that for outputting the alarm signal and the remote loopback signal separated.

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