JPH0478232B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a teletext signal processing circuit, and more particularly, to a teletext signal processing circuit that receives a teletext signal superimposed within a vertical blanking period of a television signal. The present invention relates to a teletext signal processing circuit that processes signals.

(Prior Art) Recently, teletext broadcasting (hereinafter referred to as teletext) has been realized as a new broadcasting service.
Furthermore, as a teletext system, there is a coded transmission system (code system) that has better transmission efficiency than the conventional pattern system.

Unlike regular television programs that are organized by time, teletext repeatedly transmits various information and entertainment programs consisting of text, graphics, and additional sounds, allowing viewers to access the information they want when they want it. This is a new broadcasting system that has made it possible to

The above information such as text and images is multiplexed with the television radio waves (image signals) from the broadcasting station currently being broadcast, and the recipient must prepare a receiving device or adapter that can receive teletext. Then, the user can select and enjoy the desired teletext program from among many teletext programs.

In addition, this teletext signal (text signal packet) is transmitted as a digital signal using the vertical blanking period of the current television video signal, and the receiving device decodes the signal and transmits it to the television. It is now possible to view text programs by converting them into signals, displaying images on the television screen, and generating additional sounds such as music.

(Problems to be Solved by the Invention) By the way, in the above-mentioned teletext broadcast using the encoded transmission method (code method), the continuity of the teletext signal (data) transmitted from the broadcasting station {clock synchronization (CR), Byte synchronization (FC) is guaranteed, and teletext signals are transmitted from broadcasting stations in such a way that the phase of data across the fields of the television signal is not discontinuous. Therefore, the receiving side uses the continuity of the transmitted teletext signal to ensure stable reception.
Various circuit improvements have been made to teletext signal adapters and receivers.

In other words, the sampling clock is obtained from the color subcarrier frequency of the television signal, and byte synchronization is achieved using a framing code, and the data of the teletext signal is obtained by using this sampling clock and further byte synchronization. Digital signal processing is performed. Furthermore, the following relationship exists between the sampling clock frequency (fsp) of the teletext signal, the horizontal scanning frequency (fh) and the color subcarrier frequency (fsc) of the television signal (composite video signal).

fsp=8/5・fsc, fh=(2/455)・fsc However, when broadcasting stations perform synchronization switching,
Due to various conditions of the broadcasting station (for example, when switching broadcast programs on the same channel or changing the relay location), it may not be possible to maintain the above continuity, so on the receiving side, the broadcasting station It is necessary to stably detect that the continuity of the transmitted teletext signal can no longer be maintained by performing synchronization switching on the receiving end, and thereby ensure stable reception from now on.

In order to stably detect that the continuity of the teletext signal transmitted as described above can no longer be maintained, it is necessary to detect the equalization pulse period and generate a stable horizontal synchronization signal that does not include the equalization pulse. need to be detected. Furthermore, in order to detect a stable horizontal synchronizing signal that does not include such equalization pulses, it is necessary to use, for example, a shift register for one horizontal scanning period, which results in a complicated circuit configuration.
There is a problem with high costs.

Therefore, in view of the above-mentioned conventional technology, the present invention provides an equalization pulse for stably detecting when the broadcasting station side performs synchronization switching and the continuity of the transmitted teletext signal can no longer be maintained. To provide a teletext signal processing circuit which can obtain a stable horizontal synchronizing signal containing no signal and has a simple and inexpensive circuit configuration.

(Means for Solving the Problems) In order to achieve the above object, the present invention receives a teletext signal superimposed within the vertical blanking period of a television signal, and processes the teletext signal by signal processing. a teletext signal processing circuit for obtaining a sampling clock having a frequency that is a predetermined multiple of the subcarrier frequency of the television signal; a separating circuit; detecting the leading edge of the synchronizing signal including the equalization pulse; and detecting the period during which the synchronizing signal exists by the output of a counter that starts counting the sampling clock using this detection output; The present invention provides a teletext signal processing circuit characterized in that it includes an equalization pulse period detection circuit that detects an equalization pulse period based on a detection output.

(Function) In the teletext signal processing circuit configured as described above, the leading edge of the synchronization signal including the equalization pulse is detected,
Based on this detection output, the period in which the synchronizing signal exists is detected by the output of a counter that starts counting the sampling clock, and the equalization pulse period is detected by this detection output.

(Embodiment) An embodiment of the teletext signal processing circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block system diagram showing an embodiment of a teletext signal processing circuit according to the present invention.

In the figure, an input terminal 1 is supplied with a received television signal (composite video signal) transmitted from a broadcasting station. A character signal (character signal packet) of the encoded transmission system is superimposed on a specific horizontal scanning period within the vertical blanking period of this television signal.

2 is a subcarrier regeneration circuit, 3 is a 1/5 frequency divider, 4 is a phase comparison circuit, and 5 is a voltage controlled oscillator (hereinafter referred to as
6 is a 1/8 frequency divider, 7 is an equalization pulse removal circuit, 8 is a synchronous separation circuit, and 9 is an output terminal. Furthermore, the 1/5 frequency divider 3, the phase comparison circuit 4, the VCO 5, and the 1/8 frequency divider 6 constitute a phase locked loop (PLL).

The subcarrier regeneration circuit 2 converts the frequency fsc [=
3.58 MHz] (waveform a in FIG. 2) is reproduced and supplied to the 1/5 frequency divider 3. Then, the subcarrier frequency fsc is multiplied by 1/5 to obtain a signal with a frequency of 1/5 fsc (waveform b in FIG. 2), which is supplied to the phase comparator circuit 4.

The phase comparison circuit 4 divides the signal supplied from the 1/5 frequency divider 3 (waveform b in FIG. 2) and the signal supplied from the 1/8 frequency divider 6 which divides the output of the VOC 5 by 1/8. (waveform d in FIG. 2), and if there is a phase difference between them, an error voltage corresponding to the phase difference is generated and supplied to the VCO 5. and,
The VCO 5 uses this error voltage to draw in a new phase signal and output it. Furthermore, the output {waveform c in FIG. 2 (waveform c' in FIG. 4)} output from this VCO 5 is supplied to the equalization pulse removal circuit 7 as a sampling clock with frequency fsp [=5.7MHz]. Ru. The equalization pulse removal circuit 7 also has a frequency fh [=15.7KHz] separated by the synchronization separation circuit 8.
A horizontal synchronizing signal (a waveform obtained by inverting waveform e in FIG. 4) is supplied. Note that this horizontal synchronization signal includes an equalization pulse.

The equalization pulse period detection circuit 7 detects the leading edge of the horizontal synchronization signal (fh) including the equalization pulse, and detects the horizontal synchronization signal by the output of a counter that starts counting the sampling clock (fsp) based on this detection output. The equalization pulse period is detected based on this detection output, and an equalization pulse period detection signal is output to the output terminal 9.

FIG. 3 is a diagram showing a specific circuit of the equalization pulse removal circuit 7, which is a main part of the circuit of the present invention.

In the same figure, terminals 10 and 11 have sampling clocks {second
Waveform c in the figure (waveform c' in Figure 4)} (fsp) and a horizontal synchronizing signal (waveform e in Figure 4) including equalization pulses.
The inverted waveform) (fh) is supplied.

A sampling clock (fsp) supplied via terminal 10 is supplied to the clock terminal of counter 12, and is also supplied to the clock terminals of counter 13 and counter 14. Further, the horizontal synchronizing signal (fh) containing the equalization pulse supplied via the terminal 11 is inverted via the inverter 15 and
The signal is converted to waveform e in the figure and supplied to the clock terminal of the D flip-flop 16. Here, the waveform in FIG. 5 is shown by changing the time axis of the waveform e in FIG. 4, and one pulse of the waveform in FIG. 5 corresponds to the waveform e in FIG. 4.

The D flip-flop 16 is triggered by the rising edge of e() supplied to the clock terminal, and is reset by a waveform f supplied from the output of a NAND circuit 17, which will be described later. The output of the flip-flop 16 is supplied to the D terminal of the D flip-flop 16 and the reset terminal R of the counter 12.

When D flip-flop 16 is triggered, D
The output of flip-flop 16 becomes "L",
This allows the counter 12 to count. Then, the counter 12 starts counting the sampling clock (fsp) of waveforms c and c' supplied to the clock terminal.

The C, D, E output terminals (i.e., 2 ³ , 2 ⁴ , 2 ⁵ output terminals) of the counter 12 have NAND circuits 1
7 is connected and the counter 12 detects a predetermined count value (“28” in this connection),
A detection signal (waveform f in FIG. 4) is output from this NAND circuit 17, and this is applied to the D flip-flop 1.
It is supplied to the reset terminal R of No. 6. Therefore, the output of the D flip-flop 16 becomes "L" for a period corresponding to 28 clock cycles, and
The Q output of the D flip-flop 16 receives a signal (fourth
The waveforms g, g') in the figure and FIG. 5 are obtained.

Here, the waveform g' in FIG. 5 is the waveform e described above.
Similarly to the relationship between waveform e' and waveform e', the waveform g in Fig.
One pulse of g' corresponds to waveform g in FIG.

In addition, the D terminal of the D flip-flop 18 has
The power supply Vcc, which is an "H" signal, is supplied, and the waveform g (g'), which is the Q output of the D flip-flop 16, is supplied to its clock terminal. The D flip-flop 18 is triggered by the waveform g (g') and reset by the waveform i output from the NAND circuit 21, which will be described later, and its Q output (waveform h in FIG. 5) is the D flip-flop of the D flip-flop 19. Supplied to the terminal. Further, the output of the D flip-flop 18 is supplied to the reset terminal R of the counter 13, while the output is supplied to the clock terminal of the D flip-flop 20.

Also, the D flip-flop 19 has a waveform g(g')
It is triggered by the waveform j output from the NAND circuit 22, which will be described later, and its Q output is D.
It is supplied to the D terminal of flip-flop 20. Furthermore, the output of the D flip-flop 19 is supplied to the reset terminal R of the counter 14.

In this way, since the D flip-flops 18 and 19 are connected in a dependent manner, the clock (waveforms g, g') is not input to the flip-flop 19 when the D flip-flop 18 is in the set state (at "H"). It is never set.

Counter 13 counts the sampling clock (waveforms c, c') supplied to its clock terminal only when D flip-flop 18 is in the set state, and counts the sampling clock (waveforms c, c') supplied to its E, F, G, H output terminals (i.e., 2 ⁵ , 2 ⁶ , 2 ⁷ , 2 ⁸ output terminals)
A predetermined count value is detected by the NAND circuit 21, and a detection signal (waveform i in FIG. 5) is output from the NAND circuit 21. The counter 13 continues to count the sampling clocks (waveforms c, c') supplied to the clock terminal until the D flip-flop 18 is reset by this detection signal.

Here, the predetermined count value detected by the above-mentioned NAND circuit 21 is set to a clock count time corresponding to a period greater than th/2 (where th is the horizontal synchronization signal period) and smaller than th. When set (connected as described above) (in this connection, the counter value is 3th/4; "240"), the D flip-flop 19 will not be set during the period when there is no equalization pulse.

Therefore, during the equalization pulse period, after the flip-flop 18 is set, th/2 later,
A clock (waveforms g, g') is input to the clock terminal, and since the D flip-flop 18 is in the set state at this time, the D flip-flop 19 is set.

On the other hand, the D flip-flop 19, the counter 14, and the NAND circuit 22 are constructed in synchronization with the above-described D flip-flop 18, counter 13, and NAND circuit 22, and their operations are the same.

That is, the counter 14 counts the sampling clock (waveforms c, c') supplied to its clock terminal only when the D flip-flop 19 is in the set state, and counts the sampling clock (waveforms c, c') supplied to its E, F, G, H output terminals (i.e., , 2 ⁵ , 2 ⁶ , 2 ⁷ , 2 ⁸ output terminals)
A predetermined count value is detected by a NAND circuit 22 connected to the NAND circuit 22, and a detection signal (waveform j in FIG. 5) is output from this NAND circuit 22. Then, until the D flip-flop 19 is reset by this detection signal, the counter 14 receives the sampling clock (waveform c,
Continue counting c′).

Here, the predetermined count value detected by the above-mentioned NAND circuit 22 is set to th/
2 (where th is the horizontal synchronization signal period),
And set (connect as above) so that the clock count time corresponds to a period smaller than th (in this connection, the count value is 3th/4;
“240”).

Therefore, the Q output of the D flip-flop 19 generates a pulse train (waveform k) that is 3th/4 "H" only during the equalization pulse period.

The Q output (waveform k) of this D flip-flop 19 is supplied to the D terminal of a D flip-flop 20, and the output of the D flip-flop 18 (an inverted waveform of waveform h) is supplied to the clock terminal of this D flip-flop 20. The D flip-flop 20 is triggered by the output of the D flip-flop 18 (inverted waveform of waveform h), and the equalization pulse period detection signal (waveform l) in which only the equalization pulse period is "H" is obtained at its Q output. This is output via the terminal 28.

Further, a NAND circuit 23 is connected to the A, B, D, E, G output terminals (i.e., 2 ^{, 2 2} , 2 ⁴ , 2 ⁵ , 2 ⁷ output terminals) of the counter 13, and this NAND circuit 23 exceeds “O (zero)” and th/
Set the count value of counter 13 to detect a clock count value corresponding to a period smaller than 2 (in this connection, the count value, th/
4; “80”).

The output (waveform m) of the NAND circuit 23 is supplied to the reset terminal R of the RS flip-flop 24 composed of gate circuits 25 and 26, and the set terminal S of this RS flip-flop 24 is supplied with the NAND
The output of the circuit 21 (waveform i) is supplied.

The output terminal of this RS flip-flop 24 becomes "H" during the period of the horizontal pulse.
A gate signal (waveform n) that is "L" is output during the equalization pulse period.

This gate signal (waveform n) and the output of the D flip-flop 16 (waveforms g, g') are connected to an AND circuit 27.
By supplying the horizontal synchronizing signal (waveform o) from which the equalization pulse has been removed, the output terminal of the AND circuit 27 can obtain the horizontal synchronizing signal (waveform o).

As described above, the equalization pulse period detection signal (waveform 1) which is "H" only during the equalization pulse period is obtained at the Q output terminal of the D flip-flop 20.
From the output terminal of the AND circuit 27, a horizontal synchronizing signal (waveform o) from which the equalization pulse has been removed is obtained.
By using this equalized pulse period detection signal and the horizontal synchronization signal from which the equalized pulse has been removed, it is possible to stably detect that the continuity of the teletext signal transmitted from the broadcasting station can no longer be maintained. can.
Furthermore, this detection signal can be supplied to, for example, a teletext receiving device or an adapter control device (signal processing control microcomputer) to perform signal processing control corresponding to this discontinuous state.

(Effects of the Invention) As described above, according to the teletext signal processing circuit of the present invention, the leading edge of the synchronization signal including the equalization pulse is detected, and counting of the sampling clock is started based on this detection output. The period in which the synchronization signal exists is detected by the output of the counter, and the equalization pulse period is detected by this detection output, so the broadcast station side performs synchronization switching etc. based on this detection output, and the teletext signal is transmitted. It is possible to obtain a stable horizontal synchronizing signal that does not include an equalization pulse to stably detect when continuity can no longer be maintained, and there is no need to use a shift register for one horizontal scanning period. It has the advantage of being simple in structure and inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of the teletext signal processing circuit according to the present invention, FIGS. 2, 4, and 5 are signal waveform diagrams of each part of the circuit according to the present invention, and FIG. 2 is a diagram showing a specific circuit of an equalization pulse period detection circuit 7, which is a main part of the inventive circuit. FIG. 1...Input terminal, 2...Subcarrier regeneration circuit, 3
... 1/5 frequency divider, 4 ... Phase comparison circuit, 5 ... Voltage controlled oscillator (VCO), 6 ... 1/8 frequency divider, 7 ... Equalization pulse period detection circuit, 8 ... Synchronization Separation circuit, 9... Output terminal, 10, 11, 28... Terminal, 12, 13, 14... Counter, 15... Inverter, 16, 18, 19, 20... D flip-flop, 17, 21, 22, 23...
NAND circuit, 24...RS flip-flop, 2
5, 26...gate circuit, 27...AND circuit.

Claims (1)

[Scope of Claims] 1. A teletext signal processing circuit that receives a teletext signal superimposed within a vertical blanking period of a television signal and processes the teletext signal, the circuit comprising: a circuit that obtains a sampling clock having a frequency that is a predetermined multiple of the subcarrier frequency from a subcarrier; a circuit that separates a synchronization signal containing equalization pulses from the television signal; and a circuit that separates a synchronization signal containing equalization pulses from the television signal; Equalization pulse period detection that detects the edge and starts counting the sampling clock using this detection output.Detects the period in which a synchronizing signal exists using the output of a counter, and detects the equalization pulse period using this detection output. A teletext signal processing circuit, characterized in that it is provided with a circuit. 2. The teletext signal processing circuit according to claim 1, wherein the circuit for obtaining the sampling clock is constituted by a phase locked loop circuit. 3. The equalization pulse period detection circuit includes a first detection circuit that detects a period larger than th/2 (th is the horizontal synchronization signal period) and smaller than th from the leading edge of the synchronization signal including the equalization pulse; a second detection circuit connected in a dependent manner to the first detection circuit and detecting a period greater than th/2 and less than th from the leading edge of the synchronization signal including the equalization pulse; and the second detection circuit; and a third detection circuit that detects the equalization pulse period by detecting the detection output of the first detection circuit only when the detection output is detected. Broadcast signal processing circuit.