KR100314071B1 - Method for automatically adjusting picture size - Google Patents

Abstract

The present invention relates to a method for automatically adjusting the screen size. In particular, an LCD screen or an LCD monitor automatically adjusts a screen size by correcting a sampling clock so that the video signal of a graphics card having a horizontal width outside the standard does not exceed the screen range. The purpose is to make adjustments. The present invention for this purpose comprises the first step of setting the frequency of the sampling clock to the standard pixel clock value of the current input signal, the second step of finding the start and end point positions of the screen area, and the screen sampled by the current sampling clock. A third step of obtaining the horizontal width ISDCH 'of the sampled screen by counting the number of horizontal pixels of the pixel; and the horizontal width (ISDCH') of the sampled screen, wherein the horizontal width (ISDCH ') corresponds to the number of pixels per line of the actual screen. A fourth step of comparing with the IDCH, and if the horizontal width ISDCH 'of the sampled screen is larger than the horizontal width IDCH of the screen, the sampling clock value is decreased by one step and then the starting point position of the screen area is And repeating the fifth step of returning to the second step of finding.

Description

How to automatically adjust the screen size {METHOD FOR AUTOMATICALLY ADJUSTING PICTURE SIZE}

The present invention relates to a screen display method, and more particularly, to a method for automatically adjusting the screen size in an LCD projector or an LCD monitor.

In general, products such as LCD projectors and LCD monitors that can input PC signals digitally process video signals input in analog or digital form to perform desired signal processing such as screen reduction, enlargement and screen modulation. It is a device that shows video.

In some cases, the digital signal is directly input, but in most cases, an analog video signal is input because a video signal is input from a computer graphics card.

As shown in the block diagram of FIG. 1, a general image display circuit includes an input signal sampling unit 110 for sampling and outputting an analog image signal as a digital signal, and a digital image signal from the input signal sampling unit 110. And a video signal output unit 130 for converting the output signal from the digital video signal processor 120 according to the output method to the screen as an input. .

As shown in the block diagram of FIG. 2, the input signal sampling unit 110 includes a PLL circuit 240 for generating a pixel clock PCLK based on a horizontal synchronization signal Hsync of the input image signal, and the PLL circuit. A clock generator 250 for generating a sampling clock SCK and a data clock DCK based on the horizontal synchronization signal Hsync and the pixel clock PCLK from the circuit 240, and the PLL circuit 240 A clamp generator 210 for matching an input image signal to a predetermined voltage value based on a horizontal sync signal Hsync and a pixel clock PCLK, and an output of the clamp generator 210 in synchronization with the sampling clock SCK. A / D converter 220 for sampling and converting the digital signal into a digital image signal, and a data buffer for temporarily storing the output signal of the A / D converter 220 in synchronization with the data clock DCK to output digital image data. 230.

The operation of such a general technique is described as follows.

When an analog image signal is input, the input signal sampling unit 110 generates a pixel frequency (PCLK; dot clock) based on the horizontal synchronization signal (Hsync) of the image signal, and the clock generator 250. ) Generates a sampling clock SCK of a frequency corresponding to the frequency of the pixel clock PCLK and outputs the same to the A / D converter 220, and simultaneously generates a data clock DCK and outputs the data clock DCK to the data buffer 230. Done.

At this time, if the clamp generator 210 matches the analog image input signal with a predetermined voltage value based on the horizontal sync signal Hsync and the pixel clock PCLK in the PLL circuit 240, the A / D converter 220 may perform the same. In synchronization with the sampling clock SCK in the clock generator 250, the output signal from the clamp generator 210 is sampled and converted into a digital image signal.

Accordingly, the data buffer 230 receiving the digital image signal from the A / D converter 220 is synchronized with the data clock DCK of the clock generator 250 to output digital image data.

That is, the PLL circuit 240 and the clock generator 250 are provided in order to generate the sampling clock SCK at the standard pixel frequency. The clock generator 250 is synchronized with the pixel frequency of the image input signal. Instead, it functions to generate a clock with a clock value set by a command given from a microcomputer (not shown).

The reason is that as shown in the waveform diagram of FIG. 3, since the image signal itself input to the input signal sampling unit 110 is an analog form, pixels are not distinguished, the pixel clock of the input signal is converted by the PLL circuit 240. This is because there is no detectable method.

On the other hand, in order to understand the concept for accurate sampling of the analog video signal, the configuration of the analog video input signal is as shown in FIG.

At this time, if the actual input signal is not in a digital form, a pixel clock (PCLK; dot clock) for displaying a screen in the region shown in FIG. 4 does not mean a signal that is actually input in the form of a clock pulse, but is a frequency band of an image signal. This is a virtual clock pulse that indicates which area it belongs to.

Therefore, since the video image is configured and output in units of pixels in synchronization with the pixel clock corresponding to the frequency of the video signal, the video input signal input to the circuit of FIG. 2 is actually an analog signal. The meaning of the pixel clock PCLK in the PLL circuit 240 may be understood as the same concept as in the actual digital signal.

In FIG. 4, all areas including the black part represent all signal parts between the vertical / horizontal sync signal Vsync (Hsync) including all the blank sections of the image signal, and the light color part represents the actual image. Indicates the screen area that is loaded.

Here, 'ISPH (; Horizontal Start Point of Real Image)' is a numerical value indicating how many pixels of empty space exist until the video input signal starts from the horizontal sync signal Hsync.

'ISPV (Vertical Start Point of Real Image)' is a numerical value indicating how many lines of blank interval exist until the video input signal starts from the vertical synchronization signal Vsync.

'IDCH (; Horizontal Dot Count of Real Image)' is a numerical value representing the horizontal width of the signal of the real image signal among the image input signals, that is, the number of pixels per line.

IDCV (Vertical Dot Count of Real Image) is a numerical value representing the vertical width, that is, the number of lines, of a signal included in an actual video signal among the image input signals.

In this case, when the image signal having the screen region as shown in FIG. 4 is input, the screen region of the image signal sampled by the A / D converter 220 in synchronization with the sampling clock SCK is the same as the example of FIG. 5. ISSPH, ISSPV, ISDCH, and ISDCV generate a sampling clock (SCK) to accurately sample only a screen area signal from an analog image signal, and input an input signal sampling unit (110) for sampling a signal in synchronization with the sampling clock (SCK). This value is a value that is counted based on the sampling clock SCK.

That is, 'ISSPH (; Horizontal Input Sample Start Point)' is a horizontal position at which the actual image starts to be sampled from the analog image signal, and the number of clocks (number of pixels from the horizontal sync signal Hsync) to the position at which sampling is started. ).

'ISSPV (; Vertical Input Sample Start Point)' is a vertical position at which the actual image starts to be sampled in the analog image signal, and represents the number of lines from the vertical sync signal to the position at which the sampling starts.

'ISDCH (; Horizontal Input Sample Dot Count)' is the number of horizontal pixels that sample an actual image from an analog video signal and can be obtained by counting the number of sampling clocks (SCK).

'ISDCV (; Vertical Input Sample Dot Count)' is the number of vertical lines that sample an actual image from an analog image signal, and can be obtained by counting the number of horizontal sync signals Hsync.

Therefore, when it is assumed that the horizontal width IDCH of the actual screen area and the horizontal width ISDCH of the sampled screen area correspond to the image input signal, the frequency of the input signal sampling unit 110 corresponds to the pixel clock PCLK. When the sampling clock SCK is generated and the analog video input signal as shown in FIG. 3B is sampled in synchronization with the sampling clock SCK, the digital video signal processor 120 performs predetermined signal processing and outputs the video signal. The output unit 130 outputs the screen in accordance with the method to be displayed on the screen, thereby displaying the screen of the sampled area as shown in FIG.

However, in the conventional art, when an analog image signal having a horizontal width outside the standard is input, an image displayed on the screen is cut off when sampling is not performed according to the correct screen size.

Accordingly, the present invention improves the size of the screen by correcting the sampling clock so as not to deviate from the range of the screen for the video signal of the graphics card having a horizontal width outside the standard in products such as LCD projectors or LCD monitors to improve the conventional problems It is an object of the present invention to provide a method for automatically adjusting the screen size that is created to automatically adjust.

1 is a block diagram of a general video display circuit.

FIG. 2 is a block diagram illustrating an input signal sampling unit in FIG. 1. FIG.

3 is a waveform diagram showing a sampling position of an image input signal;

4 is an exemplary view showing an actual screen area of a video signal.

5 is an exemplary view showing a sampling screen region of a video signal.

6 is an exemplary view showing a screen area when sampling a standard video signal.

7 is an exemplary view showing a screen area during sampling of an image signal deviating from the standard.

8 is an exemplary view showing a screen area during sampling correction.

9 is an operation flowchart for sampling correction in the present invention.

Explanation of symbols on the main parts of the drawings

210: clamp generator 220: A / D converter

230: data buffer 240: PLL circuit

250: clock generator

In order to achieve the above object, the present invention provides a method for setting a frequency of a sampling clock to a standard pixel clock value of a signal currently input, finding a start point and an end point position of a screen area, and sampling the current sampling clock. Counting the number of horizontal pixels of the screen to obtain a horizontal width (ISDCH ') of the sampled screen, and the horizontal width (ISDCH') of the sampled screen corresponds to the number of pixels per row of the actual screen (IDCH). Greater than), and if the horizontal width (ISDCH ') of the sampled screen is larger than the horizontal width (IDCH) of the actual screen, decrease the sampling clock value by one step and return to finding the starting point position of the screen area. Terminating the correcting operation of the sampling clock when the horizontal width ISDCH 'of the sampled screen matches the horizontal width IDCH of the actual screen; When the horizontal width ISDCH 'of the screen is smaller than the horizontal width IDCH of the actual screen, the sampling start point is set to the starting point value of the standard screen, and the correction operation is terminated.

Hereinafter, the present invention will be described in detail with reference to the drawings.

The circuit for the embodiment of the present invention is configured in the same way as the block diagram of Figs.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

In the present invention, in the sampling of an analog video signal in the A / D converter 220 of FIG. 2, the following two functions are performed to fit an accurate screen size for an image input signal having a horizontal width that is outside the standard. do.

First, in order to sample the correct screen size, as shown in the example of FIG. 6, it is necessary to find the start point position and the end point position of the real image from the analog image input signal.

First of all, assuming that the sampling clock is correct, basically, if the input value displayed on the screen is not black, it is distinguished from the signal size in the blank section. Therefore, from the horizontal sync signal (Hsync) (or vertical sync signal (Vsync)), The point where the non-blank point occurs first is determined as the start position of the actual screen area.

Similarly, the point with the last non-black signal level is determined as the end of the screen.

That is, in the present invention, it is basically assumed that a signal level other than black exists at the start and end points of the screen.

If the size of the screen calculated at the start and end points of the screen obtained by the above method is smaller than the standard size at the current input resolution, a black signal is included in a part of the start / end area of the screen. Set the starting point to the standard value to minimize screen distortion.

Second, when the sampled screen width and the actual screen width do not match, clock correction is performed to sample the correct screen size. In this case, it is assumed that the sampling start point is set to the actual start point of the screen.

4 and 5, when the value of the sampling clock SCK of the input signal coincides with the value of the input pixel clock PCLK, the screen width to be sampled is actually the value of the image input signal. It will be equal to the screen width.

Therefore, when the number of sampling clocks ISDCH is set to the number of pixels per row IDCH, the screen is sampled with the correct size.

However, when the value of the sampling clock SCK does not exactly match the value of the pixel clock PCLK, the sampling is performed by setting the number of sampling clocks ISDCH to the number of pixels per row IDCH. As shown in FIG. 6, the width of the sampled screen is different from the width of the actual screen.

The reason is that the time axis actually occupied when counting the same number of pixels when the value of the pixel clock PCLK, which is a signal generation criterion, and the value of the sampling clock, SCK, which is a reference signal for sampling the image input signal are different from each other. This is because the area (width) of the image is different from each other.

Meanwhile, in the exemplary diagram of FIG. 7, the horizontal width ISDCH of the screen is the number of pixels sampled in the actual screen area based on the sampling clock SCK, and the horizontal width ISDCH ′ of the screen is sampled, as illustrated in FIG. 5. The total number of pixels in the horizontal direction to be sampled when the actual screen area is sampled to the last end point based on the clock SCK.

That is, if the sampling clock SCK coincides with the pixel clock PCLK in the exemplary diagram of FIG. 7, the value of the horizontal width ISDCH 'of the sampled screen matches the value of the horizontal width IDCH of the actual screen. If the sampling clock SCK does not coincide with the pixel clock PCLK and ISDCH '> IDCH, it is necessary to correct the sampling clock SCK.

Therefore, when the value of the sampling clock SCK and the value of the pixel clock PCLK do not coincide exactly, the procedure for sampling the screen with the correct size will be described with reference to the operation flowchart of FIG. 9.

First, the frequency of the clock SCK for sampling the video input signal is set to the standard pixel clock value in the signal frequency band currently input.

Then, the first non-blank point portion, that is, the starting point position ISSPH of the actual screen area, is first found from the horizontal synchronizing signal Hsync (or the vertical synchronizing signal Vsync).

At this time, if the starting point position ISSPH of the actual screen region is found, the screen region is sampled according to the setting of the current sampling clock SCK value, the data value of every pixel is read, and the end position of the actual screen region is simultaneously found.

Accordingly, when the position of the end point is found, the number of sampled pixels in the actual screen area sampled based on the current sampling clock value is calculated by subtracting the start point value from the end point value, that is, the horizontal width (ISDCH ') of the screen. .

At this time, the value of the sampled horizontal width ISDCH 'is compared with the value of the horizontal width IDCH of the actual screen.

Accordingly, when the value of the sampled horizontal width ISDCH 'is smaller than the value of the actual screen IDCH, a part of the left and right sides of the actual screen area is black or the sampling clock SCK is slightly higher. In this case, the screen is not cut off and thus ends without performing the correction function.

If the value of the sampled screen width (ISDCH ') is larger than the value of the actual screen width (IDCH), as shown in the example of FIG. 7, when the screen is sampled by the number of pixels conforming to the standard, Some parts are sampled less and part of the screen is cut off and needs correction.

Therefore, if it is determined that the value of the sampled screen width (ISDCH ') is larger than the value of the actual screen width (IDCH), the value of the sampling clock (SCK) is decreased by one step and then performed again from the initial step of finding the starting point position of the screen. do.

In this case, decrease the sampling clock value by one step and go back to step 2) to find the starting point of the screen area and the value of ISDCH 'and perform the comparison process again.

In other words, since the value of the current sampling clock is the optimal sampling clock value, set the sampling clock value to the currently found value before switching the input signal, and use it only if the screen size is not accurately sampled. The image input signal is optimally sampled by performing a function of finely correcting the values of the sampling clock and the phase in order to create a sampling state.

Therefore, by performing the above process, as shown in the example of FIG. 8, the value of the horizontal width ISDCH 'of the actual screen is equal to the value of the horizontal width IDCH of the video signal.

This process is performed by a microcomputer (not shown) for controlling the circuits of Figs.

As described in detail above, the present invention adds only a program for adjusting the screen size without modifying or adding circuits to find the start position of an actual screen area, obtains an accurate sampling clock value, and uses the sampling clock value to sample an image input signal. This eliminates the possibility of part of the screen being cut off for input signals that are outside of the standard, making it possible to display all screens.

In particular, it is expected that the usefulness of the function of automatically setting the screen position and size in the present invention will be very large considering the actual situation in which most graphics cards do not output a signal conforming to the correct standard.

The present invention is applicable to a sampling circuit provided in an LCD monitor, a projector, a PC-compatible projection TV, a head mounted display (HMD) device, and the like.

Claims (4)

A screen display method of an LCD type display device, comprising: a first step of setting a frequency of a sampling clock to a standard pixel clock value of a signal currently input; a second step of finding start and end positions of a screen area; A third step of obtaining the horizontal width ISDCH 'of the screen sampled by the sampling clock, and a fourth comparing the horizontal width ISDCH' of the sampled screen with the actual width IDCH of the screen; And a fifth step of reducing the sampling clock value by one step and returning to the second step if the horizontal width ISDCH 'of the sampled screen is larger than the horizontal width IDCH of the actual screen. And a sixth step of terminating the correction operation of the sampling clock when the horizontal width (ISDCH ') of the screen matches the horizontal width (IDCH) of the actual screen. The method of claim 1, wherein when the horizontal width ISDCH 'of the sampled screen is smaller than the horizontal width IDCH of the actual screen, the sampling start point is set to a starting point value of the standard screen, and the correction operation is terminated. How to automatically adjust the screen size. The method of claim 1, wherein the starting point of the image is determined from a position where the value of the input signal is not black, and the end point of the image is determined from a portion where the value of the input signal is black. . The method of claim 1, wherein the horizontal width (ISDCH ') of the sampled screen is obtained by counting horizontal pixels of the sampled screen as a difference between a start point and an end point of the screen.