JP2001166755A - Conversion circuit for synchronizing frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert a synchronizing frequency of an input video signal so that a CRT is able to correspond to plural pairs of horizontal and vertical synchronizing frequencies. SOLUTION: This conversion circuit is provided with 1st circuits 54, 55 for generating a write control signal S5W varying correspondingly to the horizontal and vertical synchronizing frequencies of an input video signal S11, and memory 43 in which the input video signal S11 is written. The circuit is provided with a discriminating circuit 52 for discriminating the horizontal and vertical synchronizing frequencies of the input video signal S11, and a PLL 60 for outputting a clock S61 controlled by the discrimination result of the discriminating circuit 52 and varying in frequency. The circuit is further provided with 2nd circuits 54, 55 for forming a discrimination output of the discriminating circuit 52 and a read-out control signal S5R from the clock S61. By supplying the read-out control signal S5R to the memory 43, the circuit reads from the memory 43 the video signal being written therein at an almost constant horizontal synchronizing frequency irrespective of the horizontal synchronizing frequency of the input video signal S11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a circuit for converting a synchronous frequency of a video signal.

[0002]

2. Description of the Related Art In many cases, CRTs are used as display means or display elements in television receivers, personal computers, and the like.

[0003]

By the way, even in the case of television broadcasting, the horizontal and vertical synchronization frequencies are different between the NTSC system, the CCIR system, and the Hi-Vision system.

In a personal computer, depending on the OS, the user can change the display resolution (the number of pixels per screen). Moreover, the resolution is generally 640 dots × 480 lines (dots) until the OS starts, and when the OS starts, the resolution is switched to a value set by the user, for example, 1024 dots × 768 lines. Then, at this time, the horizontal and vertical synchronization frequencies change according to the resolution.

Therefore, among display devices using CRTs, a CRT monitor (CRT display) called a multi-scan monitor or the like is adapted to support a plurality of sets of horizontal and vertical synchronization frequencies.

In this case, as a method in which the CRT monitor responds to a plurality of sets of horizontal and vertical synchronization frequencies, the horizontal and vertical deflection frequencies (scanning frequencies) of the CRT are fixed to a single frequency. Then, the horizontal and vertical synchronization frequencies of the input video signal are converted into horizontal and vertical deflection frequencies of the CRT by performing an interpolation process and a thinning process on the input video signal. The horizontal and vertical deflection frequencies in the CRT are made variable. And the horizontal and vertical deflection frequencies are
Change so as to match the horizontal and vertical synchronization frequencies of the input video signal. It has been known.

In this specification, in order to make the meaning of the "synchronous frequency" clear, the "deflection frequency" is the frequency at which the CRT performs horizontal / vertical deflection. Scan frequency. That is, the horizontal and vertical synchronization frequencies of the video signal supplied to the CRT. Use in the sense of.

However, in the case of the method (1), interpolation or thinning is performed on the input video signal, so that, for example, a point or a line that should be displayed by one dot is represented by two dots on the display screen. It is displayed or blurred. Moreover, such a phenomenon does not occur uniformly, for example, every three dots. As a result, when displaying text characters and graphics, the display quality is significantly reduced.

In addition, a product-sum operation unit or the like is used as hardware in the interpolation processing (a digital filter or the like is also used, but the digital filter is also configured by the product-sum operation unit or the like). The proportion of the sum arithmetic unit in the hardware LSI increases. In addition, since the frequency range of the signal to be handled is wide and high, the operation frequency of the interpolation arithmetic unit also has a very high value, and it is difficult to appropriately cope with the operation frequency.

On the other hand, in the case of the method, since the input video signal is not processed, there is no problem as in the case of the method.

However, in the case of the method (1), since the range of the horizontal deflection frequency is wide, stable horizontal deflection and CR
In order to obtain a high voltage for T, a separate system in which a horizontal deflection circuit and a high voltage generation circuit are separated is fundamental.

At this time, the horizontal deflection circuit must be synchronized with a wide range of frequencies, and it is difficult to design a circuit having good synchronization performance such as jitter performance.
Further, from the characteristics of the horizontal deflection circuit, if the frequency of the horizontal drive pulse suddenly changes, it will result in destruction, so that it is necessary to properly execute a procedure for protection.

Further, when the horizontal deflection frequency changes, the horizontal size of the display screen changes. Therefore, the power supply of the horizontal deflection circuit must be controlled according to the horizontal deflection frequency. Further, it is necessary to switch the horizontal S-shaped correction capacitor according to the horizontal deflection frequency, and for this switching, it is necessary to use an FET having a high withstand voltage as a switch.

Further, since it is necessary to perform tracking adjustment for the frequency characteristic of the horizontal deflection circuit, the circuit and system become more complicated than a deflection circuit having a single horizontal scanning frequency. In addition, since the response when controlling the main deflection and the high voltage changes depending on the horizontal scanning frequency, setting the design parameters is difficult. In some cases, the parameters need to be switched according to the horizontal scanning frequency.

The vertical deflection circuit has the same problem as the horizontal deflection circuit. However, since the frequency of the signal to be handled is much lower than that of the horizontal deflection circuit, the burden is considerably smaller than that of the horizontal deflection circuit. Is easy.

For the above reasons, the following method is generally employed in a multi-scan monitor. However, at that time, the above problems have not been solved.

The present invention has been made in view of the above points,
It is intended to solve the problems as in the case of the methods (1) and (2).

[0018]

According to the present invention, for example, a first circuit for forming a write control signal that changes in synchronization with a horizontal and vertical synchronization signal of an input video signal, and the write control signal, A memory in which the input video signal is written, a discrimination circuit for discriminating the horizontal and vertical synchronization frequencies of the input video signal, and a clock whose frequency changes according to the discrimination result of the discrimination circuit, And a second circuit for forming a read control signal from the discrimination output of the discrimination circuit and the clock, and by supplying the read control signal to the memory, the data is written from the memory to the memory. Video signal that is read at a substantially constant horizontal sync frequency regardless of the horizontal sync frequency of the input video signal. It is an conversion circuit of the synchronization frequency so as to force. So from memory,
Regardless of the horizontal synchronization frequency of the input video signal, a video signal having a substantially constant horizontal synchronization frequency is read.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, an input video signal is written into a frame memory in synchronization with its horizontal and vertical synchronization frequencies, and the written video signal is written in synchronization with the horizontal and vertical deflection frequencies of a CRT. It shall be read.

In this case, when the input video signal is written to the frame memory, it is written for each dot displayed by the video signal. The reading of the video signal from the frame memory is also performed in dot units, and each dot is read without excess or deficiency.

First, consider the horizontal deflection of the CRT as follows. That is, when reading a video signal, as shown in FIG. 3, in each horizontal line, when each dot displayed on the CRT is associated with each cycle of the read clock CLKR (horizontal and vertical blanking periods). ), The total number of dots in one second = the number of dots in one line × the number of lines in one second. Therefore, the frequency fclkr of the read clock CLKR is fclkr = (nhscn + nhblk) · fhdef (1) nhscn: horizontal The number of dots in the video period (horizontal effective scanning period) nhblk: the number of dots in the horizontal flyback period fhdef: the horizontal deflection frequency of the CRT.

When the read clock CLKR is formed by a PLL, fclkr = N · fref (2) N: frequency division ratio of a frequency divider of the PLL fref: frequency of a reference signal of the PLL.

Therefore, from the equations (1) and (2), N = fclkr / fref = (nhscn + nhblk) fhdef / fref (3)

However, actually, since the dividing ratio N is an integer, the equation (3) further satisfies N = int (fclkr / fref + 0.5) = int ((nhscn + nhblk) fhdef / fref + 0.5 ) (4)

Here, int (x) is a function that rounds the value x down to the decimal point to make it an integer. Therefore, int (x + 0.
5) is a value obtained by rounding off the decimal part of the value x. Therefore, the dividing ratio N obtained by the expression (4) is a value obtained by rounding off the decimal part of the dividing ratio N obtained by the expression (3) and converting it to an integer. If the error does not matter, It may be rounded down to an integer.

When the frequency division ratio N obtained by the equation (4) (or the equation (3)) is used, the actually obtained frequency fclkr0 of the read clock CLKR is fclkr0 = int ((nhscn + nhblk) fhdef / fref + 0 .5) fref (5) Therefore, the actual horizontal deflection frequency fhdef0 of the CRT is fhdef0 = 1 / (nhscn + nhblk) · fcrl0 = int ((nhscn + nhblk) fhdef / fref + 0.5)) / (nhscn + nhblk) · fref (6)

The horizontal blanking period thblk in the CRT
0 becomes thblk0 = nhblk / fclkr0 (7).

That is, when the video signal is read from the frame memory, if the frequency division ratio N is set to the value shown by the equation (4), the frequency fclkr0 of the read clock CLKR becomes the value shown by the equation (5). As shown in FIG. 3, each dot of the video can be associated with each cycle of the read clock CLKR, and each dot can be read and displayed without excess or deficiency. At this time, even if the resolution changes, the horizontal deflection frequency fhdef0 of the CRT becomes a value shown by the equation (6), and becomes substantially constant.

On the other hand, the vertical deflection of a CRT is as follows. That is, horizontal deflection frequency = vertical deflection frequency × the number of lines in one vertical period or horizontal synchronization frequency = vertical synchronization frequency × the number of lines in one vertical period (8).

Then, in this case, the horizontal deflection frequency is the value f
Since it is constant at hdef0, when a video signal is read from the frame memory, the vertical cycle of the reading changes according to the number of lines of the video signal to be read. That is, the vertical deflection frequency is determined by the sum of the number of lines of the input video signal and the number of lines in the vertical blanking period.

Therefore, in the video signal supplied to the CRT, the vertical deflection frequency fvdef0 is fvdef0 = fhdef0 / (nhscn + nhblk) (9) nvscn: the vertical video period (vertical effective scanning period) of the input video signal Nvblk: The number of lines in the vertical flyback period. Also, the vertical blanking period tvblk0 in the CRT
Is as follows: tvblk0 = nvblk / fhdef0 (10)

Therefore, the vertical deflection frequency of the CRT also changes. However, as mentioned above, the vertical deflection frequency is much lower than the horizontal deflection frequency,
The burden associated with the vertical deflection circuit is fairly small.

When an image is displayed on a CRT by the above-described method, the image signal is only written and read to and from a frame memory, and processing such as interpolation and thinning is performed. Since the processing is not performed, the display quality is almost degraded.

Further, since it is not necessary to change the horizontal deflection frequency of the CRT even if the resolution is changed, the configuration of the horizontal deflection circuit is simplified, and appropriate horizontal deflection can be performed even if distortion correction or the like is required. it can.

As is apparent from equation (9), when the number of lines nvscn increases, the vertical deflection frequency fvdef0 decreases, and flicker on the CRT becomes noticeable.
Therefore, when the number of lines nvscn is the largest input video signal, the flicker on the CRT is not noticeable.
The horizontal deflection frequency fhdef0 will be set.

According to the present invention, a synchronous frequency conversion circuit capable of coping with a plurality of sets of synchronous frequencies is constructed in accordance with the above-described concept. Hereinafter, one embodiment of the present invention will be described.

In FIG. 1, an input video signal S11 is supplied from an input terminal 11 to a synchronous frequency conversion circuit 14 through an input interface circuit 13. Further, a horizontal and vertical synchronization signal Ssync corresponding to the input video signal S11 is supplied from the input terminal 12 to the synchronization frequency conversion circuit 14 through the interface circuit 13.

In this case, it is assumed that the video signal S11 is a three primary color signal composed of red, green and blue signals.
Although the details of the conversion circuit 14 will be described later, the conversion circuit 14 has a frame memory, and converts the synchronization frequency of the supplied video signal S11 and outputs the video signal S14 according to the above idea. is there.

The output video signal S 14 is supplied to a color CRT 17 through a video drive circuit 16 after processing such as gamma correction is performed in a video control circuit 15.

The conversion circuit 14 outputs a horizontal synchronizing signal H synchronized with the output video signal S14, as shown in FIG.
The sync is taken out and the horizontal synchronization signal Hsync is supplied to the horizontal deflection circuit 21 to form a horizontal deflection current. Then, the horizontal deflection current is supplied to the horizontal deflection coil 22, and the horizontal deflection of the CRT 17 is performed. The horizontal deflection frequency at this time is the value fhdef0.

Further, a horizontal pulse is extracted from the horizontal deflection circuit 21, and the horizontal pulse is supplied to a high voltage generation circuit 23 to form a high voltage. The high voltage is supplied to the CRT 17 as an anode voltage or the like.

Further, the output video signal S
A vertical synchronizing signal Vsync synchronized with 14 is taken out, and this vertical synchronizing signal Vsync is supplied to a vertical deflection circuit 24 to form a vertical deflection current. This vertical deflection current is supplied to a vertical deflection coil 25 to cause a vertical deflection of the CRT 17 to be performed. Is performed.
The vertical deflection frequency at this time is the value fvdef0.

In this case, the synchronous frequency conversion circuit 1
4 is configured, for example, as shown in FIG. That is,
The input video signal S11 from the interface circuit 13 is
The signal is supplied to the A / D converter circuit 42 and A / D-converted into a digital video signal S12. This signal S12 is supplied to the frame memory 43.

The horizontal synchronizing signal Shsyn of the synchronizing signal Ssync is extracted from the interface circuit 13 and supplied to the PLL 51 to form a pulse signal S51 having a frequency corresponding to the dot period of the input video signal S11.
The pulse signal S51 is supplied to the A / D converter circuit 4
2 is supplied as a clock at the time of the A / D conversion, and the input video signal S11 is A / D-converted as described above for each dot when display is performed by the signal S11.

Further, the horizontal and vertical synchronizing signals Ssync from the interface circuit 13 are supplied to the signal discriminating circuit 52, and the horizontal and vertical synchronizing frequencies of the input video signal S11, the temporal positions of the horizontal and vertical video periods, and the like are provided. Is determined, and the determined output is supplied to the timing control circuit 53.

The timing control circuit 53 is constituted by a microcomputer, a DSP or a hard logic. The control circuit 53 calculates the input video signal S11 and the input video signal S11 from the information indicated by the discrimination output of the signal discrimination circuit 52 by calculation or by referring to a look-up table prepared in advance in a nonvolatile memory or the like. The number of dots in one horizontal period of the output video signal S14, the number of lines in the vertical period, the temporal position of the horizontal and vertical video periods (scanning periods), and the like are determined, and the synchronization frequency of the video signal is converted. It forms the data.

The output of the control circuit 53 is supplied to a timing pulse generation circuit 54. PLL5
The pulse signal S51 from the timing pulse generation circuit 5
4 and the horizontal and vertical synchronization signals Ssync from the interface circuit 13 are supplied to the timing pulse generation circuit 54.

Thus, the timing pulse generating circuit 54
, A timing signal S4W is formed. This timing signal S4W is stored in the frame memory 43 as the video signal S12.
Is a signal indicating the timing when writing is performed, and includes a signal indicating the temporal position of the horizontal and vertical video periods.

Then, the timing signal S4W is supplied to the memory controller 55, and the pulse signal S51 from the PLL 51 is supplied to the memory controller 55. Thus, in the memory controller 55, a control signal S5W for writing the input video signal S12 to the frame memory 43 is formed, and this signal S5W is supplied to the frame memory 43.

The control signal S5W includes a write clock, a write address signal, and a write enable signal for writing the video signal S12 in the frame memory 43. These signals are the effective dots of the input video signal S12. And changing in sync with the line.

Therefore, of the input video signal S12, the signal of the signal section serving as the display screen is sequentially written into the frame memory 43 without excess or deficiency for each dot.

The input video signal S12 written in the frame memory 43 is read out in synchronization with the horizontal and vertical deflection of the CRT 17. That is, VCO 61
, An oscillation signal S61 having a predetermined frequency is extracted, and the oscillation signal S61 is supplied to the variable frequency dividing circuit 62. The variable frequency dividing circuit 62 and the VCO 61 constitute the PLL 60 together with the circuits 63 to 65.

From the timing control circuit 53, (4)
The frequency dividing ratio N obtained according to the equation is taken out, the frequency dividing ratio N is set in the variable frequency dividing circuit 62, and the oscillation signal S61 is frequency-divided into a frequency of 1 / N from the variable frequency dividing circuit 62. The divided signal S62 is extracted, and the divided signal S62 is supplied to the phase comparison circuit 63. Further, in the forming circuit 64, a reference signal S64 having a stable frequency fref as a reference is formed, and this signal S64 is supplied to the comparing circuit 63.

In this way, in the comparing circuit 63, the frequency-divided signal S62 is compared in phase with the reference signal S64, and the comparison output is supplied to the loop filter 65 to correspond to the phase difference between the frequency-divided signal S62 and the reference signal S64. A DC voltage having a varying level is extracted. Then, this DC voltage is supplied to the VCO 61 as its control voltage.

Therefore, in the steady state, the signals S62 and S64
Are equal to each other, the expression (2) is satisfied. As a result, the frequency of the oscillation signal S61 of the VCO 61 is set to the frequency fclkr0 expressed by the expression (5).

Then, the signal S61 is supplied to the timing pulse generating circuit 54 as the read clock CLKR to form the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync. Then, these synchronization signals Hsync and Vsync are supplied to the deflection circuits 21 and 24 as described above, and the CRT 17
Are subjected to horizontal and vertical deflection at frequencies fhdef0 and fvdef0.

In the timing pulse generation circuit 54, the signal S61 (read clock CL) supplied thereto is supplied.
KR) in synchronization with the timing signal S4R. The timing signal S4R is a signal indicating the timing when the video signal S13 is read from the frame memory 43.
The signal includes a signal indicating the temporal position of the horizontal and vertical video periods.

Then, the timing signal S4R is supplied to the memory controller 55, and a control signal S5R for reading the output video signal S13 from the frame memory 43 is formed. The signal S5R is supplied to the frame memory 43. The control signal S5R includes, for example, a read clock CLKR for reading the video signal S13 from the frame memory 43, a read address signal, and a read enable signal RDEN, as shown in FIG.

Therefore, as shown in FIG. 3, for example, the horizontal frequency has a value fhd from the frame memory 43 regardless of the horizontal and vertical synchronizing frequencies of the input video signal S12.
An output video signal S13 that is constant at ef0 and whose vertical frequency changes in accordance with the number of lines of the input video signal S11 is extracted.

Then, the extracted video signal S13
Is supplied to the D / A converter circuit 44,
The pulse signal S61 from the VCO 61 is supplied to the D / A converter circuit 44 as a clock for D / A conversion.
Thus, the video signal S13 is output to the D / A converter circuit 44.
In the above, the analog three primary color signals, that is, red, green and blue video signals S14 are D / A converted, and this signal S14 is supplied to the color CRT 17 through the video control circuit 15 and the video drive circuit 16 as described above. .

As described above, according to the display device and the synchronization frequency conversion circuit shown in FIGS. 1 and 2, the horizontal deflection frequency can be set to a constant value fhdef0 for a plurality of sets of synchronization frequencies. Therefore, the horizontal deflection frequency of the CRT 17 becomes constant with respect to a plurality of sets of synchronization frequencies, so that the horizontal deflection circuit 22 only needs to synchronize to the constant frequency fhdef0, and the synchronization performance such as jitter performance is improved.

Furthermore, even if the horizontal synchronizing frequency of the input video signal S11 changes during use, the frequency of the horizontal drive pulse does not suddenly change, so that there is no need to take measures against destruction of the frequency.

Even if the horizontal synchronizing frequency of the input video signal S11 changes, the horizontal deflection frequency fhdef0 does not change, so that there is no need to control the power supply of the horizontal deflection circuit 22. Further, there is no need to switch the horizontal S-shaped correction capacitor in accordance with the horizontal deflection frequency fhdef0, and a high-withstand-voltage FET for the switching is not required.

Further, since the tracking adjustment for the frequency characteristic of the horizontal deflection circuit 22 is not required, the circuit and the system can be simplified. Furthermore, the response when controlling the main deflection and the high voltage changes depending on the horizontal deflection frequency. However, since the horizontal deflection frequency fhdef0 is constant, the design parameters can be easily set and there is no need to switch the parameters.

Further, since no interpolation or thinning is performed on the input video signal S11, when displaying text characters or graphics, the display quality does not deteriorate. Further, since a product-sum calculator required for the interpolation processing is not required, the degree of integration of the LSI can be reduced. Further, since it is not necessary to operate the product-sum operation unit at a very high operating frequency, it is not necessary to cope with such a frequency.

In the above description, the input video signal S11
Is a general analog signal, for example, TDM
In the case of the S format or the LVDS format, the signal may be decoded into a general digital video signal in the interface circuit 13 or the like and then supplied to the frame memory 43.

As described above, since the frequency division ratio N obtained by the equation (4) is a value obtained by converting the frequency division ratio N obtained by the equation (3) into an integer, the horizontal deflection frequency fhdef0 becomes an integer. However, in this case, the reference signal S
By changing the frequency fref of 64, the change of the horizontal deflection frequency fhdef0 can be minimized.

Further, the timing control circuit 53 is
In this case, the CRT 17 can also be used as a DSP for forming a distortion correction signal.

When the horizontal deflection frequency fhdef0 is set so that flicker on the CRT is not noticeable when the number of lines nvscn is the largest in the input video signal, the horizontal deflection frequency fhdef0 may become too high. The horizontal deflection frequency fhdef0 can be switched to several values, and the number n of lines of the input video signal
The value of the horizontal deflection frequency fhdef0 may be switched according to vscn.

List of abbreviations used in this specification A / D: Analog to Digital CCIR: Comite Consultantif international Radiop
honique; International Radio Communication Advisory Committee CRT: Cathode Ray Tube; Cathode ray tube D / A: Digital to Analog DSP: Digital Signal Processor FET: Field Effect Transistor; Field effect transistor LSI: Large Scale integration; Large scale integrated circuit LVDS: Low Voltage Differential Signal NTSC: National Television System Committee; US Television System Committee OS: Operating System PLL: Phase Locked Loop; Phase Locked Loop TDMS: Transition Minimized Differrential Signa
l VCO: Voltage Controlled Oscillator

[0071]

According to the present invention, the horizontal deflection frequency can be set to a constant value for a plurality of sets of synchronization frequencies. Therefore, the horizontal deflection circuit need only be synchronized with the fixed frequency, and the synchronization performance such as the jitter performance is improved. Furthermore, even if the horizontal synchronization frequency of the input video signal changes during use, the frequency of the horizontal drive pulse does not suddenly change, so that no destructive measures against the change in the frequency are required.

Further, even if the horizontal synchronization frequency of the input video signal changes, the horizontal deflection frequency does not change, so that there is no need to control the power supply of the horizontal deflection circuit. Further, there is no need to switch the horizontal S-shaped correction capacitor according to the horizontal deflection frequency, and the FE with a high withstand voltage for the switching is not required.
T is also unnecessary.

Further, since the tracking adjustment for the frequency characteristic of the horizontal deflection circuit is not required, the circuit and the system are simplified. Furthermore, the response when controlling the main deflection and high pressure changes depending on the horizontal deflection frequency,
Since the horizontal deflection frequency is constant, the design parameters can be easily set, and there is no need to switch the parameters.

Further, since no interpolation or thinning is performed on the input video signal, when displaying text characters, graphics, etc., the display quality does not deteriorate. Further, since a product-sum calculator required for the interpolation processing is not required, the degree of integration of the LSI can be reduced. Further, since it is not necessary to operate the product-sum operation unit at a very high operating frequency, it is not necessary to cope with such a frequency.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a system diagram illustrating one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the present invention;

[Explanation of symbols]

11 and 12: input terminal, 13: interface circuit, 14: synchronous frequency conversion circuit, 15: video control circuit, 16: video drive circuit, 17: color CRT, 21
... horizontal deflection circuit, 22 ... horizontal deflection coil, 23 ... high voltage generation circuit, 24 ... vertical deflection circuit, 25 ... vertical deflection coil,
42 ... A / D converter circuit, 43 ... Frame memory,
44: D / A converter circuit, 51: PLL, 52: signal discrimination circuit, 53: timing control circuit, 54: timing pulse generation circuit, 55: memory controller, 56
... PLL, 61 ... VCO, 62 ... variable frequency dividing circuit, 63 ...
Phase comparison circuit, 64: forming circuit, 65: loop filter

Claims (3)

[Claims] A first circuit for forming a write control signal that changes in synchronization with horizontal and vertical synchronization signals of an input video signal; a memory in which the input video signal is written by the write control signal; A discriminating circuit for discriminating the horizontal and vertical synchronizing frequencies of the input video signal;
L, and a second circuit for forming a read control signal from the discrimination output of the discrimination circuit and the clock. By supplying the read control signal to the memory, A synchronous frequency conversion circuit for reading out and outputting a video signal at a substantially constant horizontal synchronous frequency regardless of the horizontal synchronous frequency of the input video signal. 2. A first circuit for forming a write control signal that changes in synchronization with horizontal and vertical synchronization signals of an input video signal; a memory in which the input video signal is written by the write control signal; A discriminating circuit for discriminating the horizontal and vertical synchronizing frequencies of the input video signal; a dividing ratio of the variable frequency dividing circuit is controlled based on a discrimination result of the discriminating circuit; A PLL, and a second circuit for forming a predetermined read control signal from the clock. By supplying the read control signal to the memory, the video signal written in the memory is read from the memory. And the read control signal converts the video signal written in the memory into a horizontal synchronization cycle of the input video signal. Reading is performed at a substantially constant horizontal synchronization frequency regardless of the wave number, and the number of lines per vertical cycle of the video signal read from the memory is made equal to the number of lines per vertical cycle of the input video signal. A conversion circuit for a synchronization frequency that is a signal. 3. The synchronous frequency conversion circuit according to claim 1, wherein the number of dots per line of the video signal read from the memory is equal to the number of dots per line of the input video signal. A synchronous frequency conversion circuit wherein the frequency of the read signal is changed so as to be equal to the number of dots.