JP3214820B2 - Digital image display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video adapter for converting an analog video signal output from a video signal source such as a personal computer into a digital video signal, and more particularly, to a converted digital video signal. And a digital image display device incorporating the video adapter, which compensates for variations in clock frequency, phase timing, and display position.

[0002]

2. Description of the Related Art Conventionally, analog displays for performing raster scan display using a cathode ray tube (CRT) have been widely used as image display devices for personal computers. However, such an analog display is a digital image display device typified by a liquid crystal display, a plasma display, and a flat display for performing a cathode type raster scan display in order to meet recent demands for space saving and low power consumption. Is being replaced by Originally, an image signal generated and processed internally by a personal computer is a digital video signal. Therefore, in order to display on a conventional analog display,
A digital video signal is converted into an analog video signal by a built-in or external video adapter and output.

Therefore, in order to use a digital image display device as a substitute for a conventional analog image display device, an analog video signal output from a personal computer by using a built-in or external video adapter on the digital image display device side. Must be converted to a digital video signal. For convenience, a video adapter used on the personal computer side is called an output video adapter, and a video adapter used on the digital image display device side is called an input video adapter.

FIG. 10 shows a conventional input video adapter VAc which converts an analog video signal input from a personal computer from analog to digital to generate a digital image signal Sidc and display control data Dco of a digital image display device. The configuration is shown. V of video adapter
Ac includes an A / D converter 1, a clock generation circuit 2, a delay circuit 5, a display control circuit 6, and a preset memory 7. The analog image signal Sia and the horizontal synchronization signal Hsync included in the analog video signal are respectively
The signal is input to the A / D converter 1 and the delay circuit 5. The clock generation circuit 2 is constituted by a PLL (phase lock loop) circuit, the display control circuit 6 is constituted by a microcomputer, and the delay circuit 5 is a method using a delay value of each element in the gate array or a delay line or the like. It consists of. The preset data memory 7 stores clock number data D suitable for each image resolution of an analog video signal that may be input from a personal computer.
An image adjustment parameter PI including a set of cl, phase data Dph, and display coordinate data Dco is stored in advance.

[0005] The display control circuit 6 includes a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync based on the input video signal.
By monitoring the frequency of c, the image adjustment parameter P corresponding to the image resolution of the analog image signal Sia
I is read, clock number data Dcl is output to the clock generation circuit 2, phase data Dph is output to the delay circuit 5, and display coordinate data Dco is output to the digital display device.

The delay circuit 5 delays the horizontal synchronizing signal Hsync for a predetermined time based on the phase data Dph to change the phase, and outputs the result to the clock generating circuit 2.

The clock generation circuit 2 is constituted by a PLL circuit, and sets the clock number data Dcl from the display control circuit 6. The clock generation circuit 2 generates a clock CLK having a frequency indicated by the set clock number data Dcl and phase-synchronized with the horizontal synchronization signal Hsync ′ whose phase has been shifted by the delay circuit 5, and performs A / D conversion. Output to the container 1.

The A / D converter 1 converts the analog image signal Sia into a digital image signal Sidc according to the timing of the clock CLK, and outputs the digital image signal Sidc to a display circuit (not shown) of the digital image display device.

As described above, the image display is adjusted by reading out the image adjustment parameter PI corresponding to the image resolution of the analog video signal from the preset data memory 7 and outputting it to the corresponding circuits. That is, the display control circuit 6 controls the phase relationship between the clock CLK and the data in the A / D converter 1 by outputting the phase data Dph (that is, the delay time) to the delay circuit 5.
Further, input means such as a key switch (not shown) connected to the display control circuit 6 is provided so that the user can directly adjust the image adjustment parameters PI.

[0010]

However, in the above-mentioned conventional video adapter VA, the clock, display, and the like of the analog video signal input from the personal computer are used.
And a clock C defined for each phase timing
It is necessary that various data of the image adjustment parameter PI including LK, display coordinate data Dco, and phase data Dph be stored in the preset data memory 7 in advance. Therefore, if an analog video signal having a timing that does not correspond to the image adjustment parameters stored in the preset data memory 7 is input, image adjustment cannot be performed, and
Digital image display devices cannot display images correctly.

Further, the output video adapter on the personal computer side may not be completely standardized, and the timing of the analog video signal output for each video adapter is standard, not to mention between models. In many cases, the timing is slightly different from the timing when it is present.
In such a case, the values of the clock number data Dcl, the phase data Dph, and the display coordinate data Dco read out from the preset data memory 7 by the display control circuit 6 do not correspond to the analog video signal actually input. As a result, there is a problem that a part of an image displayed on the digital image display device is missing or the image fluctuates.

In order to avoid such flickering, jittering, and screen loss of the image, the image adjustment parameter PI is set according to the state of the analog video signal actually input.
, The clock data Dcl, the phase data Dph, and the display coordinate data Dco must be corrected. That is, the user needs to adjust the image adjustment parameter PI stored in the preset data memory 7 in accordance with the actually input analog video signal by using a key switch or the like while watching the image displayed on the display device. There is.
For this adjustment, it is necessary to visually confirm a change in an image in pixel units, which is a difficult operation requiring a great deal of skill. Regarding this image adjustment work, the clock number data Dcl, phase data Dph, and display coordinate data Dco will be described with reference to FIGS. 11, 12, and 13, respectively.

First, adjustment of the clock number data Dcl will be described. An analog video signal input to the video adapter VAc is originally created as a digital signal by a digital circuit such as a personal computer. The original digital video signal is converted into an analog signal using a D / A conversion circuit based on a dot clock synchronized with the horizontal synchronization signal Hsync, and then converted to a display device such as a CRT monitor which receives an analog image signal. Supplying.

FIG. 11 shows a clock CLK generated by the clock generation circuit 2 and a horizontal synchronization signal Hsync. As described above, the dot clock is synchronized with the horizontal synchronization signal Hsync. Based on this clock CLK, the A / D converter 1 sequentially converts the analog image signal Sia into a digital image signal Sidc. Therefore, in order to correctly display an image on a digital image display unit, for example, a liquid crystal monitor, it is necessary to synchronize the phase of the clock CLK with the phase of the horizontal synchronization signal Hsync.

The pulses Pc1 and Pcn of the clock CLK correspond to the pulses Ph1 and Ph2 of the horizontal synchronization signal Hsync. Note that n is an integer and is larger than the horizontal resolution of the analog image signal Sia by a predetermined number. The pulse Ph1 and the pulse Ph2 are located at the beginning and the end of the predetermined one horizontal synchronization period Th, respectively.
Now, assuming that the time difference between the pulse Ph1 and the pulse Pc1 is the start time difference α and the time difference between the pulse Ph2 and the pulse Pcn is the end time difference β, if the start time difference α is equal to the end time difference β, the clock CLK and the horizontal synchronization signal Hsync are synchronized. are doing.

That is, the adjustment of the clock number data Dcl means that the start point time difference α and the end point time difference β are equal.
That is, the difference T (Dcl) between the start time difference α and the end time difference β = α
The clock CLK can be synchronized with the horizontal synchronization signal Hsync by changing the numerical value of the clock number data Dcl so that −β becomes zero. Start point time difference α
Is determined by the user based on the image quality of the image displayed on the monitor. In this way, the deviation T (Dcl) of the preset data Dcl with respect to the actual dot clock is adjusted.

Next, adjustment of the phase data Dph will be described. The delay circuit 5 delays the horizontal synchronization signal Hsync supplied to the clock generation circuit 2 based on the phase data Dph from the display control circuit 6. Clock generation circuit 2
Generates a clock CLK that is phase-synchronized with the delayed horizontal synchronization signal Hsync ′, and outputs the clock CLK to the A / D converter 1.
Output to That is, the phase data Dph is a value indicating how much the horizontal synchronization signal Hsync is delayed,
This value determines the timing at which the A / D converter 1 converts the analog image signal Sia into the digital image signal Sid.

FIG. 12 shows the analog image signal Sia, the ideal clock CLKa, and the actual clock CLKb. The ideal clock CLKa is the analog image signal Sia
Has an ideal timing pulse for A / D conversion correctly. For example, A /
Assuming that the timing for D conversion is determined, the ideal clock CLKa has a rising edge Ea located at the center of the pixel of the analog image signal Sia.

On the other hand, the actual clock CLKb is out of phase with respect to the ideal clock CLKa, and the difference T
(Dph) is a maximum of 180 degrees as shown in FIG.
In this case, the actual clock CLKb has a rising edge Eb at the rising portion and the falling portion of the analog image signal Sia. Therefore, the displayed image fluctuates because the analog image signal Sia is A / D-converted around an unstable portion. In order to solve the fluctuation of the image, the actual clock CLKb is converted to the phase difference T (Dph).
Delays only to bring it closer to the ideal clock CLKa,
Alternatively, it is necessary to modify the phase data T (Dph) so that they become equal. That is, the user determines whether or not the actual clock CLKb is synchronized with the ideal clock CLKa based on the image quality of the image displayed on the monitor. In this manner, the deviation T (Dph) of the preset data Dph from the ideal clock CLKa of the clock CLK is adjusted.

Further, the display coordinate data Dco will be described. FIG. 13 shows a horizontal synchronization signal Hsync, an analog image signal Sia, an ideal image capturing section Cp1, and an actual image capturing section Cp2 for an image on one horizontal line. The display coordinate data Dco is data for determining the capturing section CP of the analog image signal Sia. The analog image signal Sia has a horizontal effective display section HEDP within one synchronization period of the horizontal synchronization signal Hsync. Note that the horizontal effective display section HEDP is a horizontal section in which a pixel to be displayed exists, that is, a pixel located at the leftmost end and a pixel located at the rightmost end of pixels on each horizontal line displayed on the screen. This is a section corresponding to the horizontal distance of. The ideal image capturing section Cp1 matches the horizontal effective display section HEDP of the analog image signal Sia, and all images are displayed.

However, the actual image capturing section Cp2
Corresponds to a predetermined period T (Dc
o) It is shifted only. That is, the image capturing section Cp2
In this case, the capture section CP does not coincide with the horizontal effective display section HEDP, and the screen displays an image in which both ends are missing at intervals of T (Dco). In order to solve the loss of the image, it is necessary to shift the actual image capturing section Cp2 by the length of the period T (Dco) so as to approach the ideal image capturing section Cp1 or to modify the display coordinate data Dco so that the image capturing section Cp1 becomes equal to the ideal image capturing section Cp1. . That is, it is determined whether or not the actual image capturing section Cp2 is synchronized with the ideal image capturing section Cp1.
The user makes a judgment based on the image quality of the image displayed on the monitor. In this manner, the deviation T (Dco) of the preset data display coordinate data Dco of the image capturing section Cp2 with respect to the ideal image capturing section Cp1 is adjusted.

As described above, according to the actual input analog image signal Sia, the clock number data Dcl, the phase data Dph, and the display coordinate data Dco which are manually adjusted by the user while checking the image are automatically converted. It is an object of the present invention to provide a method and means for adjusting to a.

[0023]

In order to achieve this object, a display device according to the present invention receives an analog image input signal from a personal computer and a clock for converting an analog signal into a digital signal at a constant period. An A / D conversion circuit for converting an analog image input signal into a digital signal; a digital video signal output from the A / D conversion circuit; a horizontal synchronization signal and a vertical synchronization signal synchronized with the analog image input signal; An image start / end coordinate detection circuit for detecting a horizontal image start coordinate and a horizontal image end coordinate within a horizontal section by using a clock of the / D conversion circuit as an input, and calculating the A based on the horizontal image start coordinate and the horizontal image end coordinate. A display control circuit for calculating clock number data related to the frequency of the clock of the / D conversion circuit; A clock generation circuit for generating a clock for the A / D conversion circuit. The display control circuit subtracts the horizontal image start coordinate from the horizontal image end coordinate to obtain the analog image input signal. By calculating a clock corresponding to the number of clocks of the A / D conversion circuit so as to match the number of pixels in the horizontal effective display section when digitally generated, the frequency of the clock to be A / D converted is automatically adjusted. A display adjustment device and a display device characterized by adjustment.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows the structure of a digital image display device DD incorporating an input video adapter VA according to an embodiment according to the present invention. The digital image display device DD is roughly divided into an input video adapter VA, an image display unit driving circuit 10, and an image display unit 11.
Consists of The input video adapter VA (hereinafter, referred to as a video adapter VA) is connected to a personal computer, and generates a digital image signal Sid and display device control data Sdc based on an analog video signal supplied from the personal computer. Image display section drive circuit 1
0 is connected to the video adapter VA, and generates a digital image drive signal SD for driving the image display unit 11 based on the digital image signal Sid and the display device control data Sdc supplied from the video adapter VA. The image display unit 11 is connected to the image display unit driving circuit 10 and driven by the digital signal SD to display an image. As the image display unit 11, a device that displays an image using a digital video signal, such as a liquid crystal display, a plasma display, and a cathode type flat display, can be used.

Further, the video adapter VA includes an A / D converter 1, a clock generation circuit 2, an image start / end coordinate detection circuit 3, a display control circuit 4, and a delay circuit connected to each other as shown in FIG. 5 The A / D converter 1, the image start / end coordinate detection circuit 3, and the delay circuit 5 are each connected to a personal computer (not shown), and an analog image signal Sia constituting an analog video signal supplied from the personal computer. , Vertical synchronization signal V
sync and the horizontal synchronization signal Hsync are supplied.

The delay circuit 5 generates a delayed horizontal synchronizing signal Shs by delaying the horizontal synchronizing signal Hsync by a predetermined time Ts based on the phase data Sp supplied from the display control circuit 4 described later in detail. 2 and image start
It is supplied to the end coordinate detection circuit 3.

The clock generation circuit 2 generates a clock Sc having a frequency corresponding to the clock number data Scd supplied from the display control circuit 4 while synchronizing the phase with the delayed horizontal synchronizing signal Shs. And to the image start / end coordinate detection circuit 3.

The A / D converter 1 converts the analog image signal Sia into a digital signal based on the clock Sc, generates a digital video signal Sid, and drives the image start / end coordinate detection circuit 3 and the image display unit. Output to the circuit 10.

The image start / end coordinate detection circuit 3 has an A / D
The digital image signal Sid supplied from the converter 1, the clock Sc supplied from the clock generation circuit 2, the delayed horizontal synchronization signal Shs supplied from the delay circuit 5, and the vertical synchronization signal Vsy supplied from the personal computer.
Based on nc, the horizontal and vertical start and end coordinates of one frame image represented by the digital image signal Sid are detected, and an image information signal Si representing the state of the image is generated. The method of generating the image information signal Si is described in FIG.
, And will be described later in detail.

The display control circuit 4 is connected to the image start / end coordinate detection circuit 3 and receives the supply of the image information signal Si. The display control circuit 4 performs, based on the image information signal Si,
The above-described clock number data Scd, phase data Sp, and display device control data Sdc are generated. The operation of the display control circuit 4 will be described later in detail with reference to FIG.

Next, referring to FIG.
A and the operation of the digital image display device DD will be described. From a personal computer, an analog image signal S
ia, horizontal synchronization signal Hsync, and vertical synchronization signal Vsy
nc, the video adapter VA receives the digital image signal Si by the following procedure.
d and display device control data Sdc.

At step # 100, the digital image signal S
The clock is correctly adjusted by generating the clock number data Scd in the display control circuit 4 according to the state of the id. Then, the process proceeds to the next step # 200. The details of the clock adjustment routine performed in this step will be described later with reference to FIGS.

In step # 200, the display control circuit 4 generates the phase data Sp according to the state of the digital image signal Sid, so that the phase is correctly adjusted. Then, the process proceeds to the next step # 300. The details of the phase adjustment routine performed in this step will be described later with reference to FIG.

In step # 300, the display position is correctly adjusted by generating the display control data Sdc in accordance with the state of the digital image signal Sid. And
Proceed to the next step # 400. The details of the display position adjustment routine performed in this step will be described later with reference to FIG.

In step # 400, step # 400
On the basis of the display device control data Sdc generated in step (1), the image display unit drive circuit 10 performs image signal processing on the digital image signal Sid to generate a drive signal SD for the digital image display device. Go to 500.

In step # 500, an image is displayed in a correct state based on the drive signal SD, and the process ends.

In the above-described flowchart, an example has been described in which the image adjustment is always performed with respect to the digital conversion of the analog image signal Sia.
The image adjustment may be performed when the image resolution is changed. Hereinafter, calculation of the clock number data Scd, phase data SpH, display device control data Sdc, and automatic adjustment will be described in order.

First, the clock adjustment according to the present invention will be described with reference to FIG. 3, FIG. 4, FIG. 6, and FIG.
FIG. 3 shows a horizontal synchronization signal Hsync, an analog image signal Sia, and a clock S corresponding to an image on one horizontal line.
c. As shown in the figure, the image signal Sia preferably has a horizontal effective display section HEDP for displaying an image of one horizontal line in a well-balanced manner during one horizontal synchronization period Th of the horizontal synchronization signal Hsync. That is, in the image signal of one horizontal line, a non-display section TnP before and after and a non-display section TnF without display image data before and after the horizontal effective display section HEDP are included. By synchronizing with the clock pulse of the clock Sc which is the reference of the A / D conversion, the digital image signal Sid obtained by analog-to-digital conversion of the analog image signal Sia is checked in a pixel unit to determine whether or not an image is provided. For each line of the digital image signal Sid, a line image start pixel PS ′ and a line image end pixel PE ′ in the horizontal effective display section HEDP can be detected. The horizontal position of the line image start pixel PS 'is set as the image left end horizontal coordinate HcS', and the horizontal coordinate of the line image end pixel PE 'is set as the image left end coordinate HcE'.

During the horizontal effective display section HEDP, image information of the number of pixels in the horizontal direction according to the resolution of the output video adapter on the personal computer side is provided. That is, the resolution per screen of a standard image output from the VGA video adapter is 640 horizontal pixels × 480 vertical pixels in the graphic mode.
That is, the horizontal effective display section HEDP includes image information of 640 pixels. Thus, the horizontal effective display section H
EDP is the number of horizontal pixels H of the digital image signal Sid.
Can be represented by The process performed in synchronization with the period between the pulses of the clock Sc is called a clock cycle.

In order to convert the analog image signal Sia from analog to digital and generate a digital image signal Sid having image information of 640 pixels in the horizontal effective display section HEDP, the clock Sc is applied to the horizontal effective display section HE.
It is necessary to adjust the value of the clock number data Scd so as to have 640 pulses in the DP.

FIG. 4 shows one screen image FI represented by the image information of the analog image signal Sia. The screen image FI is represented by pixels in a matrix defined by a horizontal effective display section HEDP and a vertical effective display section VEDP. In the figure, pixels located at the upper left corner, upper right corner, lower left corner, and lower right corner of the screen image FI are respectively referred to as a first corner pixel Pa, a second corner pixel Pb, a third corner pixel Pc, and a fourth corner. The pixel is assumed to be Pd. Pixel Pa is the horizontal effective display section HE
The start point of the DP and the vertical effective display section VEDP, that is, the first pixel of the screen image FI. The pixel Pb is located at the end point of the horizontal effective display section HEDP and the vertical effective display section VEDP.
, That is, the last pixel in the first row of the raster image FI. The pixel Pc has a horizontal effective display section HE.
The start pixel of the DP and the end point of the vertical effective display section VEDP, that is, the start pixel of the last horizontal line V of the raster image FI. The pixel Pd is in the horizontal effective display section HEDP.
And the end point of the vertical effective display section VEDP, that is, the last pixel of the last horizontal line V of the raster image FI. A pixel on a vertical line connecting the first corner pixel Pa and the third corner pixel Pc is a start pixel on each horizontal line. The pixel on the vertical line connecting the second corner pixel Pb and the fourth corner pixel Pd is the end pixel of each horizontal line.

Now, it is assumed that the analog image signal Sia has the pixel value of the first corner pixel Pa or the third corner pixel Pc, the second corner pixel Pb or the fourth corner pixel Pd, that is, represents an image. A pixel having a pixel value representing this image is called an effective display pixel. The display control circuit 4 gives the clock generation circuit 2 an appropriate clock value Pcv as an initial value of the clock number data Scd. The image start / end coordinate detection circuit 3 sets the leftmost effective display pixel among the pixels of the screen image FI of the digital image signal Sid output from the A / D converter 1 as the image left end pixel PS, An effective display pixel located at the right end is detected as an image right end pixel PE.

Now, let the coordinates of the pixel PS at the left end of the image be (HcS,
VcS) and the coordinates of the pixel PE at the right end of the image are (HcE, Vc
E), the coordinates of the line image start pixel PS ′ are (HcS ′,
VcS ′) and the coordinates of the line image end pixel PE ′ can be represented as (HcE ′, VcE ′). The image left end pixel PS means that among all the line image start pixels PS 'of the one-screen image FI, the value of the horizontal coordinate HcS' is the vertical line Pa-Pc regardless of the value of the vertical coordinate VcS '.
It means the pixel located above or closest to it. Similarly,
The image right end pixel PE means that among all the line image end pixels PE 'of one screen image FI, the value of the horizontal coordinate HcE' is the horizontal position Hc regardless of the value of the vertical position VcE '. It means a pixel on or closest to Pd. The horizontal section of the image left end pixel PS and the image right end pixel PE obtained in this way is called a horizontal image display section HP. The distance of the horizontal image display section HP can be represented by | HcS−HcE |. In the digital image signal Sid, the horizontal image display section HP and the horizontal effective display section HEDP must be the same.

The image start / end coordinate detecting circuit 3 detects a line image start pixel PS 'and a line image end pixel PE' detected for each horizontal line Vc during the processing according to the present invention.
Are stored as temporary coordinates of the image left end pixel PS and temporary coordinates of the image right end pixel PE at any time.

The operation of the clock adjustment routine of step # 100 shown in FIG. 2 will be described with reference to the flowchart shown in FIG.

When the clock adjustment routine starts, first, in step S110, the system is reset. The initialization in step S110 is performed in step S10.
2 and the subsequent step S104 are performed as follows.

In step S102, the image start / end coordinate detection circuit 3 extracts the number of vertical pixels V and the number of horizontal pixels H indicating the image resolution of the digital image signal Sid. Next, following the vertical synchronization signal Vsync, detection of a line image start pixel PS ′ and a line image end pixel PE ′ is started for a pixel on a horizontal line that appears first. That is, the input of the pulse Ph1 of the horizontal synchronizing signal Hsync shown in FIG. 3 sets the vertical position parameter Vc, which indicates the number of the line from the first horizontal line, to 1, as a start signal. Accordingly, the vertical position parameter Vc is an integer equal to or less than the number V of pixels in the vertical direction, and the horizontal position parameter Hc is an integer equal to or less than the number of clock pulses corresponding to the horizontal synchronization period Th. Then, the process proceeds to the next step S104.

In step S104, first, an initial value Pcv is set in the clock number data Scd, and the value of a clock counter PNC which counts the number of pulses of the clock Sc in synchronization with the clock Sc is reset to zero and stored in a register. The coordinate values of the left image pixel PS and the right pixel PE of the image and the coordinate values of the line image start pixel PS ′ and the line image end pixel PE ′ are reset to zero. That is, HcS, VcS, HcE, VcE, Hc
The values of S ', VcS', HcE ', and VcE' are set to zero. Further, the digital image signal Sid converted from the analog image signal Sia by the A / D converter 1 is input to the image start / end coordinate detection circuit 3. Thus, after the initialization in step S110, the process proceeds to the next step S120.

In step S120, it is checked whether each pixel in the digital image signal Sid has an image in the order of raster scan for each horizontal line Vc, and after detecting a horizontal image display section HP, Proceed to the next step S170. The operation of detecting the horizontal image display section HP in this step will be described below with reference to FIG.

In step S122, the clock counter PNC is incremented by 1 in synchronization with one of the pulses of the clock Sc. After the first pixel on the current horizontal line of the digital image signal Sid is set as an object to be determined as an effective display pixel, the process proceeds to the next step S124.

In step S124, the pixel to be determined is
It is determined whether the pixel on this line is the first effective display pixel, that is, the line image start pixel PS ′. As described above, during the previous non-display section TnP after the pulse Ph1,
Since there is no image to be displayed, NO is determined. Furthermore,
Even if the pixel is in the horizontal effective display section HEDP, for example, if the currently detected first corner pixel PA is not an effective display pixel, it is determined as NO and the process proceeds to step S126.

In step S126, the horizontal synchronizing signal Hs
It is determined whether the pulse Ph2 next to the sync is detected. That is, it is determined whether or not the determination of the line image start pixel PS ′ has been performed for all the pixels on the current horizontal line Vc based on whether or not the pulse Ph2 is detected. The pixel P (PNC, Vc) currently being processed is
If it is not the end of the current line, since the pulse Ph2 is not detected, it is determined to be NO and the process returns to step S122. In this way, the determination is continued as long as a pixel that has not been determined for the line image start pixel PS ′ remains in the current line Vc.

In step S122, similarly to the previous clock cycle, the clock counter PNC is incremented again in synchronization with the pulse of the clock Sc, and the next pixel is set as a processing target. Thus, in step S124, the line line image start pixel P
The processing of steps S122, S124, and S126 is repeated every clock cycle until S ′ is detected or the determination of all pixels on the current horizontal line is completed in step S126.

On the other hand, if YES in step S124, that is, if the line image start pixel PS 'is detected, the flow advances to step S128. This is because it is no longer necessary to detect the line image start pixel PS ′ for undetermined pixels remaining on the current line.

In step S128, the current horizontal line Vc
Is set as the line image start pixel PS ′. That is, the clock counter PN at that time is added to the line image start horizontal coordinate HcS ′.
The value of C is set. Then, the next step S130
Proceed to.

In step S130, the aforementioned step S
Similarly to 122, the clock counter PNC is incremented in synchronization with the next pulse of the clock Sc,
Further, the next pixel is set as a processing target. Then, the process proceeds to the next step S132.

In step S132, the pixel to be determined is
The pixel next to the last effective display pixel PE 'on the line, that is, the line image end pixel P (HcE' + 1, V
c) is determined. For example, the current detection target P
If (PNC, Vc) is an effective display pixel, it is determined as NO and the process proceeds to step S134.

In step S134, step S126
Similarly, the next pulse Ph2 of the horizontal synchronization signal Hsync
The presence or absence of the detection is determined. However, in this step, it is determined whether or not a pixel that has not been subjected to the line image end pixel PE ′ detection process remains on the current line. Therefore, if the pixel P (PNC, Vc) to be processed at present is not the last pixel of the current line, it is determined as NO and the process returns to step S130. In this way, whether the line image end pixel PE 'is detected in step S132 or whether the line image end pixel PE'
Steps S130, S132, and S13 are performed until the end of the determination for all the pixels on the current line is confirmed in.
Step 4 is repeated every clock cycle.

On the other hand, if YES in step S132, that is, if P (PNC, Vc) is an invalid display pixel,
This pixel P (PNC, Vc) is a line image end pixel P
It is determined that the pixel is the pixel P (HcE '+ 1, Vc) next to E', and the process proceeds to step S136. This is because it is detected that the pixel P (PNC-1, Vc) to be determined one clock cycle ago is the line image end pixel PE ′, so that it is unnecessary to determine the pixels remaining on the current line. is there.

In step S136, the current horizontal line Vc
Is set as the coordinates of the line image end pixel PE 'of the pixel detected one clock cycle ago. In other words, the line image end horizontal coordinate HcE ′ is added to the value of the clock counter PNC one clock cycle earlier, ie, PNC.
-1 is set, and the routine proceeds to the next step S138.

On the other hand, if YES in step S126, that is, if it is determined that there is no line image start pixel PS 'in the current horizontal line Vc, it is detected in step S128 at initialization or in the previous clock cycle. The process directly proceeds to step S138 without updating the horizontal coordinate value HcS ′ of the line image start pixel PS ′.

If YES in step S134, that is, if it is determined that there is no line image end pixel PE 'in the current line, step S138 terminates the line image detected at initialization or in the previous clock cycle. The process directly proceeds to step S138 without updating the horizontal coordinate value HcE 'of the pixel PE'.

In step S138, as described above, based on the line image start pixel PS 'and line image end pixel PE' obtained for the current horizontal line Vc through one of steps S126, S134, and S136. The coordinate values of the image left end pixel PS and the image right end pixel PE stored in the register are updated as follows.

First, the updating of the left pixel PS of the image will be described. If the horizontal coordinate value HcS ′ of the newly detected line image start pixel PS ′ is smaller than the horizontal coordinate value HcS of the image left end pixel PS stored in the register, the horizontal coordinate value of the current line image start pixel PS ′ is set. The coordinate value HcS ′ is stored in the register as the horizontal coordinate value HcS of the image left end pixel PS. That is, among the effective display pixels on each horizontal line of the screen image FI, the horizontal coordinate of the pixel having the earlier raster scan order is set as the image left end coordinate HcS at that time.

Next, updating of the right edge pixel PE of the image will be described. If the horizontal coordinate value HcE 'of the newly detected line image end pixel PE' is larger than the horizontal coordinate value HcE of the image left end pixel PS stored in the register, the horizontal coordinate value of the current line image end pixel PE ' HcE ′ is stored in the register as the horizontal coordinate value HcE of the pixel PE at the right end of the image. That is, the horizontal coordinate of a pixel having a lower raster scan order than the effective display pixel on each horizontal line of the screen image FI is set as the image left end coordinate HcE at that time.

In this manner, the value obtained in units of one line is
Line image start pixel PS 'and line image end pixel P
The horizontal coordinate value of E 'is compared with the horizontal coordinate values of the left-end pixel PS and the right-end pixel PE stored in the register and updated accordingly, so that the first horizontal line V1 to the current horizontal line Vc are updated. , The horizontal coordinate HcS of the pixel PS located at the left end in the entire screen image FI including
After obtaining the horizontal coordinate HcE of the pixel PE located at the rightmost end, the process proceeds to the next step S140.

In step S140, it is determined whether the vertical position parameter Vc is equal to the number V of pixels in the vertical direction. The horizontal line Vc to be determined is the final horizontal line V of the screen image FI.
Is not reached, it is determined to be N0 and the process proceeds to step S142.

In step S142, the vertical position parameter Vc is incremented by one, and a pixel on the next horizontal line is set as a determination target. Then, the process returns to the next step S122.

On the other hand, if YES in step S140, that is, all horizontal lines in the screen image FI are to be determined, and in step S138, the image left end pixel PS and the image right end pixel PE
After updating the coordinate values, the process proceeds to step S144.

In step S144, step S138
Is subtracted from the image right end horizontal coordinate value HcE detected for the entire screen image FI, and 1 is added, thereby obtaining the number of pixels NHP in the horizontal image display section HP.
Ask for. Then, the process proceeds to the next step S146. still,
The calculation of the horizontal image display section pixel number NHP in this step can be expressed by the following equation.

[0071]

## EQU1 ## NHP = HcE-HcS + 1

In step S146, an image information signal Si is generated by the image start / end coordinate detection circuit 3, and the image information signal Si is generated based on the information detected in steps S138 and S144. Further, the image information signal Si is output to the display control circuit 4. In this way,
NP Detection Routine Processing (Step S12)
After completing (0), the process proceeds to step S170 shown in FIG.

In step S170, the display adjustment circuit 4
Determines whether the number of pixels NHP in the horizontal image display section read from the image information signal Si matches the preset number of pixels NPP in the effective display section. It is to be noted that the set effective pixel number NPP is preferably equal to the horizontal pixel number H of the analog image signal Sia as described above, but other appropriate predetermined values may be used.

When the horizontal image display section pixel number NHP is equal to the set effective display pixel number NPP, the clock Sc does not need to be adjusted because the clock number of the clock Sc matches the input analog image signal Sia. Therefore, the process ends.

On the other hand, when the horizontal image display section pixel number NHP is not equal to the set pixel number NPP, step S170
Is determined as NO, and the process proceeds to the next step S172.

In step S 172, the display control circuit 4 updates the current clock number data Scd with the number of clocks obtained by correcting the error between the set effective display pixel number NPP and the horizontal image display section pixel number NHP. After this updated clock number data Scd is output to the clock generation circuit 2, the process proceeds to step S174. The updating of the clock number data Scd in this step can be expressed by the following equation.

[0077]

## EQU2 ## Scd = Scd + NPP-NHP

In step S174, the clock generation circuit 2 generates a new clock Sc based on the clock number data Scd input from the display control circuit 4, and
/ D converter 1. Then, the next step S17
Proceed to 6.

In step S176, the A / D converter 1 sets the analog image signal S based on the clock Sc.
ia, a digital image signal Sid is generated, and based on the digital image signal Sid, the image start / end coordinate detection circuit 3, display control circuit 4, and clock generation circuit 2 perform steps S120, S170, S172, S174,
And the processing of S176 are repeated, and when the set number of effective pixels NPP matches the number of detected effective pixels NP in step S170, the clock number data Scd generation routine of step # 100 is terminated, and the process proceeds to the next step # 200. This makes it possible to automatically calculate and adjust the clock number data (clock frequency).

The detection of the image start coordinates and the image end coordinates of the image start / end coordinate detection circuit 3 is performed by detecting the coordinates of the line image start pixel PS 'and the line image end pixel PE' for each horizontal line. It is stored and updated in the next horizontal line by comparing with the coordinate values of the previous line image start pixel PS ′ and the line image end pixel PE ′, thereby updating the image left end pixel of the entire screen image FI. Although the coordinate detection of the PS and the right end pixel PE of the image has been realized, it can be realized by the following method. The coordinate register and the minimum value comparison circuit of the image left end pixel PS and the coordinate register and the maximum value comparison circuit of the image right end pixel PE are connected to a counter PNC that counts with the clock Sc using the horizontal synchronization signal Hsync as a trigger. Then, when the video signal Sia exists, the minimum value comparison circuit and the maximum value comparison circuit are operated, and the minimum value is detected by the image left end coordinate register and the maximum value is detected by the image right end coordinate register.

The set number of effective pixels NPP in the horizontal effective display section HEDP is a counter that counts the horizontal synchronizing signals in the two vertical synchronizing signals (detects the total number of horizontal lines for one screen) and this value. Can be realized by setting a comparison circuit that compares the value with a preset value. The number of pixels on the screen is generally determined for each output mode of each video adapter such as VGA, SVGA, XGA, etc.
In the case of H640 × V480 dots, in the case of SVGA H
800 x V600 dots, H1, 024 x for XGA
V is the number of pixels of 768 dots. On the other hand, the total number of horizontal synchronizing signals is related to the number of vertical pixels, and the total number of horizontal synchronizing signals is detected. The output mode of each video adapter is determined. For the sake of simplicity, the output mode of each video adapter will be simply referred to as VGA mode, SVGA mode, and XGA mode.
Each video adapter name is referred to as an output mode as it is.

Here, N1 is 600 or 6
A value obtained by adding the number of lines in a blanking section having no video signal of several lines to 00 is given to 768 or 768 in N2.
And a value obtained by adding a blanking section of several lines to the above. If the total number of horizontal synchronization signals is N1 or less, it is determined that the mode is the VGA mode, if N1 to N2, the mode is the SVGA mode, if it is more than N2, the mode is the XGA mode. To 800, and the number of effective detection pixels N in XGA mode
P is set to 1,024. This function is provided in the image start / end coordinate detection circuit 3 and output to the display control circuit 4. Alternatively, a part requiring high-speed processing such as a counter function and a comparison function for detecting the total number of horizontal synchronization signals Hsync is provided in the image start / end coordinate detection circuit 3, and the display control circuit 4 outputs the output video adapter. It can also be realized by identifying the mode and setting the set number of effective pixels NPP.

Next, the phase adjustment routine of step # 200 shown in FIG. 2 will be described below with reference to FIGS. First, the concept of the phase adjustment in the present invention will be described with reference to FIG. 5, and then the specific operation will be described with reference to FIG.

FIG. 5 shows the analog image signal Sia and the clocks CLK1, CLK2 and CLK3. In the present invention, the adjustment of the phase, that is, the generation of the phase data Sp
Attention is paid to the first video signal of the horizontal display, that is, the horizontal coordinate HcS of the image left end pixel PS, and the digital image signal Sid at this time is used.

That is, in the case of the clock CLK1, the twentieth clock pulse Ph20 corresponds to the analog image signal Si
This indicates that the start end Se of a has been detected, and the value of the line image start horizontal coordinate HcS ′ at this time is 20. From this state, the phase is changed by shifting clock CLK1 rightward. A case where the phase of the clock CLK1 is shifted to the right by 360 degrees is shown as a clock CLK2. In the clock CLK2, the 19th clock pulse Ph19 indicates that the start end Se of the analog image signal Sia has been detected, and the value of the image start horizontal coordinate at this time is 19. The start end Se of the analog image signal Sia is the clock pulse Ph2
A clock adjusted so as to be located at the transition of the clock pulse Ph19 from 0 is shown as a clock CLK3. That is, the phase of the clock CLK3 is shifted by 180 degrees from the phases of the clocks CLK1 and CLK2, respectively, and has exactly the middle phase between the clocks CLK1 and CLK2.

That is, in the present invention, two clocks CLK1 and CLK2 are generated by shifting the phase of the clock Sc, and the analog image signal Sia corresponding to each of them is generated.
Is detected as phase data, and this 2
The phase is adjusted by generating a clock CLK3 having an intermediate point of the phase data of the point as the optimum phase data.

Referring to a flowchart shown in FIG. 8, a specific operation of step # 200 shown in FIG. 2 will be described.
Prior to this phase adjustment routine, step # 100
Needless to say, the clock Sc has already been correctly adjusted in accordance with the analog image signal Sia to be input in the clock adjustment step. As the analog image signal Sia, a signal having an image at the left end of the screen is input. That is, the analog image signal Sia corresponds to the pixel Pa shown in FIG.
Or, it has Pc.

In step S402, the display control circuit 4 outputs the phase data Spv indicating the shortest delay time as the initial value of the phase data Sp to the delay circuit 5, and then proceeds to the next step S404.

In step S404, the display control circuit 4 further reads the image left end horizontal coordinate HcS from the image start / end coordinate detection circuit 3, and then proceeds to the next step S406. The reading of the horizontal coordinate HcS at the left end of the image is performed by the same method as that used in the detection routine of the horizontal image display section HP described in detail with reference to FIG.

In step S406, the display control circuit 4 increments the phase data Sp in the direction of increasing the delay time based on the horizontal coordinate HcS of the left end of the image read in step S404, and outputs the clock CLK1. Then, the process proceeds to the next step S408.

In step S408, the left horizontal coordinate HcS 'of the image is newly read, and the next step S410 is executed.
Proceed to.

In step S410, if the currently read image left end horizontal coordinate HcS 'is equal to the previously read image left end horizontal coordinate HcS, YES is determined, and the flow advances to step S412.

In step S412, the clock CLK1
Is further incremented, and the process proceeds to the next step S414.

In step S414, the updated Sp is output to the delay circuit 5, and CLK2 is generated.
Return to 408.

On the other hand, if NO in step S410, that is, if the current image left end horizontal coordinate HcS 'is different from the previous image left end horizontal coordinate HcS, the flow advances to step S416.

In step S 416, it is determined whether or not it is the first change point. In the case of YES, the process proceeds to step S418.

In step S418, after the phase data Sp is stored in the variable P1, the process proceeds to step S412. Then, the aforementioned steps S412, S414, S408,
And the process of searching for a change point in S410 is repeated.

On the other hand, when NO is determined in the step S416, that is, YES is determined twice in the step S410,
The clock CLK corresponding to the second detected change point
After storing the phase data Sp based on 2 in the variable P2, the process proceeds to the next step S420.

In step S420, the variables P1 and P
After generating the average value of 2 as the adjusted phase data Sp, the process proceeds to the next step S424.

At step S424, the phase data Sp generated at step S420 is output to the delay circuit 5, and
After generating K3, the process ends. In this way, by calculating and adjusting the phase data Sp that determines the timing for performing the A / D conversion on the analog image signal Sia, it is possible to eliminate the fluctuation of the display image.

In the above description, the left end image is used. However, the same adjustment can be made by inputting the right end image and using the data of the image end coordinates. In this case, the image end coordinates from the image start / end coordinate detection circuit 3 are used.

Next, the details of the display position adjustment routine in step # 300 shown in FIG. 2 will be described with reference to the flowchart shown in FIG. At the start of this routine, in the preceding steps # 100 and # 200,
Needless to say, the clock Sc and the phase data Sp have been correctly adjusted according to the input analog image signal Sia. Also, the analog image signal Sia to be input
Represents an image at the left end and the upper end, that is, the pixel P shown in FIG.
This is a signal having an image corresponding to a. Further, the image start / end detection circuit 3 further has a vertical image start detection function in addition to the functions described in the clock adjustment and the phase adjustment. Since the function of detecting the start of the image in the vertical direction is mainly constituted by software, it is not particularly shown as means such as a circuit. Further, the image start position in the vertical direction is nothing less than obtaining the vertical coordinates of the upper end of the screen image FI, that is, the image upper-end vertical coordinates VcS. In order to detect the image top vertical coordinate VcS, the image start / end coordinate detection circuit 3 counts the horizontal synchronization signal Hsync using the vertical synchronization signal Vsync as a trigger, and calculates the vertical coordinate value VcS.
c, and the vertical coordinate value Vc at which the analog image signal Sia first appears is the image top vertical coordinate VcS. The processing content of each step is as follows.

In step S302, the display control circuit 4 reads out the image left end horizontal coordinate HcS and the image upper end vertical coordinate VcS from the image start / end coordinate detection circuit 3, and then proceeds to the next step S304.

In step S304, the following processing is executed based on these image left horizontal coordinate HcS and image upper vertical coordinate VcS to generate display device control data Sdc. The horizontal coordinate HcS at the left end of the image is set as the horizontal display start coordinate HsS. The image left end coordinate HcE is calculated by adding the horizontal image display section pixel number NHP representing the number of pixels in the horizontal effective display section HEDP to the image left end horizontal coordinate HcS. The image top vertical coordinate VcS is set to the vertical display start coordinate V
Set as sS. Further, the vertical effective display section VED
P is added to the vertical image display section pixel number NVP representing the number of pixels in P and the image top vertical coordinate VcS to obtain the image bottom vertical coordinate V
Calculate cE. In addition, the vertical image display section pixel number NVP
Can be basically obtained by the same method as the horizontal image display section pixel number NHP, and a detailed description of the method will be omitted. After performing the above processing, the process advances to the next step S306.

In step S306, the display device control data Sdc including the image left end coordinate HcE and the image lower end vertical coordinate VcE generated in step S304 is output to the image display unit driving circuit 10, and the process ends.

In the above example, the image left end coordinate HcE and the image lower end vertical coordinate VcE are respectively set to the image left end horizontal coordinate HcE.
It is calculated from cS and the horizontal effective display section HEDP, and the image top vertical coordinate VcS and the vertical effective display section VEDP. However, an analog image signal Sia having valid image pixels Pa and Pd is input to the upper left corner and lower right corner of the screen image FI, and the image left end coordinate HcE and the image lower end vertical coordinate VcE data are input from the image start / end detection circuit 3. It is also possible to detect and generate display coordinate control data Sdc. In this case, the image start / end detection circuit 3 further has a function of detecting the image end position in the vertical direction.
To detect the image end position in the vertical direction, the vertical synchronization signal Vsync is used as a trigger, the horizontal synchronization signal Hsync is counted, and the vertical coordinate value Vc is calculated.
By sequentially storing the vertical coordinate value Vc when ia appears in a register, the value of this register becomes the image bottom vertical coordinate VcE. The image start / end detection circuit 3 detects an image left end horizontal coordinate HcS and an image upper end vertical coordinate VcS, and an image left end coordinate HcE and an image lower end vertical coordinate VcE.
Then, the display control circuit 4 generates display device control data Sdc based on these values, and outputs the data to the image display unit driving circuit 10. As shown in FIG. 4, the input analog image signal Sia may be a signal having effective display pixels Pb and Pc at the upper right corner and the lower left corner of the screen image FI, respectively.

According to the present invention, a special screen is usually unnecessary for correctly generating display coordinate control data for adjusting the display position of an image. For example, Windows
An input image having wallpaper as a whole on a ws (registered trademark of Microsoft Corporation) screen may be used.

Alternatively, the number of horizontal image display section pixels NHP and the number of vertical image display section pixels NVP can be detected by the following means. It is composed of a counter that counts the horizontal synchronization signal Hsync (detects the total number of horizontal lines for one screen) described in the calculation of the clock number data, and a comparison circuit that compares this value with a preset value. , Each display mode is identified, and the number of pixels in the horizontal effective display section HEDP and the vertical effective display section VEDP is set. In the case of the VGA mode, the number of pixels in the horizontal effective period is 640 and the number of pixels in the vertical effective period is 480. In the case of the SVGA mode, the number of pixels in the horizontal effective period is 800 and the number of pixels in the vertical effective period is 600.
In the case of the XGA mode, the number of pixels in the horizontal effective period is set to 10
24, the number of pixels in the vertical effective period is set to 768. In this case, the required image screen may have a length having only the effective display pixel Pa at the upper left corner shown in FIG. Then, the display control data Sdc can be calculated by detecting only the horizontal coordinate HcS at the left end of the image and the vertical coordinate VcS at the upper end of the image, and adding the number of pixels in the horizontal and vertical effective periods in each mode.

Although the description has been given of a monochrome image, only a portion different from a monochrome image in a color image will be described below. The A / D converter 1 has R
(Red), G (Green), and B (Blue) are respectively prepared for a total of three. The logical sum of the outputs of these three A / D conversion circuits is obtained, and this output is connected to the image start / end detection circuit 3 as a digital image signal Sid. Other circuits may be configured as described above, and it is not necessary to separately prepare means other than the A / D converter 1 for each color signal.

With this configuration, the optimum clock number data, phase data, and display position data according to the input video signal can be automatically obtained without preparing preset data corresponding to the analog image input signal from the personal computer in advance. Can be set. It also eliminates the need for data adjustment by the user.

[0111]

As is apparent from the above description, according to the present invention, the start and end coordinates of an image of a digitized video signal are detected, and the actual video signal input by using those data is detected. , The clock number data, the phase data, and the display position data can be set. Therefore, there is no need to prepare preset data in accordance with the video signal to be input. As a result, the input video signal and the preset data PI
There is no need for the user to adjust the gap between the two.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the structure of a digital image display device incorporating an input video adapter according to an embodiment of the present invention.

FIG. 2 is a flowchart showing main operations of the input video adapter according to the present invention shown in FIG. 1;

FIG. 3 is a conceptual diagram illustrating clock adjustment based on the present invention.

FIG. 4 is a conceptual diagram illustrating image information of an image signal according to the present invention.

FIG. 5 is a conceptual diagram illustrating phase adjustment based on the present invention.

FIG. 6 is a flowchart illustrating a detailed operation of a clock adjustment routine shown in FIG. 2;

FIG. 7 is a flowchart showing details of a horizontal image display section pixel number detection routine shown in FIG. 6;

8 is a flowchart showing a detailed operation of a phase adjustment routine shown in FIG.

FIG. 9 is a flowchart showing a detailed operation of a display position adjustment routine shown in FIG. 2;

FIG. 10 is a block diagram showing the structure of a conventional input video adapter.

FIG. 11 is a conceptual diagram illustrating a problem of clock adjustment unique to a conventional input adapter.

FIG. 12 is a conceptual diagram illustrating a problem of phase adjustment unique to a conventional input adapter.

FIG. 13 is a conceptual diagram illustrating a problem of display position adjustment unique to a conventional input adapter.

[Explanation of symbols]

 Reference Signs List 1 A / D conversion circuit 2 Clock generation circuit 3 Image start / end coordinate detection circuit 4 Display control circuit 5 Delay circuit 7 Preset data memory 10 Image display drive circuit 11 Image display 14 Display control circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H04N 5/66

Claims (6)

(57) [Claims] 1. A digital image display device for converting an analog image input signal into a digital signal and displaying the digital image signal, wherein the analog image input signal and a clock for converting from analog to digital at a constant period are input to the analog image display device. An A / D conversion circuit for converting an image input signal into a digital signal; a digital video signal output from the A / D conversion circuit; a horizontal synchronization signal and a vertical synchronization signal synchronized with the analog image input signal; Detected for each horizontal line of the digital video signal using the clock of the D conversion circuit as input
An image start / end coordinate detection circuit for detecting a horizontal image start coordinate which is the horizontal coordinate of the leftmost display pixel and a horizontal image end coordinate which is the horizontal coordinate of the rightmost display pixel in a plurality of horizontal sections; From the horizontal image start coordinates and the horizontal image end coordinates, the A / A
A display control circuit for calculating clock number data associated with a clock frequency of the D conversion circuit, and a clock generation circuit for generating a clock for the A / D conversion circuit based on the clock number data from the display control circuit A value obtained by subtracting the horizontal image start coordinate from the horizontal image end coordinate by the display control circuit matches the number of pixels in a horizontal effective display section when the analog image input signal is digitally generated. As described above, a digital image display apparatus characterized in that the clock corresponding to the number of clocks of the A / D conversion circuit is calculated to automatically adjust the frequency of the clock to be A / D converted. 2. A digital image display device for converting an analog image input signal into a digital signal and displaying the digital image signal, wherein the analog image input signal and a clock for converting from analog to digital at a constant cycle are input. An A / D conversion circuit for converting an image input signal into a digital signal; a digital video signal output from the A / D conversion circuit; a horizontal synchronization signal and a vertical synchronization signal synchronized with the analog image input signal; Detected for each horizontal line of the digital video signal using the clock of the D conversion circuit as input
An image start coordinate detection circuit that detects a horizontal image start coordinate that is a horizontal coordinate of a leftmost display pixel in a plurality of horizontal sections; a delay circuit that delays a horizontal synchronization signal synchronized with the analog image input signal; A clock generation circuit for generating a clock for the A / D conversion circuit in synchronization with an output of the delay circuit; and inputting the horizontal image start coordinates and outputting phase data for determining a delay time of the horizontal synchronization signal to the delay circuit. The display control circuit changes the phase data, and the image start coordinate value from the image start coordinate detection circuit changes by one coordinate to check out the phase data. A digital image display device wherein a phase of a clock of the A / D conversion circuit is automatically adjusted using the obtained phase data. 3. A digital image display (VA) for converting an analog image input signal (Sia) into a digital signal and displaying the digital image signal, wherein the analog image input signal (Sia) and a clock (Sc) for converting from analog to digital. ) As input, an A / D conversion circuit (1) for converting the analog (Sia) into a digital signal, a digital video signal (Sia) output from the A / D conversion circuit (1), and the analog image (Sia) and a vertical synchronizing signal (Vsync) synchronized with the horizontal synchronizing signal (Hsync).
nc), an image start coordinate detection circuit (3) for detecting a horizontal image start coordinate (HcS) and a vertical image start coordinate (VcS) using a clock of the A / D conversion circuit (1) as an input, A display coordinate control circuit (4) for controlling display coordinates (Sdc) for displaying the converted video signal (Sid) is provided. The display coordinate control circuit (4) includes a horizontal display start coordinate (Hs).
S) is the horizontal image start coordinate (HcS), the horizontal display end coordinate (HsE) is the horizontal image start coordinate (HcS), and the horizontal effective display section when the analog image input signal (Sia) is digitally generated. (HEDP)
P), the vertical display start coordinate (VsS) is converted from the vertical image start coordinate (VcS) to the vertical display end coordinate (VsE).
Is calculated from the vertical image start coordinates (VcE) and the number of lines (V) of the vertical effective display section (VEDP) when the analog image input signal (Sia) is digitally generated, thereby displaying the display coordinates (Sdc). Digital image display device characterized by automatic adjustment. 4. A screen for displaying an image at the upper end at the right end and at the lower end at the left end, or at the upper end at the left end and at the lower end at the right end, and inputs the horizontal image end coordinate (HcE) to the image start coordinate detection circuit (3). The number of pixels in a horizontal effective display section when the analog image input signal (Sia) in the display coordinate control circuit (4) is digitally generated by adding a function of detecting a vertical image end coordinate (VcE) (NHP) is the horizontal image end coordinate (HcE)
Is subtracted from the horizontal image start coordinate (HcS), and the number of lines in the vertical effective display section (VEDP) when the analog image input signal is digitally generated is calculated from the vertical image end coordinate (VcE) to the vertical image start coordinate. The display coordinates are automatically adjusted by using a value obtained by subtracting (VcS).
2. The digital image display device according to 1. 5. A function for counting the total number of horizontal synchronization signals between vertical synchronization signals synchronized with the analog image input signal is added to the image start / end detection circuit (3), and the analog image input signal is digitally converted. 2. The frequency of a clock for A / D conversion is automatically adjusted by having a function used to identify the number of pixels (NHP) in a horizontal effective display section (HEDP) when the clock is generated. Digital image display device. 6. A horizontal effective display section (HED) when an analog image input signal identified from the total number of horizontal synchronization signals between the vertical synchronization signals according to claim 5 is digitally generated.
The number of pixels (NHP) of P) is set to the number of pixels in the horizontal effective display section when the analog image input signal according to claim 3 is digitally generated, and the number of pixels of the vertical synchronization signal according to claim 5 is set. The total number of horizontal synchronizing signals between them is also used to identify the number of lines in a vertical effective display section when an analog image input signal is digitally generated. A digital image display device wherein display coordinates are automatically adjusted by setting the number of lines in a vertical effective display section when digitally generated.