KR100247111B1 - Motion detecting device - Google Patents

Abstract

Motion detection with half pixel precision is performed easily.

In the i cycle, data of Ai and ai are input to the input terminals 1 and 5, and a value of 1/2 of Ai data is supplied to the serially connected registers 3a to 3n, and 1 / The value of 2 and the outputs of the registers 3a, 3b, 3f, 3h, 3l, 3m, and 3n are supplied to the adders 4a to 4h, respectively, and the data of ai and the output of the register 3g are subtracted (6). ), And the subtracted output from the subtractor 6 is supplied to the adders 4a to 4h. The outputs of these adders 4a to 4h are supplied to the accumulation circuits 8a to 8h through the absolute value circuits 7a to 7h, respectively, and are supplied to the accumulator circuits 8a to 8h at the terminals 9. Supply the enable control signal.

Description

Motion detection device

1 is a configuration diagram of an example of a motion detection apparatus according to the present invention.

2 is a diagram for illustration thereof.

3 is a diagram for that explanation.

4 is a flowchart of an example of a motion detection apparatus.

5 is a configuration diagram of an essential part of a motion detection device.

6A and 6B are diagrams for explaining motion detection with one pixel precision.

7 is a diagram for explaining motion detection with half pixel precision.

* Explanation of symbols for main parts of the drawings

1: Input terminal to which data of A is supplied

2: means for shifting the data one bit to half the value

3a to 3n: registers 4a to 4h: adder

5: Input terminal to which data of a is supplied 6: Subtractor

7a to 7h: absolute value circuit 8a to 8h: accumulation circuit

9: Terminal to which enable control signal is supplied

10: Input terminal supplied with residual difference S of 1 pixel precision

11: comparison circuit

12: output terminal of motion vector with half pixel precision

The present invention relates to a motion detection device used for, for example, the detection of motion vectors in high efficiency encoding of moving picture data.

For example, when a motion vector is detected by high efficiency encoding of moving image data, for example, when detection is performed by full search block matching, a pixel within a search range composed of a predetermined number of pixels, and the like. A motion detection apparatus for comparing pixels in a reference data block composed of a small number of pixels by their arrangement is used. In such a motion detection apparatus, after detecting a motion of a normal one-pixel precision, the predicted images shifted by 0.5 pixels are obtained by interpolating (an average value of two points) in the eight directions around the obtained vector, and these predictive images are obtained. A vector is obtained in which the residual difference with the original image (reference data block) is minimized (motion detection with half pel precision) is performed.

That is, for example, in the case where the reference data block is 4 × 4, motion detection with one pixel precision is performed, and motion vectors as shown in Figs. 6A and 6B are obtained first. If the residual difference at this time is S

Becomes Where a _i is 16 pixels of the reference data block as shown in FIG. 6B, and A _i is 16 pixels corresponding to the reference data block which has detected motion with one pixel precision of the search range as shown in FIG. 6A. Pixel.

On the other hand, to detect the motion with the accuracy of half pixel (0.5 pixel), as shown in FIG. 7, the following equation 1 is used by using the pixel (6 x 6 data) of the search range larger than the above 16 A _i. We can calculate the minimum sum (·, ·) by calculating.

[Equation 1]

However, in the case of performing motion detection with half-pixel accuracy in the related art, if Equation 1 is executed as it is, A _I + A _J shown in the equation must be calculated, and the correspondence between "(A _I + A _J ) / 2" and "a _k " It was complicated and could not be easily calculated.

The problem to be solved by the present invention is that when the motion detection with the conventional half pixel precision is performed, the calculation is complicated and could not be easily performed.

According to the present invention, when a pixel in a search range configured as a predetermined number of pixels and a pixel in a reference data block configured as a number of pixels smaller than the predetermined number of pixels are compared based on the arrangement state, the block can be taken within the search range. Calculation means for calculating a sum of difference absolute values between respective pixels in the block and corresponding pixels in the search range for each corresponding state of the pixels, wherein a cycle inputted to the calculation means is set in advance for each pixel in the search range. A motion detection device configured to input a pixel within the search range to the calculation means based on the cycle to perform the calculation with the pixels in the corresponding reference data block sequentially;

When detecting a motion state of one pixel or less within the search range, the average value between adjacent pixels (input terminal 1) is compared with the pixels in the block (input terminal 5), and the pixels in the block The difference absolute value is obtained for each corresponding state (adders 4a to 4h, subtractor 6, absolute value circuits 7a to 7h, accumulator circuits 8a to 8h), and the operation (subtracter 6) common between the corresponding states is performed. A motion detection device characterized by performing in advance.

According to this, the calculation is simplified by performing the common operation among the corresponding states in advance, so that the motion detection with half pixel precision can be performed with a simple device configuration.

However, the number of additions can be reduced by grouping the common term among the eight expressions except Sum (0,0) in the above formula (1). By appropriately operating the input term, the correspondence between "(A _I + A _J ) / 2" and "a _k " is also simplified, and the circuit scale of the apparatus can be reduced. That is, in the present application, the above formula 1 is modified as follows.

[Formula 2]

In the formula _{2 [(A 7/2)} -a 14], [(A 8/2) -a 15], ..., [(A 28/2) -a 35] is common to 8 wherein Once these subtractions are calculated, the values can be used in eight equations, thereby reducing the number of additions and subtractions.

1 shows the configuration of the apparatus. In this figure, the above-mentioned A data is supplied to the input terminal 1. This data is shifted by one bit (2) so that the value is 1/2. A value of 1/2 is supplied to the registers 3a to 3n connected in series. The half value and the outputs of the registers 3a, 3b, 3f, 3h, 3l, 3m, and 3n are supplied to the adders 4a to 4h, respectively.

On the other hand, the above-mentioned a data is supplied to the input terminal 5. The data of this input terminal 5 is supplied to the subtractor 6, the output of the register 3g is supplied to the subtractor 6, and the data of a supplied to the input terminal 5 is subtracted from this value. The subtraction output in this subtractor 6 is supplied to the adders 4a to 4h. The addition outputs from the adders 4a to 4h are supplied to the accumulation circuits 8a to 8h via the absolute value circuits 7a to 7h, respectively. The enable control signal at the terminal 9 is supplied to the accumulation circuits 8a to 8h. The input terminal 10 is supplied with the residual difference S of the motion vector found as the above-described motion detection with one pixel precision. Then, the residual difference at this input terminal 10 is supplied with the S value, and the addition output at the accumulation circuits 8a to 8h is supplied to the comparison circuit 11, and the minimum value is detected to move the half pixel precision. The vector is output at the output terminal 12.

In this apparatus, data of A _i is input to the input terminal 1 every i cycle, and data of ai is input to the input terminal 5 every i cycle. Where Ai is a pixel in the search range (6 x 6) of FIG. 7 described above, ai is 16 pixels of the reference data block shown in FIG. 6B, and i = 0, 1, 2, ..., 35 . In addition, a ₀ to a ₁₃ , a ₁₈ , a ₁₉ , a ₂₄ , a ₂₅ , a ₃₀ , a ₃₁ are not shown in FIG. 6B, but corresponding to 0 to 13, 18, 19, 24, 25, In the 30th and 31st cycles, dummy data is input to the input terminal 5.

Thus, in this device, the output of the input of data is disclosed for each cycle register 14 (3g) ", the value input to the input terminal (1) is one-half times the seventh cycle delayed value", or "A _7/2 "Is output and the data of" a ₁₄ "is input to the input terminal 5 simultaneously. In this way the subtractor _{(6) [(A 7/} 2) -a 14] is calculated. At this time also, the output of the register (3n) has been "the value entered in the input terminal 1 is 1/2 times 14 cycles delayed value", or "A _0/2" output. In this way the adder _{(4h) [(A 0/} 2) + {(A 7/2) -a 14}] is calculated, an absolute value generating circuit (7h) in the _{[| (A 0/2)} + {(A _7/2) -a _14} | is the absolute value as shown in screen] is input to the accumulation circuit (8h).

Similarly, the _{[(A 7/2) -a} 14] value, the adder 4a to, it is also input to (4g), respectively _{[(A 14/2) +} {(A 7/2) calculated by the subtractor (6) _{-a 14}], [(A} 13/2) + {(A 7/2) -a 14}], [(A 12/2) + {(A 7/2) -a 14}], [( _{A 8/2) + {(} A 7/2) -a 14}], [(A 6/2) + {(A 7/2) -a 14}], [(A 2/2) + {( _{a 7/2) -a 14}} ], [(a 1/2) + {(a 7/2) -a 14}] is calculated. These values are absolute values in the absolute value circuits 7a to 7g and input to the accumulation circuits 8a to 8g. If that is In summary, the right side of claim 1, wherein the value of the formula 2 in the 14 th cycle _{[(A * / 2) +} {(A 7/2) -a 14}] ( short * = 0, 1, 2, 6 , 8, 12, 13, 14 are input to the accumulation circuits 8a to 8h, respectively.

Also in the 15th to 17th cycle, for example, the accumulation circuit (8h) is _{[(A 1/2) +} {(A 8/2) -a 15} = "Formula 2 Sum (-0.5, -0.5)." right side second term _{"] [(a 2/2)} + {(a 9/2) -a 16} = the" the right side of the equation 2 Sum (-0.5, -0.5). "8 (formula 2 below. are omitted as ...) _{"], [a 3/2)} + (a 10/2) -a 17} = right side of claim 4, wherein the" in formula 2 Sum (-0.5, -0.5) (in the formula 2. Are omitted.]] Are input and are accumulated.

On the other hand, in at 18, 19 cycles, the accumulation circuit _{(8h) [{(A 4} /2) + {(A 11/2) -a 18}], [(A 5/2) + {(A _12/2) -a _19}] is, the input, which is a value that is not shown in the right side of the equation 2 Sum (-0.5, -0.5). Therefore, in these cycles, the enable control signal from the terminal 9 is set low (off) so that these unnecessary data are not accumulated. A ₁₈ and a ₁₉ are dummy data.

Hereinafter, in the 20th to 23rd cycles, the values of "the fifth to eighth terms on the right side of Sum (-0.5, -0.5) of Equation 2" are inputted, and these values are accumulated in the accumulated result until then. In the 24th and 25th cycles, since unnecessary data is input, the enable control signal from the terminal 9 is set low (off) so that these unnecessary data are not accumulated. In the 26th to 29th cycles, the values of the "ninth to twelfth term on the right side of Sum (-0.5, -0.5) of equation (2)" are input and these values are accumulated in the accumulated result until then. In the 30th and 31st cycles, since unnecessary data is input, the enable control signal from the terminal 9 is set low (off) so that these unnecessary data are not accumulated. And in the 32nd-35th cycle, the value of "13th intrinsic 16 (final) term of the right side of Sum (-0.5, -0.5) of Formula 2" is input, and these values are accumulate | accumulated to the accumulation result up to that time. As a result, the summation circuit 8h forms a value of Sum (-0.5, -0.5) at the end of the 35th cycle.

That is, in the above-described apparatus, in the register 3n between 14 and 35 cycles, the values A ₀ to A ₂₁ indicated by arrows in the second figure of the data input to the input terminal 1 are halved. Outputted, and in the accumulation circuit 8h, by the value of the oblique portion therein,

Sum (-0.5, -0.5) = Σ | (A _I / 2) + {(A _J / 2) -a _K } |

(Where I, J and K are the values of 16 terms indicated in the formula)

Is accumulated. Also, the values of A ₄ , A ₅ , A ₁₀ , A ₁₁ , A ₁₆ , A ₁₇ , (cycles 18, 19, 24, 25, 30, 31) are not added because the enable control signal goes low (off). Do not.

In addition, between 14 and 35 cycles, from the register 3m, the values A ₁ to A ₂₂ indicated by arrows in FIG. 3 of the data input to the input terminal 1 are doubled and outputted. 8g), Sum (-0.5, 0) = Σ | (A _I / 2) + {(A _J / 2) -a _K } |

(However, I, J, and K are 16 values shown in the formula.)

Is accumulated. In addition, the values of A ₅ , A ₆ , A ₁₁ , A ₁₂ , A ₁₇ , A ₁₈ , (cycles 18, 19, 24, 25, 30, 31) are not added because the enable control signal goes low (off). Do not.

Similarly, calculations are made in other accumulation circuits 8a to 8f. The overall flow chart is also as shown in FIG. (1) is a value input to the input terminal (1), (2) to (10) is a register 3n. 3m, 3h, 3g, 3f, 3b, 3a and A are data whose values are 1/2, (11) is input to input terminal 5, (12) is input to input terminal 9 Able control signal. The Sum (0, 0) = S value is input from the input terminal 10 at the same time as the Sum (...,) calculation is completed in the eight accumulation circuits 8a to 8h, and these nine values are compared circuits. The comparison is made in (11), and the vector which is the minimum of these is detected.

In this way, according to the apparatus described above, the calculation is simplified by performing a common operation (subtracter 6) in each corresponding state in advance, so that motion detection with half pixel precision can be performed with a simple apparatus configuration.

In addition, in the above-described apparatus, parts of the adders 4a to 4h, the absolute value circuits 7a to 7h, and the accumulator circuits 8a to 8h can be realized as, for example, the fifth diagram. That is, addition of (A _I / 2) and {(A _J / 2) -a _K } is performed in the upper adder 4. If the carry-out (signal bit: Co) of the adder 4 is [0], this addition value is positive and is thus input to the lower adder 81 as it is. On the other hand, when the carryout Co of the adder 4 is [1], this addition value is negative. Thus, the value inverting this addition value as the inverter 71 is selected as the switch 72, and this value is supplied to the lower adder 81, and the value of [1] selected by the switch 73 is added to the adder 81. It is input to the lowest level (carrier: Ci) of. Thereby, the value in the adder 4 is made absolute and input into the adder 81. As shown in FIG.

The output of the adder 81 is input to itself via the unit delay element (register) 82. At the same time, the enable terminal EN is provided in this register 82, and the enable control signal at the terminal 9 is supplied to the enable terminal EN. Thereby, accumulation is performed so that the unnecessary value mentioned above may not be added.

In addition, this calculation circuit shows only one system, and when calculating 8 values as mentioned above, this calculation circuit is provided in 8 system parallels. Alternatively, when there is a margin in the calculation processing time, the calculation circuit can be realized by only one system by time division multiplexing in eight. In this case, the circuit scale becomes about 1/8. In the above description, the case where the reference data block is 4 x 4 has been described, but this can be generalized to any n x m.

According to the present invention, since the calculation is simplified by performing a common operation between the corresponding states in advance, it is possible to perform motion detection with half pixel precision with a simple device configuration.

Claims (1)

When a pixel in a search range composed of a predetermined number of pixels and a pixel in a reference data block composed of a number of pixels smaller than the predetermined number of pixels are compared based on the arrangement state, the block can be taken within the search range. Computing means for computing the sum of difference absolute values between the pixels in the block and the corresponding pixels in the search range for each corresponding state of the pixels, wherein each pixel in the search range has a cycle inputted to the computing means in advance. A motion detection device for inputting a pixel within the search range to the calculating means based on the cycle to sequentially perform the calculation with the pixels in the corresponding reference data block. When detecting a motion state of 1 pixel or less within the search range, the average value between adjacent pixels is compared with the pixels in the block, Obtain the absolute difference value for each corresponding state with the pixels in the block, And performing a common operation between the corresponding states in advance.