JP3038935B2 - Motion detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion detecting apparatus used for detecting a motion vector in, for example, high-efficiency coding of moving image data.

[0002]

2. Description of the Related Art For example, when a motion vector is detected by high-efficiency coding of moving image data, for example, a full search
When performing detection by block matching, pixels in a search range composed of a predetermined number of pixels are compared with pixels in a reference data block composed of a smaller number of pixels based on the arrangement state. A motion detection device is used. In such a motion detecting device, after detecting a motion of a normal one pixel (pel) accuracy, interpolation is performed (average value of two points) in eight directions around the obtained vector to obtain 0.5 Obtain a pel-shifted prediction image,
Original image (reference data block) among those predicted images
(A motion detection with half-pel accuracy) is performed.

That is, for example, when the reference data block is 4 ×
In the case of No. 4, it is assumed that motion detection with 1-pel accuracy is performed and a motion vector as shown in FIG. 6 is obtained first. If the residual at this time is S, then S = | A ₇ −a ₁₄ | + | A ₈ −a ₁₅ | +... + | A ₂₈ −a ₃₅ | Here, a _i is 16 pixels of the reference data block as shown in B of the figure, and A _i is 16 pixels corresponding to the reference data block of which motion is detected with one pel accuracy of the search range as shown in A of the figure. Pixels.

On the other hand, in order to detect a motion with half-pel (0.5 pel) accuracy, as shown in FIG.
6 A _i from slightly larger search area of the pixel (6 × 6
The following equation (1) may be calculated by using the number of pieces of data to find the minimum sum (.,.).

[0005]

(Equation 1)

However, when performing motion detection with conventional half-pel accuracy, if equation 1 is to be executed as it is,
Each A _I + A _J that appears in the equation must be calculated,
In addition, the correspondence between "(A _I + A _J ) / 2" and "a _K " was complicated and could not be easily calculated.

[0007]

The problem to be solved is that when performing motion detection with conventional half-pel accuracy, the calculation is complicated and cannot be easily performed.

[0008]

According to the present invention, a pixel within a search range composed of a predetermined number of pixels and a pixel in a reference data block composed of a number of pixels smaller than the predetermined number of pixels are combined. When comparing based on the arrangement state, the sum of the absolute difference between each pixel in the block and the corresponding pixel in the search range is calculated for each corresponding state of the pixels that the block can take in the search range. Having a calculating means, each pixel in the search range is set in advance at a time to be input to the calculating means, and based on the time , a pixel in the search range is input to the calculating means. A motion detecting device for performing the above calculation with pixels in the reference data block which correspond sequentially to each other, when detecting a motion state of one pixel or less in the search range, an adjacent pixel (input terminal 1)
The average value between the pixels and the pixels in the block (input terminal 5) are compared, and the sum of the absolute difference values is obtained for each corresponding state with the pixels in the block (adders 4a to 4a).
h, subtractor 6, absolute value conversion circuits 7a to 7h, accumulator circuit 8
a to 8h), wherein a common operation (subtractor 6) between the corresponding states is performed in advance.

[0009]

According to this, the calculation is simplified by performing the common operation between the corresponding states in advance, so that the motion detection with half-pel accuracy can be performed with a simple device configuration. .

[0010]

[Embodiment] In the above equation (1), sum (0,
The number of additions can be reduced by extracting the common term among the eight expressions except 0). By appropriately operating the input order, the correspondence between “(A _I + A _J ) / 2” and “a _K ” is also simplified, and the circuit scale of the device can be reduced. That is, in the present application, the above equation 1 is transformed into the following equation 2.

[0011]

(Equation 2)

[0012] In this equation (2), [(A _7/2) -
a _14], [(A _8/2) -a _15], ..., [(A ₂₈ /
2) -a ₃₅ ] is common to the eight equations, and once these subtractions are calculated, the values can be used in the eight equations, and the number of additions and subtractions can be reduced.

FIG. 1 shows the configuration of the apparatus. In this figure, the data of A described above is supplied to an input terminal 1. This data is shifted by one bit (2) to reduce the value to 1/2. The halved value is supplied to registers 3a to 3n connected in series. Then, the halved value is added to the registers 3a, 3b, 3f, 3h, 31 and 3m,
The outputs of 3n are supplied to adders 4a to 4h, respectively.

On the other hand, the above-mentioned data a is supplied to the input terminal 5. The data of the input terminal 5 is supplied to the subtractor 6, and the output of the register 3g is supplied to the subtractor 6, from which the data of a supplied to the input terminal 5 is subtracted. The subtraction output from the subtracter 6 is added to the adders 4a to 4a.
4h. Further, the addition outputs from the adders 4a to 4h are supplied to the accumulators 8a to 8h via the absolute value conversion circuits 7a to 7h, respectively. Also, the accumulator circuits 8a to 8
h is supplied with an enable control signal from the terminal 9.

Further, a residual S of the motion vector obtained by the above-described 1-pel precision motion detection is supplied to the input terminal 10. Then, the value of the residual S from the input terminal 10 and the added output from the accumulators 8a to 8h are supplied to the comparison circuit 11, and the minimum value is detected. Is taken out.

[0016] Then, in this system, data of A _i are inputted to the i-th cycle to the input terminal 1, data of a _i is input to the i-th cycle to the input terminal 5. However, A
_i is a pixel in the search range (6 × 6) of FIG. 7 described above, and a _i is 16 pixels of the reference data block shown in FIG. 6B, where i = 0, 1, 2,. -It is 35. Note that a
_{0 ~a 13, a 18, a} 19, a 24, a 25, a 30, a 31 Figure 6
B, but not corresponding to 0-13,
At cycles 18, 19, 24, 25, 30, and 31,
Dummy data is input to the input terminal 5.

Therefore, in this device, at the 14th cycle from the start of the data input, the output of the register 3g is "a value obtained by multiplying the value input to the input terminal 1 by 1/2 and delayed by 7 cycles", that is, " a _7/2 "is taken out,
At the same time, the data of “a ₁₄ ” is input to the input terminal 5.
This subtractor 6 [(A _7/2) -a _14] is calculated. Further, at this time, the output of the register 3n are retrieved "value entered in the input terminal 1 is halved by 14 cycles delayed value" or "A _0/2". In this way the adder 4h [(A _0/2) +
_{{(A 7/2) -a} 14} ] is calculated, an absolute value circuit 7
h with _{[| (A 0/2) +} {(A 7/2) -a 14} | ] to be absolute values as inputted to the cumulative addition circuit 8h.

Similarly, [(A
_7/2) values of -a _14], since also input to the adder 4a-4g, respectively _{[(A 14/2) + {} (A 7 /
2) -a _{14}], [(A 13/2) + {} (A 7/2) -a
_{14}], [(A 12/2) + {} (A 7/2) -a 14} ],
_{[(A 8/2) + {} (A 7/2) -a 14} ], [(A _{6
/ 2) + {(A 7} /2) -a 14} ], [(A _2/2) +
_{{(A 7/2) -a} 14} ], _{[(A 1/2) + {} (A 7
/ 2) -a _14}] is calculated. Further, these values are converted into absolute values by absolute value converting circuits 7a to 7g,
a to 8g. That is, to summarize the above, 1
In the fourth cycle, the value of the first term on the right side of Equation 2 [(A _{*
/ 2) + {(A 7} /2) -a 14} ] (where * = 0,
1, 2, 6, 8, 12, 13, 14) is a cumulative addition circuit 8a
To 8h.

In yet 15-17 cycle, the example cumulative addition circuit 8h _{[(A 1/2) + {} (A 8 /
2) −a ₁₅ } = “sum of equation 2 (−0.5, −0.5)
The second term "] of the right side, _{[(A 2/2) + {} (A 9/2)
−a ₁₆ } = “the third term on the right-hand side of sum (−0.5, −0.5) in Equation 2 (abbreviated as... In Equation 2)”],
_{[(A 3/2) + {} (A 10/2) -a 17} = "Number 2 s
The fourth term on the right side of um (-0.5, -0.5) (abbreviated as... in Equation 2)] is input and cumulatively added.

[0020] In 18 and 19 cycle contrast, the cumulative addition circuit 8h _{[(A 4/2) + {} (A 11 /
2) -a _{18}], [(A 5/2) + {} (A 12/2) -a
₁₉ {] are input, and these are sum (−0.
5, -0.5). Therefore, in these cycles, the enable control signal from the terminal 9 is set to low (off) so that these unnecessary data are not added up. Note that a ₁₈ and a ₁₉ are dummy data.

Hereinafter, in the 20th to 23rd cycles,
"5th on the right side of sum (-0.5, -0.5) in Equation 2
The value of "8 terms" is input, and these values are cumulatively added to the cumulative addition result up to that time. In the 24th and 25th cycles, since unnecessary data is input, the enable control signal from the terminal 9 is set to low (off) so that the unnecessary data is not added up. Further, in the 26th to 29th cycles, “sum (−0.5, −
0.5), the values of the ninth to twelfth terms on the right-hand side are input, and these values are cumulatively added to the cumulative addition results up to that time. 30,
In the 31st cycle, since unnecessary data is input, the enable control signal from the terminal 9 is set low (off) so that these unnecessary data are not added up. Then, in the 32nd to 35th cycles, “13 to 16 on the right side of the sum (−0.5, −0.5) of Equation 2”
(Final) term "is input, and these values are cumulatively added to the previous cumulative addition result. Thereby, the cumulative addition circuit 8
h contains sum (−0.5,
-0.5).

That is, in the above-described apparatus, 14 to 35
During the cycle, the values of A _{0 to} A ₂₁ indicated by arrows in FIG.
/ 2, and the output is multiplied by 2. In the accumulator 8h, sum (−0.5, −0.5) = Σ | (A _I / 2) + ｛(A _J / 2) −a _K ｝ | where I, J and K accumulate the values of the 16 terms expressed in the equation. A ₄ , A ₅ , A ₁₀ , A ₁₁ , A ₁₆ , A ₁₇ (18,
The values of the 19th, 24th, 25th, 30th, and 31st cycles) are not added by turning the enable control signal low (off).

In addition, register 14 is used during 14 to 35 cycles.
From the data m, the values of A _{1 to} A ₂₂ indicated by the arrows in FIG. 3 in the data input to the input terminal 1 are output by being multiplied by 倍. sum (−0.5,0) = {| (A _I / 2) + {(A _J / 2) −a _K } | where I, J and K are accumulated values of 16 terms expressed in the formula. You. A ₅ , A ₆ , A ₁₁ , A ₁₂ , A ₁₇ , A ₁₈ (18,
The values of the 19th, 24th, 25th, 30th, and 31st cycles) are not added by turning the enable control signal low (off).

The other values are similarly calculated by the accumulators 8a to 8f. The overall time chart is as shown in FIG. Here, a is a value input to the input terminal 1, and a to are registers 3n, 3m, 3
Data of 1, 3h, 3g, 3f, 3b, 3a and A are 1
/ 2 is a value input to the input terminal 5, and S is an enable control signal input to the input terminal 9.

S in the eight accumulator circuits 8a to 8h
Simultaneously with the completion of the calculation of um (·, ·), the value of sum (0,0) = S is input from the input terminal 10, these nine values are compared by the comparison circuit 11, and the minimum vector thereof is obtained. Is detected.

Thus, according to the above-described apparatus, the calculation is simplified by performing the common operation (subtractor 6) between the corresponding states in advance, so that the half-pel precision can be reduced with a simple apparatus configuration. Can be detected.

In the above-described apparatus, the parts of the adders 4a to 4h, the absolute value converting circuits 7a to 7h, and the accumulating circuits 8a to 8h can be realized, for example, as shown in FIG. That is, the addition of (A _I / 2) and {(A _J / 2) −a _K } is performed in the upper adder 4. Here, the carry-out (sign bit: Co) of the adder 4 is

If the value is [0], the added value is positive and is input to the lower adder 81 as it is. On the other hand, when the carry-out (Co) of the adder 4 is [1], the added value is negative. Therefore, a value obtained by inverting the added value by the inverter 71 is selected by the switch 72, and this value is supplied to the lower adder 81 and the switch 73
The value of [1] selected at (1) is input to the lowermost side (carry-in: Ci) of the adder 81. Thereby, the adder 4
Are converted into absolute values and input to the adder 81.

Further, the output of the adder 81 is input to itself via a unit delay element (register) 82. At the same time, an enable terminal EN is provided in the register 82, and an enable control signal from the terminal 9 is supplied to the enable terminal EN. Thus, cumulative addition is performed so that the above-mentioned unnecessary values are not added.

Note that this calculation circuit shows only one system, and when calculating eight values as described above, this calculation circuit is provided in parallel with eight systems. Alternatively, if there is a margin in the calculation processing time, the calculation circuit can be realized by only one system by octuple time division multiplexing. In that case, the circuit scale becomes about 1/8. Further, in the above description, the case where the reference data block is 4 × 4 has been described, but this can be generalized to an arbitrary n × m.

[0030]

According to the present invention, since the calculation is simplified by performing the common operation between the corresponding states in advance, the motion detection with half-pel accuracy is performed with a simple device configuration. Now you can do it.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an example of a motion detection device according to the present invention.

FIG. 2 is a diagram for the explanation.

FIG. 3 is a diagram for the explanation.

FIG. 4 is a time chart of an example of the motion detection device.

FIG. 5 is a configuration diagram of a main part of the motion detection device.

FIG. 6 is a diagram for explaining motion detection with one pel accuracy.

FIG. 7 is a diagram for explaining motion detection with half-pel accuracy.

[Description of Signs] 1 Input terminal to which data of A is supplied 2 Means for shifting data by 1 bit to reduce the value to 1/2 3a to 3n Registers 4a to 4h Input terminal to which data of adder 5a is supplied Reference Signs List 6 Subtractor 7a-7h Absolute value conversion circuit 8a-8h Cumulative addition circuit 9 Terminal supplied with enable control signal 10 Input terminal supplied with 1-pel precision residual S 11 Comparison circuit 12 Output of half-pel precision motion vector Terminal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06T 7/20 H04N 7/32 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A method for comparing pixels in a search range composed of a predetermined number of pixels with pixels in a reference data block composed of a number of pixels smaller than the predetermined number of pixels based on an arrangement state thereof. Calculating means for calculating a sum of absolute differences between pixels in the block and corresponding pixels in the search range for each correspondence state of pixels that the block can take in the search range, Each pixel in the range is set in advance at a time input to the arithmetic means, and
A motion detection device that inputs pixels in the search range based on time to the calculation means, and performs the calculation with pixels in the reference data block that correspond sequentially.
When detecting a motion state of one pixel or less in the search range,
The average value between adjacent pixels is compared with the pixels in the block, and the sum of the absolute difference values is obtained for each corresponding state with the pixels in the block. A motion calculation device that performs a common calculation in advance.