JP2885039B2 - Motion vector detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector detecting circuit for detecting a motion vector used in motion compensation coding of a moving image by a block matching method.

[0002]

2. Description of the Related Art At present, a motion compensation coding method is generally used as a high efficiency coding algorithm for moving images. The motion compensation coding method is a coding method that uses a displacement between images having the highest correlation, called a motion vector, to reduce redundancy that is often included between images. The motion vector used in the motion compensation coding method is generally detected by a block matching method. A method of detecting a motion vector by the block matching method will be described below with reference to FIG.

In the motion vector detection by the block matching method, first, a target block 1501 composed of M × N pixels on a target image and a search set on a reference image temporally different from the target image. Between each candidate block 1502 composed of M × N pixels in the range,
A value obtained by cumulatively adding the absolute value of the difference between the pixel values at the same position in the block is calculated (hereinafter, the difference between the pixel values at the same position in the block between the two blocks as described above is calculated. Is referred to as an inter-block error value). Then, the inter-block error values for each of the candidate blocks within the search range are compared, and the displacement between the candidate block having the smallest inter-block error value and the position where the target block is projected on the reference image is defined as a motion vector. It is a method to ask.

A conventional motion vector detecting circuit for detecting a motion vector by the block matching method is disclosed in Japanese Patent Application Laid-Open No. Hei 2-213291. Hereinafter, a conventional motion vector detection circuit will be described.

FIG. 16 is a block diagram of a conventional motion vector detecting circuit in which the size of a block of interest is 2 × 2 pixels and the number of candidate blocks included in a search range is 3 × 3 for simplicity. It is a connection diagram.

In FIG. 16, reference numerals 1601 to 1609 denote processors _{1, 1} to processor for calculating an inter-block error value.
₃ , ₃ and 1610 to 1615 are side registers for temporarily holding pixel values in the search range, 1616 to 1620 are input registers for temporarily holding pixel values in the search range input from outside the circuit, and 1621 is The minimum inter-block error value among the inter-block error values output from the processors _{1, 1} to _{3, 3} and the minimum value detection circuit for detecting the processor that has output the inter-block error value. Port R _A for inputting pixel values within
, R _B , 1624 a port S for inputting a pixel value in the block of interest, 1625 a control circuit for generating a signal S and a signal T 0, and a signal S for a processor 1601 to 1609
_{1, 1} to processors ₃ , ₃ , each side register 1610 to 16
15 and a signal for selecting data input to the input registers 1616 to 1620, and a signal T0 is a signal notifying the start of calculation of an inter-block error value.

FIG. 17 is a block diagram of each of the processors 1601 to 1609 included in the conventional motion vector detecting circuit.

In FIG. 17, reference numeral 1701 denotes a register A for holding a pixel value within a search range; 1702, a subtractor;
03 is an EOR, 1704 is an adder, 1705 is a register B for holding an intermediate result of the cumulative addition calculation, 1706 is a register C for holding an error value between blocks, and S (x, y) is transferred by a bus common to each cycle. R (i, j) in each block is a pixel value in a search range peculiar to each processor held in the register A 1701 of each processor in each cycle. .

With respect to the operation of the conventional motion vector detecting circuit configured as described above, a pixel value R (i, j) within a search range and a pixel value S (x, y) within a target block as shown in FIG. )
This will be described with reference to FIG.

[0010] pixel values R in the search range (i, j) is the second port R _B port R _A and 1623 of 1622 of FIG. 16
From one port, the scanning order indicated by the arrow in FIG. 18, that is, from the port _{RA of} 1622, R (1, 1), R (1, 2), R
(2,2), R (2,1) ··· R (4,1), R (1,3) from the port R _B of 1623, R (1,4), R (2,4), R (2,3) ... R (4,
The signals are input to the input register 1618 and the input register 1620 in the order of 3).

And a processor 1601 to 1609.
_1,1 to processors _3,3 , side registers 1610 to 161
5 and the input registers 1616 to 1620 are selected by the signal S from the pixel values R (i, j) in the search range stored in the processor or the side register or the input register on the upper, lower, or right side in the previous cycle, respectively. The pixel value R (i, j) stored in the processor or the side register or the input register in the direction to be input is input.
In this operation, the direction selected by the signal S is (1) the lower neighbor, (2) the right neighbor, (3) the upper neighbor, (4) the right neighbor, (5) returning to (1). Therefore, in order to the processor _1,1 1601 R (1,1), R ( 1,2), R (2,2), R (2,1) is sequentially to the processor ₁ of 1602 R (1,2), R (1,3), R (2,3), R
(2,2): 1609 sequentially R (3 to processors _3,3,
3), R (3,4), R (4,4), R (4,3) are 1
Pixel values in the candidate blocks included in the search range are sequentially input to the processors ₁ to ₁ to ₃ and ₃ of 601 to 1609.

Each of the processors 1601 to 1609
_From the port S of 1624, each pixel value S (x, y) in the block of interest is _transmitted to the processor _1,3 in the order indicated by the arrow in FIG. 18, that is, S (1,1), S (3). (1,2), S (2,2), S (2,1)
Are entered in the order of

[0013] 1601-1 having a structure as shown in FIG.
609 processor _1,1 to processor _3,3 , subtracter 1
702 and EOR 1703 are the absolute value | S (x, y) of the difference between the pixel value S (x, y) in the target block input in each cycle and the pixel value R (i, j) in the search range. -R (i, j) |, and a cumulative adder constituted by an adder 1704 and a register B 1705 outputs a subtractor 1 in each cycle.
S (x, y) -R (i,
j) | is cumulatively added.

For this reason, in the processors ₁ and 1601, the pixel values within the search range are R (1,1), R (1,2),
R (2,2) and R (2,1) are sequentially S (1,1), S (1,2), S (2,2), S (2,1) as pixel values in the block of interest. Is input, | S (1,1) -R (1,1) | + | S (1,2) -R (1,2) | + | S (2,2) -R (2,
2) | + | S (2,1) -R (2,1) | similarly, in the processors _{1 and 2 of} 1602, | S (1,1) -R (1,2) | + | S (1,2) -R (1,3) | + | S (2,2) -R (2,
3) | + | S (2,1) -R (2,2) |: In the processors _{3 and} 1 of 1609, | S (1,1) -R (3,3) | + | S (1, 2) -R (3,4) | + | S (2,2) -R (4,
4) | + | S (2,1) -R (4,3) | is calculated. As a result, the processors _1,1 to 1,3 to _{3 of} 1601 to 1609 calculate the inter-block error value for each candidate block included in the search range, and the inter-block error value is calculated as the next inter-block error value. By inputting the signal T0 indicating the start of the calculation, 17
06 is held in the register C.

The inter-block error values held in the registers C 1706 of the processors _{1, 1} to ₃ , ₃ of the processors 1601 to 1609 are detected as minimum values through the buses shown by broken lines in FIG. The signals are sequentially output to the circuit 1621.

The minimum value detection circuit 1621 detects the minimum inter-block error value and the position of the processor at which the minimum inter-block error value has been calculated from the input inter-block error values. As described above, 1601-1609
In the processors _{1, 1} to ₃ , ₃ , the inter-block error value for each candidate block included in the search range is calculated. Therefore, the position in the search range of the candidate block for which the minimum inter-block error value has been calculated is determined from the position of the processor for which the minimum inter-block error value has been calculated. A displacement (motion vector) from the target block to the candidate block for which the minimum inter-block error value has been calculated is output.

[0017]

However, when the conventional motion vector detecting circuit detects a motion vector of a block of interest of M × N pixels within a search range of H × V, the conventional motion vector detection circuit described above requires an external circuit every cycle. In order to reduce the number of pixels in the search range that is input from, it is necessary to have H × 2N side registers and V + 2N input registers that hold the pixel values in the search range that are not used in the calculation in the cycle. However, there is a problem that the circuit scale becomes large.

Accordingly, an object of the present invention is to provide a motion vector detecting circuit which solves the above-mentioned conventional problems.

[0019]

In order to solve the above-mentioned problems, a motion vector detecting circuit according to the present invention comprises: a block of interest composed of M × N pixels on an image of interest; Between images within the search range set on different reference images, from among candidate blocks of the same size as the block of interest in the search range, the candidate block having the highest correlation with the block of interest is detected. When obtaining a motion vector from a displacement between a candidate block and a target block, M × N pixel values in the target block are sequentially input,
A pixel value input circuit in the block of interest for selecting and outputting the output destination of the input pixel value, and a pixel value in the search range for sequentially inputting pixel values in the search range, selecting and outputting the output destination of the input pixel value an input circuit, the first register and a search range pixel values in the target block held in the first register for storing a pixel value in the block of interest inputted from the target block pixel value input circuit M × N processors each including a binomial operation unit for calculating an absolute value of a difference from a pixel value within a search range input from a pixel value input circuit;
Number of Ri Do and a second register for holding the intermediate result of the cascaded adder and accumulating calculations, the cumulative addition circuit for cumulatively adding the absolute value of the difference from above SL each processor, the cumulative addition circuit And a minimum value detection circuit for detecting the minimum value from among the cumulative addition values from the above.

[0020]

According to the present invention, the above-described configuration, the motion vector detection circuit of the present invention, M × N image against each cycle
All the elementary operations are performed by register A, a process
, Accumulator circuit comprising adder and register B
And M × N are configured during the cycle in which the pixel is input, so that the side register, input, Registers can be reduced,
The circuit scale of the motion vector detection circuit can be reduced.

[0021]

【Example】

(Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a motion vector detecting circuit according to the first embodiment of the present invention when the size of a target block is M × N pixels.

In FIG. 1, reference numeral 101 denotes a register A for holding a pixel value in a block of interest; 102, a binary operation unit for calculating an absolute value of a difference between two values; 103, a register 10;
Processor (1) consisting of 1 and 2 term operation unit 102
A processor (M × N), 104 is a port S for inputting a pixel value in the block of interest, 105 is a port for inputting a pixel value in the block of interest, and the input pixel value is stored in a processor (1) of 103
~ Processor (M × N) of the target block in pixel value input circuit for outputting to each of the registers 101, 106 and 107 is the port R _A and port R _B, 108 inputs the pixel values in the search range in the search range A pixel value is input, and the input pixel value is converted into a processor (1) to a processor (M × 103).
N) a search range pixel value input circuit for outputting to the binomial calculator 102; 109, an adder (1) to an adder (M × N); 110, a register B for holding an intermediate result of the cumulative addition calculation; Are 109 adders (1) to adders (M × N) and register 1
An accumulative addition circuit consisting of 10 and 112 is a minimum value detection circuit.

FIG. 2 is a detailed block connection diagram of the pixel value input circuit 105 in the block of interest, which is a main part of the motion vector detection circuit of FIG.

In FIG. 2, reference numeral 201 denotes a gate (1) to gate (M × N), and control signals G (1) to G (M × N) indicate gates of 201.
(1) to a signal for controlling the gate (M × N); 202, a ROM in which patterns of control signals G (1) to G (M × N) are stored;
203 is a counter.

FIG. 3 is a detailed block diagram of a search range pixel value input circuit 108 which is a main part of the motion vector detection circuit of FIG.

In FIG. 3, reference numeral 301 denotes a selector (1) to selector (M × N), and control signals F (1) to F (M × N) control the selector (1) to selector (M × N) 301. A reference numeral 302 denotes a ROM in which patterns of control signals F (1) to F (M × N) are recorded, and 303 denotes a counter.

FIG. 4 is a block diagram of the minimum value detection circuit 112 which is a main part of the motion vector detection circuit of FIG.

In FIG. 4, reference numeral 401 denotes a comparator; 402, a minimum value register for holding a minimum value; 403, a counter for generating a motion vector value corresponding to each cycle;
Is a motion vector value register for holding a motion vector value.

In order to simplify the description of the motion vector detecting circuit configured as described above, M = 2, N =
5, the operation at the time of detecting the motion vector of the target block shown in FIG. 5 is represented by a symbol S (x, y) indicating each pixel value in the target block and a symbol indicating each pixel value in the search range shown in FIG. R
This will be described below using (i, j).

First, the pixel value input circuit 10 in the block of interest
5, the pixel values from the port 104 in the target block shown in FIG. 5 are arranged in the order indicated by the arrows in FIG.
1), S (1,2), S (1,3), S (1,4), S (2,1), S (2,2),
S (2,3) and S (2,4) are input in this order. As shown in FIG. 2, each gate (1) to gate (8) of 201 includes a counter 203 and a ROM 202.
When the levels of the control signals G (1) to G (8) generated are HI, the respective registers 101 of the processor (1) to processor (8) 103 to which the respective gates are connected are:
Pixel value S in the block of interest input from port 104
Output (x, y). FIG. 6 shows signal patterns of the control signals G (1) to G (8). As a result, as shown in FIG. 7, S (1,1) is stored in the register 101 of the processor (1).
S (1,2) is stored in the register 101 of (2), S (1,3) is stored in the register 101 of the processor (3), S (1,4) is stored in the register 101 of the processor (4), Register 10 of processor (5)
1, S (2,1), S (2,2) in the register 101 of the processor (6), and S (2,2) in the register 101 of the processor (7).
3), S (2,4) is stored in the register 101 of the processor (8),
So, 103 processors (1) to processor (8)
Each of the registers 101 stores a pixel value in the target block.

In the search range pixel value input circuit 108, from the port 106, each pixel value of the band A in the search range shown in FIG. 5 is displayed in the order indicated by the arrow in the figure, that is, R (1, 1), R
(1,2), R (1,3), R (1,4), R (2,1), R (2,2), R (2,
3), R (2, 4),..., R (p, 4) are input in order, and each pixel value of band B within the search range shown in FIG. , Ie, R (1,5),
R (1,6), R (1,7), R (1,8), R (2,5), R (2,6), R (2,
7), R (2, 8),..., R (p, 8) in the order of N cycles, ie, 4 cycles, from the start of input of band A. As shown in FIG. 3, each of the selectors (1) to (8) 301 includes a counter 303 and a control signal F (1) input from the ROM 302.
If the level of F (8) is LOW, the pixel value input from the port 106 is input. If the level is HI, the pixel value input from the port 107 is input. The selectors (1) to (8) 301 are connected. 103 binary processors 102 of processors (1) to (8)
Output to FIG. 8 shows signal patterns of the control signals F (1) to F (8). As a result, as for the candidate block 1 shown in FIG. 5, from FIG. 9, R (1,1) is stored in the binomial operator 102 of the processor (1) in the first cycle, and 2 (2) of the processor (2) in the second cycle. In the third cycle, R (1,2) is stored in the binomial operator 102 of the processor (3) in the third cycle.
In the cycle, R (1,4) is supplied to the binary operation unit 102 of the processor (4).
In the fifth cycle, the binomial operator 102 of the processor (5)
In the sixth cycle, R (2,2) is supplied to the binary operation unit 102 of the processor (6), and in the seventh cycle, R (2,1) is supplied to the binary operation unit 102 of the processor (7). , 3), in the eighth cycle, R (2, 4) is added to the binary operation unit 102 of the processor (8), and so on, from the processor (1) to the binary operation unit 102 in the processor of the processor (8). Every other cycle, a pixel value in the target block held in the register A 101 of the processor and a pixel value at the same position in the candidate block 1 are input.

Focusing on the pixel value of each candidate block input to the processor (1), it can be seen from FIG. 9 that, from the first cycle, the candidate block 1 is started in the second cycle, and the candidate block 2 is started in the third cycle. , The pixel value for the next candidate block is input every other cycle, such as for candidate block 3: Similarly, pixel values for the next candidate block are sequentially input to the binomial calculator 102 of the processors (2) to (8) every other cycle.

In the processors (1) to (8) 103 in FIG. 1, the binomial operation unit 102 determines the pixel value S (x, y) in the target image held in the register 101 and the input search range. The absolute value of the difference | S (x, y) -R (i,
j) | is calculated, and the calculation result is output to 109 adders (1) to (8) in the cumulative addition circuit 111.

In the accumulator 111, an adder 109
(1) to the adder (8), in order from the processor (1), the above calculation results | S (x, y) − output from the binomial calculator 102 of the processors 103 (1) to (8). R (i, j) | is cumulatively added for each candidate block, and the result is output to the minimum value detection circuit 112.

As described above, the processor (1) to processor 103 of the block 103 are input from the pixel value input circuit 105 in the block of interest.
The pixel values S (1, 1), S (1, 2), S (1, 3), S (1, 4), S (1, 4) and S (2,
1), S (2,2), S (2,3), S (2,4) are held, and from the pixel value input circuit 108 within the search range, 103 processors (1) to 103 (8) In each of the binomial operation units 102, the pixel value in the target block held in the register 101 of the processor including the binomial operation unit 102 has the same position in the candidate block every other cycle in order from the processor (1). , And the pixel value in the candidate block input to the processor (1) is also related to the next candidate block every other cycle. As a result, in the processors (1) to (8) of 103, every other cycle in order from the processor (1), the difference between the pixel value in the target block and the pixel value at the same position in each candidate block is determined. The absolute value is calculated, and the accumulator 111
103 processors (1) every other cycle in order from (1)
~ The absolute value of the difference between the pixel value in the target block calculated by the binomial calculator 102 of the processor (8) and the pixel value at the same position in the candidate block is cumulatively added for each candidate block Therefore, the inter-block error value for each candidate block is sequentially output to the minimum value detection circuit 112.

In the minimum value detection circuit 112 shown in FIG. 4, the inter-block error value for each candidate block input by the comparator 401 in each cycle and the minimum value register 40
2 is compared with the inter-block error value that was the smallest among the inter-block error values input up to and including the previous cycle. If the input inter-block error value is smaller, the minimum value signal is output. Occurs. Then, according to the minimum value signal, the minimum value register 402 replaces the inter-block error value input in the cycle with the motion vector value register 404.
Holds the motion vector value generated from the counter 403 and corresponding to the cycle. Therefore, when the inter-block error values for all the candidate blocks within the search range have been input to the minimum value detection circuit 112, the motion vector for the block of interest in the search range is obtained in the motion vector value register 404. Are output from the minimum value detection circuit 112.

As described above, according to the present embodiment, the motion vector detection circuit of the present invention comprises the processor 103 (1) to the processor 103
Each register 101 in (M × N) holds each pixel value in the block of interest, and the processor (1) to processor 103 (M
XN) calculates the absolute value of the difference between the pixel value in the target block and the pixel value in the candidate block. In the accumulative addition circuit 111, 103 processors
(1)-The processor (M × N) calculates the absolute value of the difference between the pixel value in the block of interest and the pixel value in the candidate block by cumulative addition for each candidate block. The inter-block error value is sequentially obtained, and the minimum inter-block error value and the corresponding motion vector value are detected from the inter-block error values obtained by the minimum value detection circuit 112, thereby obtaining the motion vector for the target block. Can be detected.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 10 shows that the size of the block of interest is M × N
It is a block connection diagram of the motion vector detection circuit in the second embodiment of the present invention when it is a pixel.

In FIG. 10, reference numeral 1001 denotes a register for holding a pixel value in a target block; 1002, a binomial operator for calculating the absolute value of the difference between two values; 1003, a register 1001 and a binomial operator 1002 Processor (1) to processor (M × N), 1004 denotes a port S for inputting a pixel value in the block of interest, 1005 inputs a pixel value in the block of interest, and 1003 denotes the input pixel value.
Processor (1) to the processor block of interest in the pixel value input circuit for outputting to each of the registers 1001 (M × N), the port R _A and port R _B, 1008 1006~1007 inputs the pixel values in the search range Is a search range pixel value input circuit that inputs a pixel value within the search range and outputs the input pixel value to the binomial operation unit 1002 of the processor (1) to the processor (M × N) 1003. vessel
(1) to adder (M × N), 1010 is a register B for holding an intermediate result of the cumulative addition calculation, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 1 is that a delay element 1011 that causes a one-cycle delay is added. In FIG. 1, the adder 109 has a cascade connection of M × N stages. 1009 cascade connection (M
× N ÷ 2) stages and divided into two accumulator circuits 1012 and 1013.
1 is added to the output of the accumulator 1013 and the output of the accumulator 1013, and FIG.
12 is one, but the minimum value detection circuit 1015, the minimum value detection circuit 1016, and the minimum value detection circuits 1017 and 1017
It is a point that has been increased.

In order to simplify the description of the motion vector detecting circuit of the present invention configured as shown in FIG.
2, N = 4, and the operation will be described below.

First, the method of inputting each pixel value in the block of interest shown in FIG. 5 to the port 1004, the operation of each element in the pixel value input circuit 105 in the block of interest shown in FIG. The input method of each pixel value of the band A and the band B in the search range shown in FIG. 3, and the pixel value input circuit 1008 in the search range shown in FIG.
The operation of each element is the same as in the first embodiment. But,
By making the signal patterns of the control signals G (1) to G (8) and the control signals F (1) to F (8) stored in the ROM 202 and the ROM 303 as shown in FIGS. Each of the registers 1001 of the processors (1) to (8) holds a pixel value in the block of interest shown in FIG. 12, and each of the binary operators of the processors (1) to (8) of 1003 The pixel values in the search range shown in FIG.

First, 1003 processors (1) to (4), an accumulative addition circuit 1012 and a minimum value detection circuit 1
Attention is drawn to 015. As shown in FIG. 12, the target block pixel value input circuit 1005 inputs the target block and the image in the search range shown in FIG. F consisting of two raced Fields
If it is a rame (frame) image, S (1, 1), S (1,
3), a field composed of S (2, 1) and S (2, 3) (hereinafter S (1,
Field containing 1), S (1,3), S (2,1) and S (2,3)
d1) is held. In addition, the search range pixel value input circuit 1008 allows the processor 1003
Each binomial operation unit 1002 of (1) to processor (4) has
As shown in 4, two cycles every order from the processor (1), the pixel value at the same position in a pixel value of Field1 the candidate block in the block of interest held in the register 1001 in the processor is input . Further, the pixel value in the candidate block input to the processor (1) is related to the next candidate block every other cycle.

By adding 1011 delay elements (1) to 10 (4), the accumulative addition circuit 1012 includes 1003 processors (1) to 1003 every two cycles in order from the processor (1).
The values output from the binomial calculator 1002 of the processor (4) are cumulatively added.

[0047] Accordingly, in 1003 the processor (1) to the processor (4), the 2-cycle intervals from the processor (1) in order, the pixel value at the same position in the pixel value and the respective candidate blocks Field1 in the block of interest The absolute value of the difference is calculated and the cumulative addition circuit 1012 performs cumulative addition for every one candidate block every two cycles in order from the processor (1). The obtained inter-block error values for each candidate block are sequentially output. Then, the minimum value detection circuit 10
At 15, the minimum inter-block error value and the motion vector value corresponding to the cycle in which it is detected are detected from among the inter-block error values for each candidate block obtained from the pixel value of Field 1 input in each cycle. , Field1 is detected.

Next, 1003 processors (5) to (8), an accumulative addition circuit 1013, and a minimum value detection circuit 1
Attention is drawn to 016. As shown in FIG. 12, the target block pixel value input circuit 1005 stores the target block and the image in the search range shown in FIG. Assuming that the frame image is composed of two raced Fields, a Field composed of S (1, 2), S (1, 4), S (2, 2), and S (2, 4) S (1,2), S (1,4), S (2,2) and S
(Fields including (2, 4) are referred to as Field 2). In addition, by the pixel value input circuit 1008 in the search range,
As shown in FIG. 14, the processor (5) 1003 of the processor (5) to the processor (8) 1003 has a processor (5)
From the 2-cycle intervals in order, the pixel value at the same position in a pixel value of Field2 the candidate block of interest in the block stored in the register 1001 in the processor are input. Further, the pixel value in the candidate block input to the processor (5) is related to the next candidate block every other cycle.

By adding 1011 delay elements (5) to 10 (8), the accumulative addition circuit 1013 includes 1003 processors (5) to 1003 every two cycles in order from the processor (5).
The values output from the binary operation unit 1002 of the processor (8) are cumulatively added.

[0050] Accordingly, in 1003 processor (5) to the processor (8), the 2-cycle intervals in order from the processor (5), the pixel values at the same position in a pixel value in Field2 and in each candidate block within the block of interest The absolute value of the difference is calculated and the cumulative addition circuit 1013 performs cumulative addition for every candidate block in order from the processor (5) every two cycles, so that the minimum value detection circuit 1016 uses the pixel value of Field 2 The obtained inter-block error values for each candidate block are sequentially output. Then, the minimum value detection circuit 10
In step 16, the minimum inter-block error value and the motion vector value corresponding to the cycle in which it is detected are detected from among the inter-block error values for each candidate block obtained from the pixel values of Field 2 input in each cycle. , Field 2 of the block of interest is detected.

The inter-block error value | S (1,1) -R (1 + X, 1 + Y) | + | S (1,3) -R (1 + X, 3) calculated with the pixel value of Filed1 + Y) | + | S (2,
1) -R (2 + X, 1 + Y) | + | S (2,3) -R (2 + X, 3 + Y) | (X and Y are integers)
And the inter-block error value | S (1,2) -R (1 + X, 2 + Y) | + | S (1,
4) -R (1 + X, 4 + Y) | + | S (2,2) -R (2 + X, 2 + Y) | + | S (2,4) -R (2 + X, 4
+ Y) | is the inter-block error value | S (1, 1) -R (1 + X,
1 + Y) | + | S (1,3) -R (1 + X, 3 + Y) | + | S (2,1) -R (2 + X, 1 + Y) | + | S
(2,3) -R (2 + X, 3 + Y) | + | S (1,2) -R (1 + X, 2 + Y) | + | S (1,4) -R (1+
X, 4 + Y) | + | S (2, 2) -R (2 + X, 2 + Y) | + | S (2, 4) -R (2 + X, 4 + Y) |. As shown in FIG. 14, the calculation of the inter-block error value calculated by the pixel value of Filed1 is advanced by one cycle compared to the calculation of the inter-block error value for the same motion vector as that calculated by the pixel value of Filed2. Therefore, the value output from the cumulative addition circuit 1012 one cycle earlier and the value output from the cumulative addition circuit 1013 are added using an addition circuit 1014 including a delay element and an adder. Then, the minimum value detection circuit 1017 calculates the minimum inter-block error value and the corresponding Frame pixel value from the inter-block error values calculated using the Frame pixel values output from the addition circuit 1014. A motion vector value is detected.

As described above, according to the present embodiment, M × N delay elements for delaying one cycle are added in the accumulating circuit, and the cascaded adders of M × N stages, the register B, A cumulative adder circuit composed of delay elements is divided into (M × N ÷ 2) stages of cascade-connected adders and registers B and a cumulative adder circuit A and a cumulative adder circuit B composed of delay elements. The value detection circuit is composed of the minimum value detection circuit A and the minimum value detection circuit B.
By adding one to another, a motion vector obtained from the pixel value of each field can be detected. Further, by providing the addition circuit 1014 and the minimum value detection circuit 1017, the motion vector obtained from the pixel value of Frame can also be detected. It can be detected at the same time.

[0053]

As described above, according to the present invention, the target block composed of M × N pixels on the target image and the target block within the search range set on the reference image temporally different from the target image are described. Between the image and the candidate block having the same size as the target block in the search range, the candidate block having the highest correlation with the target block is detected, and the motion vector is calculated from the displacement between the candidate block and the target block. Is obtained, M × N pixel values in the block of interest are sequentially input,
A pixel value input circuit in the block of interest for selecting and outputting the output destination of the input pixel value, and a pixel value in the search range for sequentially inputting pixel values in the search range, selecting and outputting the output destination of the input pixel value an input circuit, the first register and a search range pixel values in the target block held in the first register for storing a pixel value in the block of interest inputted from the target block pixel value input circuit M × N processors each including a binomial operation unit for calculating an absolute value of a difference from a pixel value within a search range input from a pixel value input circuit;
Number of Ri Do and a second register for holding the intermediate result of the cascaded adder and accumulating calculations, the cumulative addition circuit for cumulatively adding the absolute value of the difference from above SL each processor, the cumulative addition circuit And a minimum value detection circuit for detecting the minimum value from among the cumulative addition values from the pixels.
A, a processor consisting of a binary operation unit, an adder and
An accumulator circuit including a register B and an M × N circuit structure
With this configuration, it is possible to realize a motion vector detection circuit whose circuit scale is significantly reduced as compared with a conventional motion vector detection circuit.

[0054]

[Brief description of the drawings]

FIG. 1 is a block diagram of a motion vector detection circuit according to a first embodiment of the present invention;

FIG. 2 is a detailed block connection diagram of a pixel value input circuit in a block of interest, which is a main part of the motion vector detection circuit in the embodiment.

FIG. 3 is a block connection diagram of a search range pixel value input circuit which is a main part of the motion vector detection circuit in the embodiment.

FIG. 4 is a block connection diagram of a minimum value detection circuit which is a main part of the motion vector detection circuit in the embodiment.

FIG. 5 is a conceptual diagram showing a pixel value in a target block and a pixel value in a search range of the motion vector detection circuit in the embodiment.

FIG. 6 is a conceptual diagram showing signal patterns of control signals G (1) to G (8) of the motion vector detection circuit in the embodiment.

FIG. 7 is a conceptual diagram showing data held by registers in processors (1) to (8) in each cycle of the motion vector detection circuit in the embodiment.

FIG. 8 is a conceptual diagram showing signal patterns of control signals F (1) to F (8) of the motion vector detection circuit in the embodiment.

FIG. 9 is a diagram showing data input to a binary operation unit in each of the processors (1) to (8) in each cycle of the motion vector detection circuit in the embodiment.

FIG. 10 is a block diagram of a motion vector detection circuit according to a second embodiment of the present invention;

FIG. 11 is a conceptual diagram showing signal patterns of control signals G (1) to G (8) of the motion vector detection circuit in the embodiment.

FIG. 12 is a conceptual diagram showing data held by registers A in processors (1) to (8) in each cycle of the motion vector detection circuit in the embodiment.

FIG. 13 is a conceptual diagram showing signal patterns of control signals F (1) to F (8) of the motion vector detection circuit in the embodiment.

FIG. 14 shows a processor in each cycle in the embodiment.
(1) to (8) are diagrams showing data input to the binary operation unit in the processor (8)

FIG. 15 is a conceptual diagram of motion vector detection by a conventional block matching method.

FIG. 16 is a block diagram of a conventional motion vector detection circuit.

FIG. 17 is a block diagram of a processor which is a main part of a conventional motion vector detection circuit.

FIG. 18 is a conceptual diagram showing pixel values in a target block and a search range of a conventional motion vector detection circuit.

[Explanation of symbols]

101 register A 102 2 dyadic operation 103 the processor (1) to the processor (M × N) 104 port S 105 target block pixel value input circuit 106-107 ports R _A and port R _B 108 search range the pixel values input circuit 109 Adder (1) to adder (M × N) 110 Register B (1) to Register B (M × N) 111 Cumulative adder circuit 112 Minimum value detection circuit 201 Gate (1) to Gate (M × N) 202 ROM 203 Counter 301 Selector (1) to selector (M × N) 302 ROM 303 Counter 401 Comparator 402 Minimum value register 403 Counter 404 Motion vector value register 1001 Register A 1002 Binomial operation unit 1003 Processor (1) to processor (M × N) N) 1004 port S 1005 target block pixel value input circuit 1006 to 1007 ports R _A and port R _B 10 8 Pixel value input circuit within search range 1009 Adder (1) to adder (M × N) 1010 Register B (1) to Register B (M × N) 1011 Delay element (1) to delay element (M × N) 1012 Cumulative addition circuit A 1013 Cumulative addition circuit B 1014 Addition circuit 1015 Minimum value detection circuit A 1016 Minimum value detection circuit B 1017 Minimum value detection circuit C

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-5-236455 (JP, A) JP-A-5-328332 (JP, A) JP-A-6-96209 (JP, A) JP-A-7-96 115646 (JP, A) JP-A-6-225287 (JP, A) IEEE Transactions on circuits and systems, Vol. 36, No. 10, p. 1309-1316 (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N ^7/ 24-7/68 G06T 7/20

Claims (1)

(57) [Claims] 1. An image processing apparatus according to claim 1, further comprising: a block in the search range between a block of interest formed of M × N pixels on the target image and an image in a search range set on a reference image temporally different from the target image. When a candidate block having the highest correlation with the target block is detected from candidate blocks having the same size as the target block, and a motion vector is obtained from a displacement between the candidate block and the target block, the M × N
The pixel value input circuit sequentially inputs the pixel values, selects the output destination of the input pixel value and outputs the selected pixel value, and sequentially inputs the pixel values in the search range, and determines the output destination of the input pixel value. A search range pixel value input circuit for selecting and outputting, a first register for holding a pixel value in the block of interest inputted from the above-mentioned pixel value input circuit for block of interest, and a first register. M × N processors comprising a binomial calculator for calculating the absolute value of the difference between the held pixel value in the target block and the pixel value in the search range input from the search range pixel value input circuit; the M × N Ri Do and a second register for holding the intermediate result of the cascaded adder and accumulating calculations, the cumulative addition circuit for cumulatively adding the absolute value of the difference from above SL each processor, the from the cumulative addition circuit
And a minimum value detection circuit for detecting a minimum value from among the cumulative addition values of the motion vector.