KR100230473B1 - Display device - Google Patents

Abstract

The present invention relates to a display device having a light modulation layer such as a liquid crystal, and more particularly to a liquid crystal display device, which includes a liquid crystal panel, a signal line driver circuit for generating image data and a signal to be supplied to the signal line by a first clock signal, A clock signal generation circuit for generating the first clock signal, the second clock signal and the adjustment clock signal from the reference clock signal; and a clock signal generation circuit for generating a clock signal for the image data, And a delay time adjustment circuit for delaying the image data for a predetermined time based on the adjustment clock signal from the clock signal generation circuit for adjusting the delay time of the first clock signal generated by the clock signal generation circuit , And a display device capable of accurately matching the phase of the first clock signal and the phase of the image data It characterized.

Description

Display device

FIG. 1 is a circuit diagram of a control circuit of a liquid crystal driving apparatus according to a first embodiment of the present invention. FIG.

Fig. 2 is a circuit diagram showing a modification of the control circuit portion in Fig. 1; Fig.

FIG. 3 is a circuit diagram showing another modification of the control circuit portion in FIG. 1; FIG.

FIG. 4 is a circuit diagram of a signal line driver circuit of a liquid crystal driving apparatus according to a first embodiment of the present invention. FIG.

Fig. 5 is a circuit diagram showing a modification of the signal line driver circuit in Fig. 4; Fig.

Fig. 6 is a circuit diagram showing another modification of the signal line driver circuit in Fig. 4; Fig.

FIG. 7 is a time chart of each signal of the first embodiment; FIG.

FIG. 8 is a view for explaining a duty ratio in the present invention; FIG.

FIG. 9 is a circuit diagram of an analog type PLL circuit. FIG.

10 is a circuit diagram of a digital type PLL circuit;

FIG. 11 is a circuit diagram of a control circuit of a liquid crystal driving apparatus according to a second embodiment of the present invention. FIG.

FIG. 12 is a time chart of each signal of the second embodiment; FIG.

13 is a circuit diagram of a driving circuit of a conventional liquid crystal display device.

14 is a circuit diagram of the control circuit.

FIG. 15 is a time chart of each conventional signal.

DESCRIPTION OF THE REFERENCE NUMERALS

9: horizontal clock signal generation circuit part 10: control circuit

12: control signal generation circuit part 14: delay time adjustment circuit part

16, 35, 54: PLL circuit 18: latch

20: Amplifier 24: Signal line driver circuit

26: shift register 28: first latch

30: second latch 32: driver circuit portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, particularly a liquid crystal display device, having a light modulation layer such as a liquid crystal.

[Configuration of Driver Circuit of Active Matrix Type Liquid Crystal Display Device]

FIG. 13 shows the structure of the driving circuit 100 of the active matrix type liquid crystal display device.

Reference numeral 102 denotes a liquid crystal display panel, which includes, for example, a first electrode substrate having a plurality of pixel electrodes arranged in a matrix, a second electrode substrate having a counter electrode facing the pixel electrode, And a liquid crystal as a light modulating layer disposed between the electrode substrate and the second electrode substrate through the alignment film.

Reference numeral 104 denotes a signal line driver circuit which outputs an image signal to a signal line electrically connected to the pixel electrode of the liquid crystal display panel 102 through a switch element such as a thin film transistor (hereinafter abbreviated as TFT).

Reference numeral 108 denotes a scanning line driver circuit for outputting a scanning signal to a scanning line for controlling a switching element electrically connected to the pixel electrode of the liquid crystal panel 102.

Reference numeral 110 denotes a control circuit which outputs image data, a horizontal clock signal CK1 and a start signal ST to the signal line driver circuit 104 and outputs a vertical clock signal CK2 .

[Configuration of control circuit]

Details of the control circuit 110 will be described with reference to FIG.

The control circuit 110 includes a horizontal clock signal generation circuit portion 109, a signal generation circuit portion 112, and a delay time adjustment circuit portion 113.

The horizontal clock signal generating circuit unit 109 generates a horizontal clock signal CK1 and an adjusting clock signal SCK based on a reference clock signal CK from an external source such as a personal computer.

The delay time adjustment circuit unit 113 receives the image data of red (R), green (G), and blue (B) (hereinafter abbreviated as RGB) Is generated by the time until the horizontal clock signal CK1 is generated and the timing of the horizontal clock signal CK1 is matched with the image data. As the circuit configuration, the latches 114 of signal lines of image data of RGB are connected in series in multiple stages, and the Mars data is delayed by the movement of the latches 114. The delay time is output by the horizontal clock signal generating circuit 109 to the latch 114 of each stage, and the delay time is adjusted by this signal.

The signal generating circuit unit 112 generates the vertical clock signal CK2 and the horizontal start signal ST based on the synchronizing signal EN and the reference clock signal CK from the outside such as the personal computer.

The signal generating circuit unit 112 outputs the generated vertical clock signal CK2 and the horizontal start signal ST to the horizontal clock signal generating circuit unit 109 in the same manner as the delay time adjusting circuit unit 113, Is delayed based on the adjustment clock signal SCK by the time until the horizontal clock signal CK1 is generated and adjusted so that the timing, i.e., the phase, with the horizontal clock signal CK1 is matched.

[Operation state of drive circuit]

The operation state of the drive circuit 100 having the above-described structure will be described.

The horizontal clock signal CK1 is supplied to the horizontal clock signal generation circuit portion 109 and the signal generation circuit portion 112 in which the RGB image data, the synchronizing signal EN and the reference clock signal CK are input to the control circuit 110. [ The vertical clock signal CK2 and the horizontal start signal ST and outputs the adjustment clock signal SCK to the respective latches 114 of the delay time adjustment circuit 113 to output the RGB image data and the horizontal clock signal SCK, And adjusts the phase of the signal CK1.

The signal line driver circuit 104 generates an image signal to be output to each signal line of the liquid crystal panel 102 based on the inputted horizontal clock signal CK1, horizontal start signal ST, image data and load signal LD do.

The scanning line driver circuit 108 generates and outputs a scanning signal to be sent to the scanning line of the liquid crystal panel 102 based on the vertical clock signal CK2.

15 shows a timing chart of the horizontal clock signal CK1, the horizontal start signal ST, the image data, the load signal LD and the vertical clock signal CK2.

The driving circuit 100 has the following problems.

The duty ratio of the reference clock signal CK may be shifted while the reference clock signal CK input from the outside is notified to the circuit elements such as the phase inverting circuit of the horizontal clock signal generating circuit unit 109. [ If the duty ratio is out of order, the duty ratio of the horizontal clock signal CK1 output to the signal line driver circuit 104 is naturally also shifted. Particularly, when the phase inversion circuit 150 is disposed after outputting the final-stage adjustment clock signal SCKn as in the control circuit 110 of FIG. 14, as shown in the timing chart of FIG. 15, the horizontal clock signal CK1 are sampled using the falling timing of the RGB image signal data. At this time, if the duty ratio is out of order, the sampling timing is out of order, and the setup period becomes uneven or the other image signal data is sampled.

(2) In the control circuit 110, the horizontal clock signal generation circuit portion 109 outputs the adjustment clock signal SCK to each of the latch 114 and the signal generation circuit portion 112 of the delay time adjustment circuit portion 113 However, since the latch 114 is configured in parallel for RGB, a signal is sent to the latch 114 in parallel for the adjustment clock signal SCK. Therefore, the waveform of the adjusting clock signal SCK is distorted due to the capacity of the latch 114 and the phase is shifted. Thus, the image data of RGB, the horizontal clock signal CK1 and the horizontal start signal ST There is a problem that the phase of the load signal LD or the like deviates.

(3) When a signal such as the horizontal clock signal CK1 or image data of RGB is input to the signal line driver circuit 104, the horizontal clock signal CK1 ) Or the waveform of the image data of RGB are deformed and the phases are out of phase with each other.

That is, the phases of the various signals are shifted from each other in the time chart of FIG. 15 due to the problems (1) to (3). Particularly, since the horizontal clock signal CK1 and the image data are different from the vertical clock signal CK2 and the horizontal start signal ST and the period thereof is narrow, the phases tend to be out of phase with each other. In order to realize a display image of high precision, The higher the operation speed, the greater the problem becomes.

Therefore, the present invention is to provide a display device capable of realizing accurate sampling of image data even if the operating speed is increased to realize high precision, thereby realizing a good display image.

According to a first aspect of the present invention, there is provided a display device comprising a display panel having a plurality of display pixels electrically connected to a plurality of signal lines, clock signal generating means for generating a first clock signal and an adjusting clock signal from an input reference clock signal, And a phase adjusting means for adjusting the relationship between the phase of the input image data and the phase of the first clock signal on the basis of the adjusting clock signal and a phase adjusting means for correcting at least the image data based on the first clock signal And a signal line driver circuit for supplying an image signal to the signal line, wherein the clock signal generating means comprises a duty ratio adjusting circuit for correcting the duty ratio of the first clock signal output to the signal line driver circuit to about 50% And is built in.

According to the present invention, since the duty ratio of the first clock signal to be output to the signal line driver circuit is corrected to about 50%, sampling of accurate image data can be realized even if the operation speed is increased to realize high precision, An image is realized.

According to a second aspect of the present invention, there is provided a display device including a display panel having a plurality of display pixels electrically connected to a plurality of signal lines, a display panel for generating a first clock signal and a clock signal for adjustment from an input reference clock signal, And a phase adjusting means for adjusting the relationship between the phase of the input image data and the phase of the first clock signal based on the adjusting clock signal, and a control circuit for controlling at least the image data and the first clock signal The clock signal generation means and the phase adjustment means are connected to each other through the PLL circuit for the adjustment clock signal in the display device provided with the signal line driver circuit for supplying the image signal to the signal line on the basis of the signal line driver circuit.

In the present invention, it is also possible to realize accurate sampling of image data, thereby realizing a good display image.

According to a third aspect of the present invention, there is provided a display panel comprising a display panel having a plurality of display pixels electrically connected to a plurality of signal lines, a control circuit section for outputting image data, a first clock signal and a control signal, And a signal line driver circuit for supplying an image signal to the signal line based on the first clock signal or the control signal, wherein the signal line driver circuit includes a first phase adjusting means on the input side of at least one signal of the image data, the first clock signal or the control signal .

By arranging the first phase adjusting means in the signal line driver circuit in this way, accurate image data sampling can be realized, thereby realizing a good display image.

According to a fourth aspect of the present invention, there is provided a display panel including a display panel having a plurality of display pixels electrically connected to a plurality of signal lines, a display panel for generating a first clock signal and a clock signal for adjustment from an input reference clock signal, And a phase adjustment means for adjusting the relationship between the phase of the input image data or the control signal and the phase of the first clock signal based on the adjustment clock signal, and a control circuit including the image data, the first clock signal, And a signal line driver circuit for supplying an image signal to the signal line on the basis of the control signal, wherein the clock signal generating means includes a clock signal generating means for generating a clock signal having a duty ratio for correcting the duty ratio of the first clock signal output to the signal line driver circuit to about 50% And an adjustment circuit is incorporated.

[First Embodiment]

A first embodiment of a driving circuit of an active matrix liquid crystal display device of the present invention will be described below with reference to Figs. 1 to 10. The overall structure of the active matrix liquid crystal display device is substantially the same as that of the thirteenth aspect.

[Configuration of control circuit]

FIG. 1 is a circuit diagram of the control circuit 10 in the drive circuit of this embodiment, and is integrally formed in a semiconductor chip as an integrated circuit element.

The control circuit 10 includes a horizontal clock signal generating circuit 9 for generating a horizontal clock signal CK1 and an adjusting clock signal SCK and a horizontal start signal generating circuit 9 for generating a horizontal start signal ST, a vertical clock signal CK2, And a delay time adjusting circuit 14 for delaying the image data of RGB inputted by an 8-bit digital signal for a predetermined time, for example, do.

7 shows a timing chart of the horizontal clock signal CK1, the horizontal start signal ST, the image data, the load signal LD and the vertical clock signal CK2.

The horizontal clock signal generating circuit 9 includes a phase inversion circuit 50 composed of an inverter circuit or the like for inverting the phase of an input reference clock signal CK by 180 °, The latches 18R-1, 18R-2, ... 18R-n, the latches 18G-1, 18G-2, ... 18G-n, and the latches 18B- 2, ... 18B-n and the signal generating circuit 11 are connected in parallel to each other in order to output the adjusting clock signal SCK to the latch (which has almost the same structure as the delay time adjusting circuit 14 and not shown here) And buffers 52-1, 52-2, ..., and 52-n are connected and configured. The output of the buffer 52-n that controls the last unit latches 18R-n, 18G-n, and 18B-n of the delay time adjustment circuit unit 14 and the final unit latch of the control signal generation circuit unit 11 The output of the PLL circuit 54 is branched into two and the other is connected to the final stage latches 18R-n 18G-n and 18B- n and the final stage of the control signal generation circuit portion 11 are connected to the latch and the other is led to the phase inversion circuit 56 composed of an inverter circuit or the like. The output from the phase inversion circuit 56 is output from the control circuit 10 as the horizontal clock signal CK1.

The delay time adjustment circuit unit 14 is configured so that a plurality of latches 18 are connected in series for each image data of RGB and are output through the amplifier 20 at the end thereof. The latches 18R-1, 18R-2, ..., and 18R-n are connected in series in the case of red (R) image data and the image data of green (G) B are similarly connected in series with latches 18G-1, 18G-2, ... 18G-n and latches 18B-1, 18B-2, ..., 18B-n.

The first adjustment clock signal SCK-1 output from the buffer 52-1 of the horizontal clock signal generation circuit portion 9 is supplied to the first stage of each image data of RGB, that is, the latch 18R-1, the latch 18G- And 18B-1, respectively. And each latch 18 is operated by this first adjustment clock signal SCK-1.

Similarly, the latch 18 for each stage except the final stage receives the adjustment clock signal SCK, whereby each image data of RGB is delayed by a predetermined time.

When the n-th adjustment clock signal (SCK-n) output from the PLL circuit 54 is input to the last stage latch 18R-n, the latch 18G-n and the latch 18B-n, Each of the data is delayed for a predetermined time so as to be synchronized with the horizontal clock signal CK1.

The control signals such as the horizontal start signal ST, the vertical clock signal CK2 and the load signal LD generated by the control signal generation circuit portion 11 are supplied to the control signal generation circuit 11 based on the respective adjustment clock signals SCK And is delayed for a predetermined time so as to be synchronized with the horizontal clock signal CK1.

Here, the PLL circuit refers to a phase-locked loop (PLL) circuit, compares both signals so that the oscillation output always coincides with the frequency and phase of the input signal, and the duty ratio is 50% It is a circuit that controls the oscillator so that it is always substantially zero.

Here, the duty ratio is defined as follows. As shown in Fig. 8, in the waveform of the pulse signal, Let t1 and t2 be T0 = t1-t0 when the amplitude (A) is a zero-cross point of 1/2 and the period T = t2-t0 of this waveform. And the duty ratio = T0 / T.

The control circuit 10 generates the horizontal clock signal CK1 based on the output from the PLL circuit unit 54 and also outputs the latches 18R-n and 18G- the horizontal start signal ST and the vertical clock signal CK2 outputted from the control circuit 10 and the respective image signal data or the horizontal start signal ST, CK2 and the load signal LD are substantially in phase with each other.

In addition, since the duty ratio of the output from the PLL circuit 54 is almost 50%, the signal line driver circuit 24 outputs the RGB The timing of the sampling is not largely deviated even in the case of sampling the image signal data of the high-speed image signal, and the image signal data can be reliably sampled even in the high-speed operation.

In addition, even if the duty ratio of the input reference clock signal CK deviates significantly from 50%, the duty ratio is compensated by the above configuration.

[Configuration of signal line driver circuit]

FIG. 4 is a circuit diagram of the signal line driver circuit 24 in the driver circuit of the present embodiment, in which a plurality of signal line driver circuits 24 are electrically connected and arranged. Each signal line driver circuit 24 includes, for example, a shift register portion 26, a first latch portion 28, a second latch portion 30, and a plurality of And a driver circuit 32 of the driver circuit 32. A horizontal start signal ST and a horizontal clock signal CK1 from the control circuit 10 are input to the shift register 26 and RGB image data is input to the first latch unit 28. [ The load signal LD from the control circuit 10 is also input to the second latch 30. An image signal supplied to the signal line in the driver circuit portion 32 is generated by these signals.

The horizontal start signal ST and the RGB image data are directly inputted to the shift register unit 26 and the first latch unit 28 while the horizontal clock signal CK1 is supplied to the shift register unit 26 . The distortion of the waveform of the horizontal clock signal CK1 and the deviation of the duty ratio are corrected by passing through the PLL circuit 34 and the phase of the horizontal clock signal CK1 is not shifted from that of the RGB image data.

With such a configuration, the display operation is speeded up, and even if the period of the horizontal clock signal CK1 or the period of the image data is narrowed, the deterioration of the horizontal clock signal CK1 due to the influence of the time constant of the wiring, This makes it possible to provide a liquid crystal display device of a size larger than that of the liquid crystal display device, since both of the liquid crystal display device and the liquid crystal display device can be synchronized at high speed.

In the present embodiment, each of the signal line driver circuits 24 is integrally formed in the semiconductor chip as integrated circuit elements, and the PLL circuit 34 common to the respective signal line driver circuits 24 is disposed as a separate component. However, As shown in FIG. 5, the signal line driver circuit 24 may incorporate the PLL circuit 34 in the same semiconductor chip.

In addition to the horizontal clock signal CK1, as shown in FIG. 6, a PLL circuit 34 may be provided for signals such as RGB image data, a start signal ST, and a load signal LD.

[Configuration of PLL circuit]

In the PLL circuit, there are an analog type PLL circuit and a digital type PLL circuit. In this embodiment, any PLL circuit may be used. In the digital type PLL circuit, however, the phase comparison result of the input frequency and the output frequency is digitized, A very large time constant can be realized by detecting and controlling only very low frequency phase fluctuations by averaging the data, thereby making it possible to lower the cutoff frequency of the jitter. Also, it is easy to control the duty ratio to 50%.

9 shows an example of the analog type PLL circuit 40. The phase comparator 42, the analogue filter 44 and the VCXO (voltage control transmitter) 46 are connected in series, (42). In this case, when the degree of control of the VCXO increases, it is easy to control the duty ratio to 50% accordingly.

FIG. 10 is an example of a digital PLL circuit 48. FIG. This includes a DIV (frequency divider) 50 and a phase comparator 52, a D / A converter 54, a digital filter 56, an A / D converter 58, a VCXO (voltage control transmitter) 60, And this output is fed back to the phase comparator 52 through the DIV 62. [ The DIV 62 is also preset by the digital filter 56.

[Modifications]

Although the PLL circuit 54 is connected to the buffer 52-n of the last stage in the control circuit 10 of FIG. 1e, the PLL circuit 54 may be provided on the output side of the phase inversion circuit 56 as shown in FIG.

Further, if the PLL circuit is provided on the input side of the phase inversion circuit 50 on the input side as in the third aspect, even if the duty ratio of the external clock signal CK deviates, the waveform is shaped, . In particular, in such a configuration, the control signal generation circuit section 12 generates control signals such as the start signal ST and the load signal LD based on the reference clock signal CK whose duty ratio is compensated by the PLL circuit The phases of the various signals are almost coincident with each other, whereby a good display image can be realized even in a high-speed operation.

Although the PLL circuit is used to set the duty ratio to 50% in the above embodiment, a zero cross detector or the like may be used instead.

[Second Embodiment]

Hereinafter, the control circuit 10 of the second embodiment of the present invention will be described based on FIG. Also in this embodiment, the control circuit 10 is integrally formed in the semiconductor chip as an integrated circuit element.

The control circuit 10 generates a horizontal clock signal CK1, a horizontal start signal ST and a vertical clock signal CK2 based on a reference clock signal CK and a synchronizing signal EN from an external source such as a personal computer, A signal generating circuit section 12 for generating a clock signal SCK and a delay time adjusting circuit section 14 for delaying the RGB image data for a predetermined time. Here, the horizontal clock signal generation circuit portion 9 in the first embodiment is matched with the signal generation circuit portion 11 that generates signals such as the horizontal start signal ST, the vertical clock signal CK2, and the load signal LD Control signal generation circuit unit 12 ".

The control signal generation circuit 12 outputs the adjustment clock signal SCK as a reference signal for controlling the delay time adjustment circuit 14 but does not directly output the adjustment clock signal SCK to the delay time adjustment circuit 14, And outputs it through the circuit 16.

The delay time adjustment circuit 14 has a plurality of latches 18 connected in series for each image data of RGB, and finally outputted through the amplifier 20. The latches 18R-1, 18R-2, ..., and 18R-n are connected in series in the case of red (R) image data, and the image data of green (G) B are similarly connected in series with latches 18G-1, 18G-2, ..., 18G-n and latches 18B-1, 19B-2, ..., 18B-n.

The first adjustment clock signal SCK-1 output from the control signal generation circuit 12 is corrected through the PLL circuit 16-1 and becomes the first adjustment clock signal SCK-1, 1, the latch 18G-1, the latch 18B-1, and the control signal generation circuit portion 12 in parallel. And each latch 18 is operated by this corrected first adjustment clock signal SCK-1. That is, since the PLL circuit 16-1 is provided, even if the latch 18-1 is connected in three stages in parallel, the phase of the first adjustment clock signal SCK-1 does not deviate from that of the latch 18-1. Therefore, the phase of the RGB image data and the first adjustment clock signal SCK-1 can be accurately matched.

Also, in the latches 18R-2, 18G-2, and 18B-2, since the second adjustment clock signal SCK-2 is input through the PLL circuit 16-2, the phases of both can be precisely adjusted. Similarly, in the latch 18 of each stage, the adjustment clock signal SCK is corrected by the PLL circuit 16, so that the phase can be accurately adjusted.

The PLL circuit 16 used in the control circuit 10 and the signal line driver circuit 24 subsequent to the control circuit 10 use the one described in the first embodiment.

According to the present invention, accurate image data and sampling can be realized even if the operating speed is increased to realize high precision, thereby providing a display device that realizes a good display image.

Claims (11)

A display panel having a plurality of display pixels electrically connected to a plurality of signal lines, a display panel for outputting an input reference clock signal as a horizontal clock signal, and a horizontal start signal and a horizontal start signal based on the reference clock signal and the input digital image data, A control circuit for generating synchronous digital image data synchronized with a horizontal clock signal, and a signal line driver circuit for sampling the synchronous digital image data based on the horizontal start signal and the horizontal clock signal and supplying a corresponding image signal to the signal line A first to N-th latch circuits connected in series to each other for sequentially transmitting the digital image data to synchronize the digital image data with the horizontal clock signal; And a duty ratio adjusting circuit for adjusting a horizontal clock signal A display device, characterized by. The display device according to claim 1, wherein the duty ratio adjustment circuit is disposed in the vicinity of an output position at which the horizontal clock signal is output from the control means. The display device according to claim 1, wherein the duty ratio adjustment circuit is disposed in the vicinity of an input position to which the reference clock signal is input by the control means. The display device according to claim 1, wherein the duty ratio adjustment circuit is a PLL circuit. The display device according to claim 1, wherein the signal line driver circuit includes phase adjusting means at an input side of at least one of the synchronous digital image data, the horizontal start signal and the horizontal clock signal. The display device according to claim 5, wherein the phase adjusting means corrects the duty ratio of at least one of the synchronous digital image data, the horizontal start signal and the horizontal clock signal to about 50%. The display device according to claim 5, wherein the phase adjusting means is a PLL circuit. 2. The display device according to claim 1, wherein the duty ratio adjusting circuit outputs the horizontal clock signal that matches the phase and frequency of the reference clock signal. 9. The display device according to claim 8, wherein the duty ratio adjusting circuit corrects the duty ratio of the reference clock signal to about 50%. 6. The display device according to claim 5, wherein the duty ratio adjusting circuit outputs the horizontal clock signal that matches the phase and frequency of the reference clock signal. The display device according to claim 5, wherein the signal line driver circuit integrally includes the phase adjusting means.