JP3226464B2 - Three-phase clock pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-phase clock pulse generating circuit for generating a three-phase clock pulse, which is a driving pulse for a liquid crystal display element or the like and has a three-phase pulse train signal having different phases.

[0002]

2. Description of the Related Art In recent years, a technique for driving a display element by a digital scanning drive method, such as a liquid crystal display panel (hereinafter simply referred to as a liquid crystal panel), has been widely used. In this digital scanning drive method, a clock pulse which is a reference signal for sampling display data of a display element is used in a multi-phase form for reasons such as securing sampling time and reducing EMI such as interference and radiation. In particular, three-phase clock pulses are often used because of the ease of sampling corresponding to each color of RGB.

Further, with the widening of display elements such as a liquid crystal panel, the width has been widened by a video signal for displaying an image having an aspect ratio of 4: 3 (hereinafter, referred to as 4: 3 aspect). When displaying a 4: 3 aspect image on a 16: 9 aspect display element, the display function is to use the side panel mode in which the image is shrunk in the left-right direction and the remaining part is used for other display such as blackout. It is needed.

As described above, a conventional three-phase clock pulse generating circuit for generating a three-phase clock pulse which is a driving pulse for a liquid crystal display element or the like and is composed of a three-phase pulse train signal having different phases will be described with reference to the drawings. This will be described below.

FIG. 3 shows an example of the configuration of a conventional three-phase clock pulse generating circuit and its peripheral circuits in consideration of the side panel mode. In FIG. 3, reference numeral 1 denotes an inverter for oscillating a source oscillation pulse, and 2 denotes a frequency of the source oscillation pulse from the inverter 1 divided by 3 and the phases thereof are 1 to each other.
3 frequency dividing circuit for generating three pulses Φ1, Φ2, Φ3 different by 20 °, 3 frequency dividing circuit for dividing pulse Φ1 by 2, 4 frequency dividing circuit for dividing pulse Φ3 by 2 and 5 pulse When used in the side panel mode, the divide-by-two circuits 6, 7 and 8 for dividing Φ2 by two are arranged such that the video part sampling period is on the (2) side during the display part other than the video part, that is, the side panel part. The sampling period switches to the (1) side, and when used in the normal mode other than the side panel mode (hereinafter referred to as “full mode”), the changeover switch is always fixed to the (1) side. A buffer circuit connected to the output side of the switches 6, 7, 8;
12, 13, and 14 are sampling pulses CPH1, CPH2, and CPH3 applied to a liquid crystal display element and the like, respectively.
An output terminal 15; an n frequency dividing circuit 15 for dividing the source oscillation pulse from the inverter 1 to 1 / n up to the horizontal scanning frequency; 16 a horizontal synchronizing signal (hereinafter referred to as H. Sync.) Input line; Reference numeral 17 denotes an output signal of the n frequency dividing circuit 15 and H.H. Sync. A phase comparison circuit 18 for detecting a phase difference between the signals; a timing pulse generator 18 including each of the above circuits as a component;
Is an integration circuit for smoothing the output signal of the phase comparison circuit 17;
0 is a variable capacitance diode, 21, 26 and 27 are DC blocking capacitors, 22 is a first resonance coil, 23 is a resonance capacitor, 24 is a second resonance coil, and 25 is off in full mode. By being turned on in the side panel mode, the frequency of the source oscillation clock (hereinafter, referred to as a basic clock) in the full mode is changed to the series of the variable capacitance diode 20, the first resonance coil 22, and the resonance capacitor 23. Determined based on the frequency of the source oscillation pulse by the inverter 1 when using a resonance circuit,
The frequency of the basic clock in the side panel mode is determined by using a series resonance circuit including the variable capacitance diode 20, a coil having a parallel configuration of the first resonance coil 22 and the second resonance coil 24, and a resonance capacitor 23. A switching diode 28 which is determined based on the frequency of the source oscillation pulse of the inverter 1;
9 to 34 are resistors, 35 is a switching transistor which is turned on in a side panel mode, 36 and 37 are switching transistors which are turned on in a full mode, 38
Is a variable resistor for adjusting the free oscillation frequency of the basic clock in the side panel mode, 39 is a variable resistor for adjusting the free oscillation frequency of the basic clock in the full mode, 40 is a switch for switching between full mode and side panel mode,
41 and 42 are voltage values of VCC1 and VCC2 (V
CC2> VCC1).

The operation of the conventional three-phase clock pulse generating circuit configured as described above will be described below with reference to FIGS. FIG. 4 shows the relationship between the waveform of a 4: 3 aspect video signal in the horizontal cycle and how the video signal looks when displayed on a widened 16: 9 aspect display element. It is. FIG. 4 (a)
Is a display at the time of the full mode display. In this case, the displayed image is expanded in the horizontal direction. FIG. 4B shows a case in which the display image is reduced to 3/4 times in the horizontal direction and the remaining image is used for other display such as blackout in the side panel mode display.

In the side panel mode shown in FIG. 4B, the image display period is 50 μs, which is the same as that in the full mode.
ec is necessary, and when the side panel section is sampled by the sampling clock of the same frequency as the video section,
Since 16.6 μsec is required for the display period of the side panel section, a total time of 66.6 μsec per horizontal scan is required, which is 63.56 μsec of the actual horizontal period.
It becomes bigger than. Therefore, a method is generally adopted in which the sampling clock of the side panel section is set to twice the frequency of the sampling clock of the video section and sampling of the video section and the side panel section is completed within an actual horizontal period.

FIG. 5 is a timing chart for explaining the operation of the conventional three-phase clock pulse generation circuit shown in FIG. 3 and its peripheral circuits. FIG. 5A shows the timing in the full mode, and shows the timing when the full mode / side panel mode changeover switch 40 in FIG. 3 is set to the FULL side. In FIG. 5A, VCO is a source oscillation pulse, CPH1, CPH2, and CPH3 are sampling pulses obtained by dividing the frequency of the VCO by 3. When CPH1 is used as a reference, CPH2 has a phase delay of 120 °, and CPH3 has 240. ° The phase is delayed. In the full mode, the switching diode 25 is turned off, the switching transistors 36 and 37 are turned on, and the free oscillation frequency of the source oscillation is adjusted by the variable resistor 39.

FIG. 5B shows the timing in the side panel mode, and shows the timing when the full mode / side panel mode switch 40 in FIG. 3 is set to the SIDE side. At this time, since the side panel section needs to have a sampling clock frequency that is 3/2 times that of the full mode, the switching diode 25 is turned on in the side panel mode and the source oscillation frequency is set to 3/3 of the full oscillation mode. It is set to double.

At the timing of display on the side panel section, the changeover switches 6, 7, and 8 are switched to (1) side, and the source oscillations are obtained as sampling pulses CPH1, CPH2, and CPH3 as shown in FIG. A sampling pulse obtained by dividing the pulse by three is output.

On the other hand, in the case of the image part, the display is horizontally shifted by 3/4.
In order to double the sampling rate, the sampling clock of the video section must be reduced to 3/4 times that in the full mode. Therefore, at the time of image display, the changeover switches 6, 7, and 8 are set to (2)
Side and the sampling pulses CPH1, CPH
As shown in FIG. 5 (b) II, sampling pulses obtained by dividing the source oscillation pulse by 6 are output as CPH2 and CPH3, respectively. The switching transistor 35 is turned on, and the free oscillation frequency of the source oscillation is adjusted by the variable resistor 38.

In FIG. 3, an oscillation circuit composed of an inverter 1, a variable capacitance diode 20, a first resonance coil 22, a second resonance coil 24, and a resonance capacitor 23, an n-divider circuit 15, Phase comparison circuit 17,
The integration circuit 19 controls P using Sync as a reference signal
An LL (phase-locked loop) is configured to correct for a deviation of the source oscillation frequency due to a temperature change, a power supply voltage change, or the like.

[0013]

However, in the conventional three-phase clock pulse generating circuit as described above, the 16: 9
When a display in a side panel mode is performed by a display element having a wide aspect, as shown in FIG. 3, a circuit for switching a source oscillation frequency by an inverter 1 such as a second resonance coil 24 to a changeover switch 40, as shown in FIG. And the peripheral circuit becomes complicated.

The present invention is to solve the above-mentioned conventional problem, and is to provide a case in which a side panel display in a side panel mode can be performed on a wide display element having a screen aspect ratio of 16: 9. However, there is provided a three-phase clock pulse generation circuit capable of simplifying a peripheral circuit configuration therefor.

[0015]

In order to solve the above-mentioned problems, a three-phase clock pulse generating circuit according to the present invention comprises a wide-screen display element having a screen aspect ratio of 16: 9.
Since a side panel mode is supported by using a divide-by-2 circuit, a divide-by-4 circuit, four delay circuits, and three clock changeover switches of the source oscillation pulse, even when the function of the side panel mode is provided, the source oscillation A peripheral circuit such as a switching circuit is not required.

As described above, the aspect ratio of the screen is 16:
Even in the case where the side panel display can be performed in the side panel mode on the widened display element 9, the peripheral circuit configuration can be simplified.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A three-phase clock pulse generation circuit according to a first aspect of the present invention is a three-phase clock pulse generation circuit for generating a three-phase clock pulse composed of three-phase pulse train signals having mutually different phases. A source oscillation circuit that oscillates a source oscillation pulse for determining a frequency thereof, and a source oscillation pulse from the source oscillation circuit is delayed by 360 ° in terms of a source signal and a reference oscillation cycle in order to generate a basic clock serving as a system clock. 120 ° delay signal and 7 in terms of source oscillation cycle
A divide-by-three circuit that divides the frequency of the source oscillation pulse from the source oscillation circuit by two by dividing the source oscillation pulse from the source oscillation circuit by two, and a source oscillation pulse from the source oscillation circuit. 4
A divide-by-4 circuit for dividing the frequency, a first delay circuit for delaying the divide-by-2 signal from the divide-by-2 circuit by a time corresponding to approximately 240 ° of the source oscillation cycle, and a divide-by-2 from the divide-by-2 circuit A second delay circuit for delaying the frequency-divided signal by a time corresponding to approximately 480 ° of the source oscillation cycle, and a third delay circuit for delaying the frequency-divided signal from the quarter-frequency circuit by a time corresponding to approximately 480 ° of the source oscillation cycle. And a fourth circuit for delaying the frequency-divided signal from the frequency-divided circuit by a time corresponding to approximately 960 ° of the source oscillation cycle.
, The reference signal from the divide-by-3 circuit and the 2
First switching means for switching between a divide-by-2 signal from the divider circuit and a divide-by-4 signal from the divide-by-4 circuit and outputting as a first pulse train signal;
° a second switching means for switching between a delay signal, a delay signal from the first delay circuit, and a delay signal from the third delay circuit and outputting the same as a second pulse train signal; Switching between the 240 ° delay signal, the delay signal from the second delay circuit, and the delay signal from the fourth delay circuit, and outputting as a third pulse train signal
And a switching means for the three-phase pulse train signal.
A first pulse train signal output from the first switching means, a second pulse train signal output from the second switching means, and a third pulse signal output from the third switching means.
Constitutes the three-phase clock pulse.

According to a second aspect of the present invention, there is provided a three-phase clock pulse generating circuit, wherein the first, second, third, and fourth delay circuits according to the first aspect of the present invention are provided by using only an inverter element or a change point of a source oscillation pulse. , And a combination of the decoded value and the inverter element.

According to these configurations, a widened display element having a screen aspect ratio of 16: 9 is connected to a source oscillation pulse divide-by-2 circuit, a divide-by-4 circuit, four delay circuits, and three clock changeover switches. Is used to support the side panel mode. Therefore, even when the function of the side panel mode is provided, a peripheral circuit such as a source oscillation switching circuit is not required.

Hereinafter, a three-phase clock pulse generation circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a three-phase clock pulse generation circuit according to the present embodiment. In FIG. 1, reference numeral 51 denotes an inverter for oscillating a source oscillation pulse, and 52 denotes three pulses Φ1 and Φ1 which divide the frequency of the source oscillation pulse from the inverter 51 by 3 and have phases different from each other by 120 °.
2, a divide-by-3 circuit for generating Φ3, 53 is an inverter 5
A divide-by-2 circuit that divides the source oscillation pulse from 1 by 2; 54 is a divide-by-4 circuit that divides the source oscillation pulse from the inverter 51 by 4; A first delay circuit 56 delays the output of the divide-by-2 circuit 53 by a time corresponding to approximately 480 ° of the cycle of the source oscillation pulse. Here, the delay circuit 55 secures a delay of 180 ° based on the source oscillation pulse and realizes the remaining delay of 60 ° using a delay element such as an inverter.
Has a delay of 360 ° secured based on a source oscillation pulse, and the remaining delay of 120 ° is realized using a delay element such as an inverter. 57, a third delaying the output of the 4 frequency dividing circuit 54 by a time corresponding to approximately 480 ° of the cycle of the source oscillation pulse;
The delay circuit 58 delays the output of the divide-by-4 circuit 54 by a time corresponding to approximately 960 ° of the cycle of the source oscillation pulse.
Is a delay circuit. Here, the delay circuit 57 secures a delay of 360 ° based on the source oscillation pulse, and realizes the remaining 120 ° delay using a delay element such as an inverter, and the delay circuit 58 uses a delay element based on the source oscillation pulse. A delay of 900 ° is ensured, and the remaining 60 ° delay is realized using a delay element such as an inverter. 59, 60, and 61 are always fixed to the (1) side when used in the full mode, and when used in the side panel mode, the video section sampling period is
On the (3) side, the side panel section sampling period is switched to the (2) side. Each of the changeover switches as first, second, and third changeover means. 62, 63, and 64 are changeover switches 59, 60, and 61, respectively. The buffer circuits 65, 66, 67 connected to the output side of the
Sampling pulses CPH1, CPH2, CPH3 applied to a liquid crystal display element or the like as a third pulse train signal
An output terminal 68 for dividing the source oscillation pulse from the inverter 51 by 1 / n up to the horizontal scanning frequency; 69, a horizontal synchronizing signal (hereinafter referred to as H. Sync.) Input line; 70 denotes an output signal of the n frequency dividing circuit 68 and H.H. Sync. A phase comparison circuit 71 for detecting a phase difference between the timing pulse generator 71 and a timing pulse generator 72
Is an integration circuit for smoothing the output signal of the phase comparison circuit 70;
3 is a variable capacitance diode, 74 is a DC blocking capacitor, 75 is a resonance coil, 76 is a resonance capacitor, 7
Reference numeral 7 denotes a bypass capacitor that grounds the cathode side of the variable capacitance diode 73 in an AC manner. The oscillation frequency of the source oscillation clock (hereinafter referred to as a basic clock) is determined by the variable capacitance diode 73, the resonance coil 75, and the resonance capacitor 7.
6 is determined based on the series resonance circuit composed of 78 is a variable resistor for adjusting the free oscillation frequency of the basic clock,
Reference numeral 79 denotes a switch for switching between a full mode and a side panel mode, and reference numeral 80 denotes an input line of a DC power supply having a voltage value of VCC.

In the above, the variable capacitance diode 7
3, a source oscillation circuit is constituted by the inverter 51 and the series resonance circuit including the resonance coil 75 and the resonance capacitor 76.

The operation of the three-phase clock pulse generating circuit configured as described above will be described below with reference to the drawings. FIG. 2 is a timing chart for explaining the operation of the three-phase clock pulse generation circuit shown in FIG. In FIG. 2, VCO is a source oscillation pulse, and uses the same pulse without switching between the full mode and the side panel mode.

FIG. 2A shows the timing in the full mode, and shows the timing when the full mode / side panel mode switch 79 in FIG. 1 is set to FULL. In FIG. 2A, CPH1, CPH2, C
PH3 is a sampling pulse obtained by dividing the frequency of the VCO by 3. When the sampling pulse CPH1 is used as a reference, the sampling pulse CPH2 is delayed by 120 ° and the sampling pulse CPH3 is delayed by 240 °.

FIG. 2B shows the timing in the side panel mode, and shows the timing when the full mode / side panel mode switch 79 in FIG. 1 is set to the SIDE side.

At this time, the side panel display section needs to have a sampling clock frequency 3/2 times that of the full mode, but in the present embodiment, the source oscillation pulse VCO
2 is used, and the sampling pulses CPH1, CPH2, and CPH3 shown in I of FIG. 2B are used as sampling clocks. In FIG. 2B, the sampling pulse CPH1 is a source oscillation pulse VCO
Is divided by two, and the sampling pulse CPH2
Is the source oscillation pulse VC from the sampling pulse CPH1.
Since the phase is delayed by 240 ° in terms of O, the sampling pulse CP is first delayed by 180 ° in terms of VCO.
A pulse indicated by a solid line of H2 is generated, and the pulse is further delayed by 60 ° in terms of VCO using an internal delay element such as an inverter. In practice, a pulse indicated by a dotted line of the sampling pulse CPH2 is used. The sampling pulse CPH3 is 48 times smaller than the sampling pulse CPH1 in terms of the source oscillation pulse VCO.
Because it is delayed by 0 °, it is 360
A pulse indicated by a solid line of the sampling pulse CPH3 delayed by .degree. Is generated, and then the pulse is further delayed by 120.degree. In terms of VCO using an internal delay element such as an inverter, and a pulse indicated by a dotted line of the sampling pulse CPH3 is actually used.

In the video display section, the sampling clock of the video section must be reduced to 3/4 times that in the full mode in order to make the display 3/4 times in the horizontal direction. , The frequency of the source oscillation pulse VCO divided by 4 is used, and the sampling pulse CPH shown in FIG.
1, CPH2 and CPH3 are used as sampling clocks. In FIG. 2B, the sampling pulse CPH1 is obtained by dividing the frequency of the source oscillation pulse VCO by 4, and the sampling pulse CPH2 is obtained by delaying the phase of the sampling pulse CPH1 by 480 ° in terms of the source oscillation pulse VCO. First, 360 in VCO conversion
A pulse indicated by a solid line of the sampling pulse CPH2 delayed by .degree. Is generated, and then the pulse is further delayed by 120.degree. In terms of VCO using an internal delay element such as an inverter. In practice, a pulse indicated by a dotted line of the sampling pulse CPH2 is used. The sampling pulse CPH3 is equal to the sampling pulse CPH.
Since the source oscillation pulse is delayed by 960 ° in terms of VCO, the sampling pulse CPH3 which is delayed by 900 ° in terms of VCO is first made as a solid line pulse, and then the VCO is converted using an internal delay element such as an inverter. , And a pulse indicated by a dotted line of the sampling pulse CPH3 is actually used.

The inverter 51, the variable capacitance diode 73, the resonance coil 75, and the resonance capacitor 7 shown in FIG.
6, a PLL (Phase Lock Loop) using a horizontal synchronizing signal (H. Sync.) As a reference signal is constituted by an oscillating circuit constituted by 6, an n frequency dividing circuit 68, a phase comparing circuit 70, and an integrating circuit 72. It corrects for the deviation of the source oscillation frequency caused by the change, the power supply voltage change, and the like.

As described above, as is clear from the comparison between FIG. 3 and FIG. 1, the aspect ratio of the screen is 16: 9.
Even when a configuration is made such that a side panel display can be performed in a side panel mode on a widened display element, the peripheral circuit configuration for that can be simplified.

As a result, it is possible to reduce the number of direct members and the area of the printed circuit board, reduce the number of adjustment steps, and stabilize the source oscillation circuit.

[0030]

As described above, according to the present invention, a widened display element having an aspect ratio of a screen of 16: 9 is provided by dividing a source oscillation pulse by two, by four, and by four delay circuits. Since three clock changeover switches are used to cope with the side panel mode, a peripheral circuit such as a source oscillation frequency switching circuit can be dispensed with even when the function of the side panel mode is provided.

Therefore, the aspect ratio of the screen is 16: 9.
Even when a configuration is made such that a side panel display can be performed in a side panel mode on a widened display element, the peripheral circuit configuration for that can be simplified.

As a result, it is possible to reduce the number of straight members, reduce the area of the printed circuit board, reduce the number of adjustment steps, and stabilize the source oscillation circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a three-phase clock pulse generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the embodiment.

FIG. 3 is a configuration diagram of a conventional three-phase clock pulse generation circuit.

FIG. 4 is an explanatory diagram of a display image on a 16: 9 wide display element.

FIG. 5 is a timing chart showing the operation of a conventional three-phase clock pulse generation circuit.

[Explanation of symbols]

 Reference Signs List 51 Inverter 52 Divide-by-3 circuit 53 Divide-by-2 circuit 54 Divide-by-4 circuit 55, 56, 57, 58 Delay circuit 59, 60, 61 Switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/30 G09G 3/36 H03K 5/15 H04N 5/66 102

Claims (2)

(57) [Claims] In a three-phase clock pulse generating circuit for generating a three-phase clock pulse composed of three-phase pulse train signals having mutually different phases, a source oscillation for determining a frequency for generating a basic clock serving as a system clock is provided. A source oscillation circuit that oscillates a pulse, a 120 ° delay signal delayed by 360 ° in terms of a reference signal and a source oscillation cycle, and a 240 ° delay signal delayed by 720 ° in terms of a source oscillation cycle from the source oscillation pulse from the source oscillation circuit Divides the source oscillation pulse from the source oscillation circuit by two, and divides the source oscillation pulse from the source oscillation circuit by four.
A frequency divider; a first delay circuit for delaying the frequency-divided signal from the frequency divider by a time corresponding to approximately 240 ° of the source oscillation cycle; A second delay circuit for delaying a time corresponding to approximately 480 ° of the oscillation cycle, and a third delay circuit for delaying the frequency-divided signal from the four-frequency divider for a time corresponding to approximately 480 ° of the source oscillation cycle. A fourth delay circuit for delaying the divide-by-4 signal from the divide-by-4 circuit by a time corresponding to approximately 960 ° of the source oscillation cycle, a reference signal from the divide-by-3 circuit and a signal from the divide-by-2 circuit; First switching means for switching between the divide-by-2 signal and the divide-by-4 signal from the divide-by-4 circuit and outputting it as a first pulse train signal; the 120 ° delay signal from the divide-by-3 circuit; And the delay signal from the third delay circuit Second switching means for switching the delay signal and outputting as a second pulse train signal; a 240 ° delay signal from the third frequency divider, a delay signal from the second delay circuit, and a delay from the fourth delay circuit. A first pulse train signal output from the first switching means as a three-phase pulse train signal; and a second switching means for switching between the first pulse train signal and the second switching signal as a three-phase pulse train signal. A third pulse train signal output from the third switching means and the third pulse train signal output from the third switching means.
Phase clock pulse generation circuit. 2. The first, second, third, and fourth delay circuits include:
2. The three-phase clock pulse generation circuit according to claim 1, wherein the three-phase clock pulse generation circuit is constituted by a combination of an inverter element alone or a decoded value at a change point of the source oscillation pulse and the inverter element.