JP3276797B2 - Horizontal output pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal output pulse generating circuit for a horizontal deflection circuit used in a TV receiver, a computer display, and the like, and more particularly to a horizontal output pulse generating circuit for preventing a horizontal output transistor from being destroyed.

[0002]

2. Description of the Related Art In a horizontal deflection circuit used in a TV receiver, a computer display, or the like, a horizontal output pulse is generated in accordance with a horizontal synchronization signal, and a horizontal deflection coil is driven in accordance with the horizontal output pulse to perform a horizontal deflection operation. Is going. FIG.
Indicates such a horizontal deflection circuit. A horizontal synchronization signal is separated from a video signal applied to an input terminal (1) by a synchronization separation circuit (2) and applied to an AFC1 circuit (3). The AFC1 circuit (3) consists of a phase comparator and LPF
It is composed of Horizontal oscillator (4) is 32fH
(FH is the frequency of the horizontal synchronizing signal), and its frequency and phase are controlled by the output signal of the AFC1 circuit (3). Horizontal countdown circuit (5)
Is composed of a plurality of T-type flip-flops and a logic circuit connected in cascade, and divides a clock signal having a frequency of 32 fH from the horizontal oscillator (4) to obtain various timings and pulses at a horizontal synchronization signal frequency. Generate a divided output signal of width.

The frequency-divided output A of the horizontal synchronizing signal frequency from the horizontal countdown circuit (5) is applied to the AFC1 circuit (3), and is output by the AFC1 circuit (3), the horizontal oscillator (4), and the horizontal countdown circuit (5). One AFC loop is configured. Therefore, the horizontal countdown circuit (5) generates frequency-divided output signals locked to the horizontal synchronization signal from the synchronization separation circuit (2).

The frequency-divided outputs B and C of the horizontal synchronizing signal frequency from the horizontal countdown circuit (5) are supplied to a phase shift circuit (6).
Applied to the first and second phase shift circuits (7) and (8) to generate horizontal output pulses. By adjusting the output signal phases of the first and second phase shift circuits (7) and (8), the inversion timing of the flip-flop circuit (9) changes and the phase of the output pulse changes.

The output signal of the phase shift circuit (6) is applied as a horizontal output pulse to a horizontal drive circuit (10), and the horizontal drive circuit (10) outputs a horizontal output transistor (not shown) in the horizontal output circuit (11). ) Is driven, and a horizontal deflection current flows through a horizontal deflection coil (not shown) of the cathode ray tube (12). A part of the output of the horizontal output circuit (11) is applied to the high voltage circuit (13) to supply a high DC voltage to the cathode ray tube (12),
(Flyback pulse).

The horizontal FBP is connected to A through a terminal (14).
The signal is applied to FC2 (15), and the phase is compared with the frequency-divided output D of the horizontal synchronization signal frequency from the horizontal countdown circuit (5). AFC2 (15) has the same configuration as AFC1 (3). The output signal of AFC2 (15) is supplied to first and second phase shift circuits (7) and (8) in phase shift circuit (6).
And the output signal phases of the first and second phase shift circuits (7) and (8) are adjusted, so that the inversion timing of the flip-flop circuit (9) changes and the phase of the output pulse changes. .

The AFC2 circuit (15) is a phase shift circuit (6)
And the phase of the horizontal output pulse, which is the output signal of the horizontal FBP, coincides with the phase of the horizontal FBP. Therefore, the horizontal deflection circuit shown in FIG. 2 generates a horizontal output pulse according to the horizontal synchronization signal, and drives the horizontal deflection coil according to the horizontal output pulse to perform a horizontal deflection operation.

[0008]

In a horizontal deflection circuit of a television receiver or a computer display using a cathode ray tube, a surge due to discharge in the tube is applied to an IC substrate in the device. The horizontal output pulse within must be generated correctly. However, in the horizontal deflection circuit of FIG. 2, the horizontal output pulse may not be generated correctly due to a surge.

Although the influence of the surge is applied to the entire horizontal deflection circuit, the flip-flop circuit (9) for determining the phase of the horizontal output pulse is particularly susceptible. For example, if the pulse width of the horizontal output pulse is short due to the effect of the surge, a high voltage is generated in the horizontal output transistor that loads the coil, and the horizontal output transistor is destroyed when the next horizontal output pulse is applied. Was feared.

This will be described with reference to FIG. Now, the output signals of the first and second phase shift circuits (7) and (8) are shown in FIG.
If the flip-flop circuit (9) performs a falling operation, as shown in FIGS. 3A and 3B, the Q output of the flip-flop circuit (9) is as shown in FIG. FIG. 3C shows a case where a normal signal is output as a horizontal output pulse. Here, it is assumed that a surge occurs at the second falling edge in FIG. 3A, that is, near the time t1. Then, in response to the surge, the flip-flop circuit (9) may cause an abnormal operation, and the waveforms shown in FIGS. 3D and 3E may be generated. In the case of FIG. 3D, one horizontal output pulse is not generated. In this case, since the frequency of the horizontal output pulse is lowered and the timing of turning on the horizontal output transistor is delayed, the horizontal output transistor may be destroyed when the next horizontal output pulse is applied.

In the case of FIG. 3E, the pulse width of the horizontal output pulse becomes narrow. In this case, the horizontal output transistor may be destroyed when the next horizontal output pulse is applied for the above-described reason.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a horizontal synchronization signal frequency and a first state change (signal level is changed from H level to L level or from L level to H level). ), A second frequency-divided output signal having a horizontal synchronization signal frequency and exhibiting a second state change at a timing later than the first state change;
A third frequency-divided output signal having a horizontal synchronizing signal frequency and a pulse width shorter than the horizontal output pulse and capable of driving a horizontal output transistor, and synchronizing the first to third frequency-divided output signals with an external horizontal synchronizing signal; A horizontal countdown circuit for inverting the horizontal countdown circuit according to the first and second frequency-divided output signals and generating a pulse having a pulse width and a cycle of a horizontal output pulse corresponding to a horizontal synchronization signal And an OR gate to which the output signal of the flip-flop circuit and the third frequency-divided output signal of the horizontal countdown circuit are applied, wherein a pulse obtained from the OR gate is a horizontal output pulse.

[0013]

According to the present invention, there is provided a horizontal countdown circuit for generating a third frequency-divided output signal having a horizontal synchronizing signal period in synchronization with an external horizontal synchronizing signal, and an OR gate. When not applied to the drive circuit, since the third frequency-divided output signal from the horizontal countdown circuit is output as a pseudo horizontal output pulse, there is no possibility that the subsequent horizontal output transistor will be destroyed.

[0014]

FIG. 1 shows a horizontal output pulse generating circuit according to the present invention. (20) is a first to third frequency-divided output signals (20) synchronized with an external horizontal synchronizing signal and having a horizontal synchronizing signal period. X, Y, Z) horizontal countdown circuit,
(21) The third frequency-divided output signal Z and the phase shift circuit (6)
Or gate to which the output signal is applied.

In FIG. 1, the same circuit elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. The first and second divided output signals (X, Y) in FIG. 1 are assumed to be equal to the divided outputs B and C of the horizontal synchronization signal frequency in FIG.
Now, assuming that both the AFC1 circuit (3) and the AFC2 circuit (15) are operating correctly, the first and second frequency-divided output signals (X, Y) are output from the horizontal countdown circuit (20).
Occurs. The first and second frequency-divided output signals (X, Y)
Has the waveforms shown in FIGS. 3A and 3B, and the Q output of the flip-flop circuit (9) is as shown in FIG. FIG. 3C shows a case where a normal signal is output as a horizontal output pulse.

Here, it is assumed that a surge occurs at the second falling edge in FIG. 3A, that is, near the time t1. Then
In response to the surge, the flip-flop circuit (9) may cause an abnormal operation, and the waveforms shown in FIGS. 3D and 3E may be generated. However, in FIG. 1, the third frequency-divided output signal (Z) is generated from the horizontal countdown circuit (20). The third frequency-divided output signal (Z) has a waveform shown in FIG. 3 (f) and is applied to the horizontal drive circuit (10) via the OR gate (21).

For this reason, the waveforms shown in FIGS. 3D and 3E are generated near time t1, and even if a sufficient horizontal output pulse cannot be obtained, the pseudo horizontal output pulse shown in FIG. Can be supplied to a subsequent circuit. Therefore, the pseudo horizontal output pulse of FIG. 3F in which a high voltage is not generated in the horizontal output transistor having the coil as a load is wider than the pulse width of the normal horizontal output pulse shown in FIG. In this case, since the normal operation is hindered, the pulse width of the regular horizontal output pulse shown in FIG. 3C is made narrower so that the horizontal output transistor is not destroyed.

FIG. 4 shows a method for setting the generation timing of the pseudo horizontal output pulse shown in FIG.
(A) shows the case where the pulse of FIG. 3 (c) is shifted to the left to the maximum, and FIG. 4 (b) shows the case where the pulse of FIG. 3 (c) is shifted to the right to the maximum. FIG.
4A is a logical product of FIG. 4B and FIG. If it is in this range, the operation of the AFC2 circuit (15) can be continued without adversely affecting the operation.

[0019]

As described above, according to the present invention, a horizontal countdown circuit for generating a third frequency-divided output signal having a horizontal synchronizing signal cycle in synchronization with an external horizontal synchronizing signal, and an OR gate are provided. Since the third frequency-divided output signal from the countdown circuit is output as a pseudo horizontal output pulse, there is no risk that the subsequent horizontal output transistor will be destroyed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a horizontal output pulse generation circuit according to the present invention.

FIG. 2 is a circuit diagram showing a conventional horizontal output pulse generation circuit.

FIG. 3 is a waveform chart for describing the operation of FIG. 2;

FIG. 4 is a waveform chart for describing the operation of FIG. 1;

[Explanation of symbols]

 (6) Phase shift circuit (20) Horizontal countdown circuit (21) OR gate

Claims (1)

(57) [Claims] A first state change having a horizontal synchronizing signal frequency (whether the signal level is from H level to L level or L level)
From the H level) and a second state change (signal level from H level to L level) having a horizontal synchronizing signal frequency and having a timing delayed from the first state change.
Le or L level and the second division output signal exhibiting H level), Pas from the horizontal output pulse having a horizontal synchronizing signal frequency
A horizontal countdown circuit for generating a third frequency-divided output signal having a short pulse width and capable of driving a horizontal output transistor and synchronizing the first to third frequency-divided output signals with an external horizontal synchronization signal; The horizontal output signal is inverted according to the first and second frequency-divided output signals, and is inverted according to the horizontal synchronization signal.
A flip-flop circuit for generating a pulse having a pulse width and a period, and an OR gate to which an output signal of the flip-flop circuit and the third frequency-divided output signal of the horizontal countdown circuit are applied. A horizontal output pulse generating circuit, wherein a pulse obtained from the OR gate is a horizontal output pulse.