KR0147579B1 - 2 picture displaying in the wide television - Google Patents

Abstract

The present invention relates to a two-screen simultaneous viewing circuit in a wide television that allows two 4: 3 screens to be simultaneously viewed without wider distortion on a wide television having a 16: 9 aspect ratio.

According to the present invention, a write clock locked to the synchronization signal of the main and sub screens is used for the frame memory of the main screen and the sub screen, and a clock locked to the synchronization signal of the main screen is used as the read clock of the main and sub screens. By synchronizing the sub-screens and varying the vertical deflection current and the vertical blank signal at the time of split screen output, it is possible to simultaneously view two 4: 3 screens without distortion on a wide television having an aspect ratio of 16: 9.

Description

Two-screen simultaneous viewing on wide television

1 is a block diagram of a two-screen simultaneous viewing circuit in a wide television according to the present invention;

2 is an operation timing diagram of each part of FIG.

3 is a state diagram showing an embodiment of screen distortion when watching two screens simultaneously;

4 is a state diagram showing an embodiment of a two-screen simultaneous viewing screen according to the present invention.

* Explanation of symbols for main parts of the drawings

100: main screen processing circuit 200: sub screen processing circuit

300: control signal generator 400: deflection unit

500,700: PLL part 600: switching part

800: main / sub switch 900: matrix

101,201 tuner 102202 sync separation and color demodulation

103,203: A / D converter 104,204: frame memory

105,205: D / A converter

The present invention relates to a two-screen simultaneous viewing circuit in a wide television having a 16: 9 aspect ratio, and more particularly, two 4: 3 screens can be simultaneously viewed without wider distortion on a wide television having a 16: 9 aspect ratio. To a two-screen simultaneous viewing circuit on a wide television.

Conventionally, a composite video signal having a 4: 3 screen is displayed on a distorted 16: 9 screen using a memory or a time compressed to a 4: 3 screen, and a picture in a margin (Picture In Picture; PIP, Picture Out Picture; Wide television is implemented as a method of displaying POP).

However, the PIP or POP screen has a disadvantage in that it displays an advertisement before a program of a desired channel is started, rather than watching, and performs only a monitoring role of watching another channel as the main screen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to change the read clock of the frame memory to time-compress the video signal and simultaneously change the vertical output size and the vertical blank width, thereby providing two 4: 3 screens. The present invention provides a two-screen simultaneous viewing circuit in a wide television that enables simultaneous viewing without wider distortion on a wide television having a 16: 9 aspect ratio.

A feature of the two-screen simultaneous viewing circuit in a wide television according to the present invention for achieving the above object is a write clock locked to the synchronization signal after performing synchronization separation and color demodulation by tuning the frequency induced in the antenna. Main screen processing means for storing the color demodulated signal and the color difference signal demodulated in the frame memory and reading the normal and time compressed luminance and color difference signal from the frame memory by the read clock and read enable signal locked to the synchronization signal. And performing synchronization separation and color demodulation by tuning the frequency induced by the antenna, and storing the luminance and color difference signals, which are color demodulated by the write clock locked to the synchronization signal, in a frame memory and synchronizing the main screen processing means. Recall a normal, time-compressed luminance and color difference signal by a read clock and a read enable signal locked to A sub clock processing means for reading from a frame memory, a write locked to a synchronous signal output from the main screen processing means, and a plurality of read signals to oscillate, and the write clock and main screen processing means of the frame memory of the main screen processing means; A main oscillation means for providing the read clock of the frame memory of the sub picture processing means and a sub oscillation means for oscillating the write signal locked to the synchronous signal of the sub picture processing means and providing it to the frame memory of the sub picture processing means; Main / sub switching means for selectively outputting the output of the main screen processing means and the sub screen processing means by the main / sub switching signal, and the main screen processing means and the sub screen processing means by the synchronization signal of the main screen processing means. Lead-Enable Signals in Frame Memory, Main / Sub-Switching Scene And vertically by the control signal generating means for outputting the split screen on / off signal, the vertical and horizontal blank signals, and the split screen on signal output from the vertical, horizontal synchronous signal and the control signal generating means output from the main screen processing means. Deflection means for compressing the deflection size to a predetermined size, and converting the luminance and color difference signals outputted from the main / sub switching means into original color signals, and varying the vertical blank signal outputted from the control signal generating means, thereby predetermining the CRT screen. It consists of the matrix means which blanks and displays the upper part and the lower part of a.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a two-screen simultaneous viewing circuit in a wide television according to the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a two-screen simultaneous viewing circuit in a wide television according to the present invention.

100 is a main screen processing circuit, a tuner 101 which tunes a high frequency induced by an antenna, converts it into an intermediate frequency, and outputs a vertical and horizontal synchronous signal by separating a synchronization signal from an intermediate frequency output from the tuner 101. In the synchronous separation and color demodulation unit 102, which outputs (a, b) and performs color demodulation to output the luminance signal Y and the color difference signal RY, BY. Analog / Digital (hereinafter referred to as A / D) conversion unit 103 for converting the output color difference signal into a digital signal, and the output of the A / D conversion unit 104 by a write clock. And a frame memory 105 to be stored, and a D / A converter 105 for converting the digital signal read from the frame memory 105 into an analog signal by a read clock.

200 is a sub picture processing circuit, and is composed of a tuner 201, a sync separation and color demodulation unit 202, an A / D converter 203, a frame memory 204, and a D / A converter 205. It is the same as the configuration of the main screen processing circuit 100 described above.

In addition, 300 is a control signal generator, and the read enable signal E of the frame memories 104 and 204 is varied by the vertical and horizontal synchronization signals a and b output from the upper main screen processing circuit 100. The vertical blank signal c, the split screen on / off signal g, and the main / sub switching signal s are output.

400 is a deflection unit, which is vertically and horizontally deflected by the synchronization signals a and b and the split screen on / off signal g output from the synchronization separation and color demodulation unit 102 of the main screen processing circuit 100. Current is generated and provided to the deflection coil of the CRT.

In this case, when the split screen on / off signal g is on, the deflection unit 400 generates a compressed vertical deflection current to compress the vertical size to a predetermined size.

500 is a phase lock loop (hereinafter, referred to as a PLL) portion of the main screen processing circuit 100. The sync separation and color demodulation unit 102 of the main screen processing circuit 100 is output. By the oscillation, the write clock of the frame memory 104 of the main screen processing circuit 100 and the read clock of the frame memories 104 and 204 are oscillated and output, and 600 is a switching unit, and the plurality of outputs from the PLL unit 500 are performed. One read clock of the read clocks is provided to the frame memory 104 of the main screen processing circuit 100 and the frame memory 204 of the sub screen processing circuit 200.

700 is a PLL unit of the sub picture processing circuit 200. The frame memory of the sub picture processing circuit 200 is oscillated by the synchronization signal output from the synchronous separation and the color demodulation unit 202 of the sub picture processing circuit 200. Provide a write clock to 204.

800 is a main / sub switching unit, and the output of the main screen processing circuit 100 and the sub screen processing circuit 200 is selected by the main / sub switching signal s provided from the control signal generator 300. 900 is a matrix, and the luminance signal Y and the color difference signals RY and BY outputted from the switching unit 700 are converted into original color signals R, G, and B and displayed on the CRT. At this time, the matrix 900 blanks the upper and lower predetermined portions of the CRT screen by the vertical and horizontal blank signals c and d provided from the control signal generator 300.

FIG. 2A illustrates one embodiment of a read enable signal provided from the control signal generator 300 to the frame memory 104 of the main screen processing circuit 100. FIG. An example of a read enable signal provided from the control signal generator 300 to the frame memory 204 of the sub picture processing circuit 200 is illustrated. FIG. 2C illustrates the control signal generator 300. ) Shows an embodiment of a switching signal provided to the main / sub switching unit 700.

In the present invention configured as described above, the high frequency induced by the antenna of the main screen processing circuit 100 is tuned by the tuner 101 and output as a composite video signal to the synchronous separation and color demodulation unit 102 so that the vertical and horizontal synchronization signals (a b), the luminance signal Y, and the color difference signals RY and BY. The luminance signal Y and the color difference signals R-Y and B-Y are converted into 8-bit x 3 digital signals by the A / D converter 103 and input to the frame memory 104.

The vertical and horizontal synchronization signals a and b are provided to the PLL unit 500, and the PLL unit 500 oscillates a read / write clock locked to the vertical and horizontal synchronization signals so that the write clock is processed as the main screen. The read signal is provided to the frame memory 104 of the circuit 100 and the read clock is provided to the switching unit 600.

That is, the write clock is oscillated at 4fsc (fsc is 3.58MHz) and is provided to the frame memory 104. The read clock is oscillated at 4fsc for normal screen output and 8fsc for split screen output to the switching unit 800. Is provided.

In this case, the frame memory 104 of the main screen processing circuit 100 stores the output of the A / D converter 103 in accordance with the write clock W provided by the PLL unit 500.

If the switching signal indicates a normal screen output, the switching unit 600 selects a read clock of 4 fsc and outputs the read signals to the frame memories 104 and 204 of the main screen processing circuit 100 and the sub screen processing circuit 200, and divides them. When the screen output is displayed, a read clock of 8 fsc is selected and output to the frame memories 104 and 204.

Accordingly, the luminance and color difference signals stored in the frame memory 104 of the main screen processing circuit 100 may be provided by the read clock R provided by the switching unit 104 and the second control signal generating unit 300. According to the lead enable signal E as shown in FIG. (A), the input signal is input to the D / A converter 105, converted into an analog signal, and then input to the main / sub switching unit 800.

On the other hand, the PLL unit 700, which is locked and oscillated by the synchronization signal outputted from the synchronous separation and color demodulation unit 202 of the sub picture processing circuit 200, provides a write clock of 4 fsc to the frame memory 204 of the sub picture. The luminance Y and the color difference signals RY and BY output from the synchronous separation and color demodulator 202 are converted into 8-bit × 3 digital signals by the A / D converter 203, and then frame memory ( It is stored in the frame memory 204 in accordance with the write clock provided to the 204.

In addition, the luminance and color difference signals stored in the frame memory 204 may include the read enable signal provided in the read clock provided by the switching unit 600 and the control signal generator 300 as shown in FIG. E) is read and input to the D / A converter 205 to be converted into an analog signal and then input to the main / sub switching unit 800.

The output of the D / A converters 105 and 205 is selected by the switching signal s as shown in FIG. 2C provided from the control signal generator 300 to the main / sub switching unit 800. The luminance signal and the color difference signal are separated into the original color signal RGB and output to the CRT.

At this time, if the read clock provided by the switching unit 600 is 8fsc, and the vertical deflection current and the vertical blank signal are the same as those of the normal screen output as shown in FIGS. As shown in c), a screen distorted on the vertical axis is displayed. That is, a fat person or an object looks slim.

Therefore, in order to eliminate such screen distortion, the control signal generator 300 provides the divided screen on signal g to the deflection unit 400, and varies the vertical blank signal c to provide the matrix 900 to the matrix 900. . At this time, the deflection unit 400 changes the vertical deflection current as shown in FIG. 4 (a) by the split screen on signal g and provides it to the vertical deflection coil of the CRT to compress the vertical size as shown in FIG. 4 (c). In the matrix 900, the vertical blank signal is varied as shown in FIG. 4 (b), and the upper and lower predetermined portions of the CRT are blanked as shown in FIG. 4 (c). In this case, the hatched portion of FIG. 4 (c) is a portion that cannot be scanned.

Therefore, in the CRT, two 4: 3 screens without distortion as shown in FIG. 4 (c) are displayed on a wide television having an aspect ratio of 16: 9. In this case, the read enable signal E of the frame memories 104 and 204, the switching signal s of the main / sub switching unit 700, and the vertical and horizontal blank signals c and d of the frame memory 104 and 204 are connected to the main screen processing circuit 100. By the main vertical, horizontal synchronous signal of the control signal generator 300 is made.

As described above, according to the two-screen simultaneous viewing circuit in the wide television according to the present invention, a write clock whose main and sub screens are locked to the synchronous signal is used for the frame memory of the main screen and the sub screen, and the synchronous signal of the main screen. By using the clock locked on the main and sub screens as the read clock, the synchronization between the main and sub screens is matched, and the vertical deflection current and the vertical blank signal are varied when the split screen is output, thereby providing two 4: 3 screens without distortion. There is an effect of enabling simultaneous viewing on a wide television having an aspect ratio of 16: 9.

Claims (1)

A two-screen simultaneous viewing circuit in a wide television that simultaneously displays first and second video signals having an aspect ratio of 4: 3 on the left and right on a 16: 9 wide screen, wherein the first and second video signals are digitally converted. First and second analog-to-digital converters for outputting the control unit; First and second frame memories respectively storing first and second image signals digitally converted by the first and second analog-to-digital converters; The first and second video signals digitally converted by the first and second analog-to-digital converters are controlled to be recorded at a recording frequency when the first and second video signals are recorded in the first and second frame memories, respectively. A memory control unit for controlling reproduction at a frequency multiplied by a recording frequency; First and second digital-to-analog converters for analog-converting and outputting first and second video signals read out from the first and second frame memories; A main / sub switching unit which sequentially selects and outputs outputs of the first and second digital-to-analog converters; A compression unit for compressing the screen by a predetermined ratio in the vertical direction by changing the vertical deflection current according to the split screen on signal input by the user; And a matrix section for blanking the upper and lower sides of the screen by varying the vertical blanking signal in accordance with the split screen on signal input by the user.