JPH06319090A - Slave picture generator - Google Patents

Abstract

PURPOSE:To obtain a slave picture generator capable of generating a slave picture independently of either the horizontal deflecting frequency of a master picture or the input source of the slave picture. CONSTITUTION:This slave picture generator is provided with both a vertical filter circuit 11 for taking the weight mean of 1/4:1/2:1/4 of scanning lines of a slave picture displaying use video signal and letting the number of scanning lines be 1/3 and a frame memory 12 for storing the output of the circuit 11. The whole lines are read out from the memory 12 of a slave picture use video signal synchronously with a master picture video signal, and when the horizontal synchronizing frequency of the slave picture use video signal is almost twice the horizontal synchronizing frequency of the master picture use video signal, the contents of the memory 12 are thinned at every one line and the lines are read out synchronously with the master picture use video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a child screen generation device capable of generating a child screen in accordance with the input source of the parent screen and the child screen regardless of the horizontal deflection frequency of the parent screen and the input source of the child screen. It is about.

[0002]

2. Description of the Related Art FIG. 19 is a diagram showing a conventional sub-screen generator, in which 1 is an input terminal for a composite video signal and 2 is an input terminal.
Is a Y / C separation circuit, 3 is a color demodulation circuit, 8 is a multiplexer, 9 is an A / D converter, 10 is a horizontal filter circuit,
Reference numeral 11 is a 1/3 vertical filter circuit, 12 is a frame memory, 13 is a control signal generating circuit, 14 is a D / A converter, and 15 is a child screen output terminal.

Next, the operation will be described. The composite video signal input to the composite video signal input terminal 1 is separated into a luminance signal and a carrier color signal by the Y / C separation circuit 2, and the carrier color signal is demodulated into a color difference signal by the color demodulation circuit 3. The luminance signal and the color difference signal are multiplexed by the multiplexer 8 in the order of the luminance signal Y, the color difference signal R-Y, and the color difference signal B-Y, and converted by the A / D converter 9 into a digital signal. After that, the horizontal filter circuit 10 applies a filter so that the number of pixels in the horizontal direction becomes 1/3, and further 1/3.
The vertical filter circuit 11 filters the scanning lines to 1/3. This 1/3 vertical filter circuit 11
Output data is stored in the frame memory 12, is read at a clock locked to the sync signal of the parent screen source, is converted into an analog signal by the D / A converter 14, and is output to the child screen output terminal 15.

Input / output of the frame memory 12 is controlled by a signal generated by a control signal generating circuit 13. Further, in this conventional example, it is general that the color difference signals are thinned out so that the ratio of Y: RY-BY: BY is 4: 1: 1 before the multiplexer 8. Further, the horizontal filter circuit 10 is often a circuit that simply thins out the number of pixels in the horizontal direction to 1/3. Further, the 1/3 vertical filter circuit 11 simply thins out the number of scanning lines to 1/3, and there is one that limits the band so that the number of scanning lines becomes 1/3 in order to prevent aliasing (FIG. 20). , The sub-screen display video signal is sequentially multiplied by 1/4, 1/2, 1/4 coefficient,
One scan line out of three scan lines by adding the scan line multiplied by ¼, the scan line multiplied by the next ½, and the scan line further multiplied by ¼ Is generated.

[0005]

As described above, in the conventional sub-picture generation device, the horizontal deflection frequency of the target main picture and the sub-picture input source are only NTSC signals.
The 3 vertical filter circuit is a circuit that makes the scanning line ⅓, and when the horizontal deflection frequency of the parent screen is twice that of the NTSC signal, or in the case of high-definition, the child screen cannot be generated. Since the operation is guaranteed only by the clock of the NTSC signal, it is impossible to mount the conventional small screen generation device on a multi-scan television receiver.

The present invention has been made in order to solve the above-mentioned problems, and only by changing the number and combination of existing 1/3 vertical filter circuits and peripheral circuits such as memories,
An object of the present invention is to obtain a small screen generation device that generates a small screen regardless of the horizontal deflection frequency of the main screen and the source of the small screen and can be installed in a multi-scan television.

[0007]

SUMMARY OF THE INVENTION A small screen generator according to the present invention has a 1/4: 1 scanning line of a small screen display video signal.
/ 2: A vertical filter that takes a weighted average of 1/4 and reduces the number of scanning lines to 1/3, and a frame memory that stores the output of this 1/3 vertical filter are provided. All lines are read from the memory in synchronization with the main screen video signal, and when the horizontal sync frequency of the sub screen video signal is approximately twice the horizontal sync frequency of the main screen video signal, the line memory is used for each line. The line is read out in synchronism with the main screen video signal.

In addition, one of the scanning lines of the video signal for displaying the small screen is used.
/ 4: 1/2: 1/4 weighted average is taken and the number of scanning lines is 1 /
By providing a vertical filter to set to 3, a frame memory for storing the output of the 1/3 vertical filter, and a line memory for time axis compression and reading twice of the output of the frame memory, the main screen image This makes it possible to generate a sub-picture when the horizontal synchronizing frequency of the signal is almost twice as high as the picture signal for the sub-picture.

Further, one of the scanning lines of the video signal for displaying the small screen is used.
/ 4: 1/2: 1/4 weighted average is taken and the number of scanning lines is 1.
Vertical filter for ⅓ (1/3 vertical filter means 1)
And a line memory for delaying the sub-screen display video signal by one line in the preceding stage, and a weighted average of 1/4: 1/2: 1/4 of the scanning line of the sub-screen display video signal delayed by one line. Vertical filter that reduces the number of scanning lines to 1/3 (1 /
3 vertical filter means 2), 2 frame memory systems for storing the outputs of the 1/3 vertical filters of the 2 systems, 1 multiplexer system for alternately switching the output of this frame memory in the horizontal cycle, and the output of this multiplexer. By providing one line memory for time-axis compression, a sub-picture can be generated when the horizontal synchronizing frequency of the main-picture video signal is almost twice that of the sub-picture video signal. Also, the weight of the 1/3 vertical filter means 2 is set to 0:
1/2: A selector and four coefficient multipliers are provided to make the ratio 1/2.

Furthermore, by providing a 1/3 vertical filter 1 system, a frame memory 2 system for storing the output of the 1/3 vertical filter, and a multiplexer 1 system for switching the output of the frame memory,
This is to enable generation of a sub-screen when the horizontal synchronizing frequency of the main-screen video signal and the sub-screen video signal is almost twice that of the NTSC signal.

[0011]

According to the present invention, the sub-picture generating device changes the number and combination of the existing 1/3 vertical filter circuit and the peripheral circuits such as the memory by the above-mentioned means, so that the main picture signal and the sub-picture image signal can be obtained. It enables the generation of a child screen regardless of the horizontal synchronizing frequency of the signal.

[0012]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a television receiver including a child screen generator according to an embodiment of the present invention. In the figure, 31 is an antenna, 32 is a tuner, 33 is a parent screen selector, and 34 is Y. / C separation circuit, 35 is a color demodulation circuit, 36 is a parent screen RGB matrix circuit, 37 is a video multiplex circuit, and 38 is a CRT.
The SC signal is added. On the other hand, 4a to 4c are primary color RGB signal input terminals for a child screen, 5a to 5c are input terminals for a luminance signal Y and color difference signals RY (PR) and BY (PB), 6 is an RGB signal for Y, A matrix circuit for converting into RY and BY, 7 is a selector for a child screen, 8 is a multiplexer, 9 is an A / D converter, 10 is a horizontal filter circuit, 11 is a 1/3 vertical filter circuit, and 12 is a frame memory. , 13 is a control signal generation circuit, 14 is a D / A converter, 15 is a small screen output terminal, and 39 is a small screen RGB matrix circuit.

Next, the operation will be described. Antenna 31
The signal received from the tuner 32 and output from the tuner 32 and the signal from the external NTSC input terminal 40 are input to the parent screen selector 33, one of which is selected and input to the Y / C separation circuit 34. The Y / C separation circuit 34 performs Y / C separation and outputs a luminance signal Y and a color signal C. Luminance signal Y
Is input to the parent screen RGB matrix circuit 36, the color signal C is color demodulated by the color demodulation circuit 35, and color difference signals R-Y,
After being converted to BY, it is input to the parent screen RGB matrix circuit 36. RGB matrix circuit for parent screen 36
Then, the input luminance signal Y and color difference signals RY and BY are input.
Is converted and the primary color RGB signals are output to the video multiplexing circuit 37.

On the other hand, the RGB signals input from the primary color RGB input terminals 4a to 4c are converted into a luminance signal and a color difference signal by the matrix circuit 6, and the luminance and color difference signal input terminals 5a.
The signals are input to the sub-screen selector 7 together with the signals input from 5c. These signals are selected by the selector 7 according to the input mode, and the multiplexer 8 selects Y, RY, B-.
After being multiplexed in the order of Y, A / D converter 9
Is converted into a digital signal by. After that, the horizontal filter circuit 10 performs filtering so that the number of pixels in the horizontal direction becomes 1/3, or thinning is performed, and the result is input to the 1/3 vertical filter circuit 11. The data filtered in the vertical direction is stored in the frame memory 12 and is read by being controlled by the signal generated by the control signal generating circuit 13. The read data is converted into an analog signal by the D / A converter 14, converted into a primary color RGB signal by the sub-screen RGB matrix circuit 39, and input to the video multiplexing circuit 37. The video multiplexing circuit 37 superimposes the sub-screen video signal on the main-screen video signal and outputs it to the CRT 38.

In this embodiment, the horizontal deflection frequency of the parent screen is NTSC, and the source of the child screen is double speed NTSC.
In the case of a signal or a high-definition signal, the data is read from the frame memory 12 at the clock synchronized with the source of the parent screen, and the data is thinned out for each scanning line (FIG. 12). .

Example 2. FIG. 2 shows another embodiment of the present invention. In the figure, 16 is a 1/3 vertical filter circuit similar to 11, and 17 is a multiplexer. Since other configurations are the same as those in FIG. 1, the same reference numerals are given and description thereof is omitted. In this embodiment, the 1/3 vertical filter circuit 11 in the first embodiment is existing, and the operation is guaranteed only by the clock of the NTSC signal.
A 1/3 vertical filter circuit 16 is provided to compensate for the operating speed.
Is added, the filter circuits are operated in parallel, and output data is alternately switched by the multiplexer 17.

Embodiment 3. FIG. 3 shows another embodiment of the present invention. In the figure, 18 is a line memory, 19 is an adder, 20 is a coefficient unit that multiplies by 1/2, and other configurations are the same as in FIG. . In this embodiment, a line memory 18 is further added under the same conditions as in the first embodiment, and the output data from the 1/3 vertical filter circuit 11 is
The line memory 18 divides the line-delayed data into the current data, adds them by an adder, and then multiplies them by 1/2 to obtain an average value one after another, which is stored in the frame memory 12 and stored in the first embodiment. Similarly, it is read (FIG. 13).

Example 4. FIG. 4 shows still another embodiment, which is a combination of Embodiments 2 and 3, and is given the same reference numerals as those shown in FIGS. 2 and 3 and their description is omitted.
In this embodiment, since the 1/3 vertical filter circuit 11 in the third embodiment is existing and the operation is guaranteed only by the clock of the NTSC signal, the 1/3 vertical filter is added to compensate the operation speed. 16 is added, the filter circuits are operated in parallel, and output data is alternately switched by the multiplexer 17.

Example 5. FIG. 5 is a block diagram showing a main part of a television receiver including a slave screen generator according to another embodiment of the present invention, in which the horizontal deflection frequency of the master screen is NTS.
It is twice as high as C or high definition, and when the input source of the small screen is an NTSC signal. In the figure, 8 to 15 and 31 to 40 are the same as those in FIG. Reference numeral 41 is a sub-screen selector, 1 is a composite video signal input terminal, 2 is a sub-screen Y / C separation circuit, 3 is a sub-screen color demodulation circuit, and 21 is a line memory.

Next, the operation will be described. Antenna 31
The signal received from the tuner 32 and output from the tuner 32 and the signal from the external NTSC input terminal 40 are input to the parent screen selector 33, one of which is selected and input to the Y / C separation circuit 34. The Y / C separation circuit 34 performs Y / C separation and outputs a luminance signal Y and a color signal C. Luminance signal Y
Is input to the parent screen RGB matrix circuit 36, the color signal C is color demodulated by the color demodulation circuit 35, and color difference signals R-Y,
After being converted to BY, it is input to the parent screen RGB matrix circuit 36. RGB matrix circuit for parent screen 36
Then, the input luminance signal Y and color difference signals RY and BY are input.
Is converted and the primary color RGB signals are output to the video multiplexing circuit 37.

On the other hand, the signal output from the sub-screen selector 41 is Y / C separated by the sub-screen Y / C separation circuit 2,
It is converted into a luminance signal Y and a color signal C. The luminance signal Y is input to the multiplexer circuit 8, the color signal C is color-demodulated by the child screen demodulation circuit 3, converted into color difference signals RY and BY, and then input to the multiplexer 8. After being multiplexed in the order of Y, R-Y, and BY by the multiplexer 8, it is converted into a digital signal by the A / D converter 9. After that, the horizontal filter circuit 10 applies a filter such that the number of pixels in the horizontal direction becomes 1/3 or is thinned out, and the result is input to the 1/3 vertical filter circuit 11.
The vertically filtered data is stored in the frame memory 12 and is read by being controlled by a signal generated by the control signal generating circuit 13. The read data is read twice (FIG. 14) while being compressed on the time axis in the line memory 21, and a double-speed child screen signal is generated. This signal is converted back into an analog signal by the D / A converter 14, and the primary color RG is converted by the RGB matrix circuit 39 for the child screen.
It is converted into a B signal and input to the video multiplexing circuit 37. The video multiplexing circuit 37 superimposes the sub-screen video signal on the main-screen video signal and outputs it to the CRT 38.

Embodiment 6. FIG. 6 shows another embodiment of the present invention, in which 18 and 21 are line memories,
Reference numeral 19 is an adder, and 20 is a coefficient unit that multiplies by 1/2. In this embodiment, the line memory 2 is operated under the same conditions as in the fifth embodiment.
The data read once or twice is filtered again, and the average value of the data delayed by one line in the line memory 18 and the current data is taken one after another (FIG. 15).

Example 7. FIG. 7 shows another embodiment of the present invention, in which 18 and 21 are line memories,
16 is a 1/3 vertical filter circuit similar to 11, and 22 is 1
The same frame memory as 2 and 17 are multiplexers. In this embodiment, under the same conditions as in the sixth embodiment, a double speed sub-picture is generated by the filter method instead of the double reading method. The output data of the horizontal filter circuit 10 is 1/3.
A normal one which is input to the frame memory 12 through the vertical filter circuit 11, and a 1/3 vertical filter circuit 16 and a frame memory 2 which are delayed by one line in the line memory 18.
2 is input to the frame memories 12 and 22 and is read from each of the frame memories 12 and 22 at a clock for synchronizing with the main screen. After that, these data are sent to the multiplexer 17
Are alternately switched with (FIG. 16), and the time axis compression is performed in the line memory 21.

Example 8. FIG. 8 shows another embodiment of the present invention, in which 18 and 21 are line memories,
23, 24, 25 and 27 are 0, 1/2, 1 and 2, respectively.
Is a selector, 26 is a 1/3 vertical filter circuit similar to 11, 22 is a frame memory similar to 12, and 17 is a multiplexer. This example
The filtering method is changed under the same conditions as in the seventh embodiment. The output data of the horizontal filter circuit 10 is 1
Frame memory 12 through the / 3 vertical filter circuit 11.
Input to the normal memory, the line memory 18 delays by 1 line, and the coefficient of 0, 1/2, 1 is multiplied by coefficient units 23, 24, 25 respectively in a sequence of 3 lines, and then 1/3. The vertical filter circuit 16 and the one input to the frame memory 22 are branched to be read from the frame memories 12 and 22 at the clock for synchronizing with the parent screen. After that, the data read by the frame memory 22 is doubled by the coefficient unit 27, and these data are alternately switched by the multiplexer 17 (FIG. 17),
The line memory 21 is time-axis compressed.

Example 9. FIG. 9 shows another embodiment of the present invention. In the figure, 22 is a frame memory similar to 12, and 17 is a multiplexer. This example
The horizontal deflection frequency of the main screen and the input source of the sub screen are those for double-speed NTSC or HDTV.
The output data of the / 3 vertical filter circuit 11 is alternately written into the frame memories 12 and 22 for each line, and is read out at the clock for synchronizing with the parent screen. Thereafter, these data are alternately switched line by line by the multiplexer 17 (FIG. 18).

Example 10. FIG. 10 shows another embodiment of the present invention. In FIG.
3 is a vertical filter circuit, 22 is a frame memory similar to 12, and 17 is a multiplexer. This embodiment is a case where the 1/3 vertical filter circuit 11 of the ninth embodiment is existing and the operation is guaranteed only by the clock of the NTSC signal. In order to compensate the operation speed, 1
/ 3 vertical filter circuit 16 is added, the filter circuits are operated in parallel, and output data is alternately written to the frame memories 12 and 22 pixel by pixel.
Switch alternately with.

Embodiment 11. FIG. 11 shows another embodiment of the present invention, in which 18, 21, 28 are line memories, 23, 24, 25, 20, 27 are 0, 1/2, 1, 1/2, respectively. Coefficient multiplier for multiplying by 2, 26, 3
0 is a selector, 16 is a 1/3 vertical filter circuit similar to 11, 22 is a frame memory similar to 12, 17 and 29
Is a multiplexer and 19 is an adder. This embodiment is a collection of the vertical filter sections of the first to tenth embodiments, and the operation thereof is the same as that of the above embodiment, but the horizontal deflection frequency of the parent screen and the selector 2 for the child screen input source are used.
Select the required data at 6 and 30. This embodiment is compatible with multi-scan television.

[0028]

As described above, according to the present invention, it is possible to generate a sub-screen regardless of the horizontal deflection frequency of the main screen and the sub-screen input source, and it is possible to support a multi-scan television. A child screen generator can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a television receiver including a child screen generation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a child screen generation device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a child screen generation device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a child screen generation device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a main part of a television receiver including a child screen generation device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a child screen generation device according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a child screen generation device according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a child screen generation device according to an eighth embodiment of the present invention.

FIG. 9 is a block diagram showing a child screen generation device according to a ninth embodiment of the present invention.

FIG. 10 is a block diagram showing a child screen generation device according to a tenth embodiment of the present invention.

FIG. 11 is a block diagram showing a child screen generation device according to an eleventh embodiment of the present invention.

FIG. 12 is a diagram showing an algorithm of the vertical filter unit according to the first embodiment of the present invention.

FIG. 13 is a diagram showing an algorithm of a vertical filter unit according to the third embodiment of the present invention.

FIG. 14 is a diagram showing an algorithm of a vertical filter unit according to the fifth embodiment of the present invention.

FIG. 15 is a diagram showing an algorithm of a vertical filter unit according to the sixth embodiment of the present invention.

FIG. 16 is a diagram showing an algorithm of a vertical filter section according to the seventh embodiment of the present invention.

FIG. 17 is a diagram showing an algorithm of a vertical filter unit according to the eighth embodiment of the present invention.

FIG. 18 is a diagram showing an algorithm of the vertical filter unit according to the ninth embodiment of the present invention.

FIG. 19 is a block diagram showing a conventional small screen generation device.

FIG. 20 is a diagram showing an algorithm of a vertical filter unit of a conventional small screen generation device.

[Explanation of symbols]

 1 Composite video signal input terminal 2 Y / C separation circuit 3 color demodulation circuit 4a to 4c Primary color RGB input terminals 5a to 5c Luminance signal, color difference signal input terminal 6 Matrix circuit 7, 26, 30 Selector 8, 17, 29 Multiplexer 9 A / D converter 10 Horizontal filter circuit 11, 16 1/3 vertical filter circuit 12, 22 Frame memory 13 Control signal generation circuit 14 D / A converter 15 Sub-screen output terminal 18, 21, 28 Line memory 19 Adder 20, 23, 24, 25, 27 coefficient unit

Claims (11)

[Claims] 1. A 1 / th of a scanning line of a video signal for displaying a small screen
The weighted average of 4: 1/2: 1/4 is taken and the number of scanning lines is 1 /
A vertical filter to set to 3 and a frame memory that stores the output of the 1/3 vertical filter are provided, and all lines are read from the frame memory of the sub-screen video signal in synchronization with the main-screen video signal, When the horizontal synchronizing frequency of the video signal for the screen is approximately twice the horizontal synchronizing frequency of the video signal for the parent screen, the lines are read out in synchronization with the video signal for the parent screen by thinning out each line from the frame memory. A child screen generation device characterized by the above. 2. A 1/3 vertical filter system that operates with clocks whose phases are mutually inverted, and 1 / of these 2 systems.
3. The sub-screen generator according to claim 1, further comprising a multiplexer for switching and outputting the output of the three vertical filters in synchronization with the clock. 3. The output of the 1/3 vertical filter is 1/2: 1.
2. The child screen generation device according to claim 1, further comprising a vertical filter for extracting the weighted average of / 2. 4. The output of the multiplexer is 1/2: 1/2
3. The child screen generation device according to claim 2, further comprising a vertical filter for extracting the weighted average of the above. 5. A 1 / th of a scanning line of a video signal for displaying a small screen
The weighted average of 4: 1/2: 1/4 is taken and the number of scanning lines is 1/3.
By providing a vertical filter for storing the output of the 1/3 vertical filter, and a line memory for compressing the output of the frame memory and reading the output of the frame memory twice. A small screen generation device capable of generating a small screen when the horizontal synchronizing frequency of the above is approximately twice as high as the image signal for the small screen. 6. The sub-picture generation device according to claim 5, further comprising a vertical filter for extracting the output of the line memory by weighted average of 1/2: 1/2. 7. A 1 / th of a scanning line of a video signal for displaying a small screen
The weighted average of 4: 1/2: 1/4 is taken and the number of scanning lines is 1 /
Vertical filter for 3 (1/3 vertical filter means 1)
And a line memory for delaying the sub-screen display video signal by one line in the preceding stage, and a weighted average of 1/4: 1/2: 1/4 of the scanning line of the sub-screen display video signal delayed by one line. Vertical filter that reduces the number of scanning lines to 1/3 (1 /
3 vertical filter means 2), 2 frame memory systems for storing the outputs of the 1/3 vertical filters of the 2 systems, 1 multiplexer system for alternately switching the output of this frame memory in the horizontal cycle, and the output of this multiplexer. By providing one line memory system for time axis compression, it is possible to generate a small screen when the horizontal synchronizing frequency of the main screen video signal is almost twice that of the small screen video signal. Child screen generator. 8. The weight of the 1/3 vertical filter means 2 is set to 0:
8. The sub-screen generator according to claim 7, further comprising a selector and four coefficient multipliers for making 1/2: 1/2. 9. A 1/3 vertical filter system, and
The horizontal synchronizing frequency of the parent screen video signal and the child screen video signal is the NTSC signal by providing two frame memories for storing the output of the vertical filter and one multiplexer for switching the output of the frame memory. A small screen generation device capable of generating a small screen in the case of almost twice as much as the above. 10. Two-system 1/3 vertical filters operating with clocks whose phases are mutually inverted, two-system frame memories storing the outputs of these two-system 1/3 vertical filters, and these two systems. 10. The sub-picture generation device according to claim 9, further comprising a multiplexer for switching and outputting the output of the frame memory in accordance with the clock. 11. A plurality of systems of 1/3 vertical filters, a frame memory, a line memory, a coefficient unit, a multiplexer,
A sub-screen generation device comprising an adder and a selector, and by combining them, a sub-screen can be generated regardless of the horizontal synchronizing frequencies of the main-screen video signal and the sub-screen video signal.