JPWO2006018925A1 - Semiconductor integrated device and IC card and portable information terminal using the same - Google Patents

Abstract

Provided are a highly reliable semiconductor integrated device capable of detecting insufficient erasure and writing generated during updating of a nonvolatile memory, and an IC card and a portable information terminal using the same. A non-volatile memory 904 having a memory cell group 1001 divided into a plurality of blocks is provided, and a flag 1011 is added to the data string 1010 of the block, and each time a data string is erased, written, or erased / written. The flag is also erased, written, or erased / written. Two types of set constant currents are applied to the flag memory cell, and the flag determination unit 1007 determines whether the erasure, writing, or normality / abnormality of erasing / writing is performed using the voltage exhibited by the memory cell. The data in which the abnormality is detected is erased, written, or erased / written again, and normal data is obtained.

Description

  The present invention relates to a semiconductor integrated device suitable for application to an LSI (Large Scale Integrated circuit) used for an RFID (Radio Frequency IDentification), a non-contact IC (Integrated Circuit) card, etc., and more particularly to a semiconductor integrated device having a nonvolatile memory. The present invention relates to an apparatus, an IC card using the same, and a portable information terminal.

  In recent years, with the progress of semiconductor integrated circuit technology, RFID (mobile identification device) and non-contact IC cards configured by mounting IC or LSI pieces on a card together with an antenna are rapidly expanding the market. An RFID or a non-contact IC card exchanges data wirelessly with a reader / writer or an interrogator, but does not have a power supply by itself and receives power supply via an antenna. Since the power is cut off outside the communication area of the reader / writer, a nonvolatile memory is usually used for data recording.

  Due to the power supply situation as described above, the power supply may drop below the operating conditions of the chip during the rewriting process of the nonvolatile memory, or may be interrupted, and inconvenience such as loss of some data to be stored May happen.

  In order to prevent data loss due to power interruption or the like, information (flag) indicating one validity / invalidity is attached to one meaningful data set, and the information representing the validity / invalidity is attached. Patent Document 1 discloses an example of a non-volatile memory that determines validity / invalidity of a corresponding set of meaningful data.

  In addition, there is an example in which information indicating a processing state is added to each unit in a non-volatile memory that is divided in units of blocks, further divided into units, erased in units of blocks, and written in units of units. It is disclosed in Patent Document 2. In this example, since the processing content when the update processing is interrupted due to a failure during data update is stored, the interrupted update processing is continued by referring to the information indicating the processing content when returning. .

  Further, in Patent Document 3, a write-back process for setting the memory cell threshold voltage to a high value immediately after power-off is performed in order to prevent a memory cell from being in a depleted state when the flash memory being written / erased is turned off and causing a read failure. An example of a semiconductor memory device is disclosed.

  Further, in Patent Document 4, a memory card is provided with a terminal for detecting power interruption separately from the power terminal, and it is detected in advance that the card is pulled out, and the termination process is performed by itself before the power is completely shut off. An example of a semiconductor processing apparatus to perform is disclosed.

  Further, Patent Documents 3 and 4 describe that a power cut-off flag for storing the generation of power or an identification flag indicating that the block is in the middle of processing are provided.

JP 2001-249855 A JP 2002-318733 A JP 2004-118908 A JP 2004-295724 A

  First, the problem of a device to which power is supplied from the outside will be described using a non-contact IC card as an example. FIG. 14 shows a configuration example of a non-contact IC card. Generally, a non-contact IC card has a configuration in which an antenna coil 909 is connected to a non-contact IC card LSI 900. A non-contact IC card LSI 900 includes a CPU (Central Processing Unit) 901 for controlling and processing the entire LSI, a ROM (Read Only Memory) 902 for storing programs and static parameters, a dynamic work area. RAM (Random Access Memory) 903 used as storage, non-volatile memory 910 used for information storage / retention, cryptographic coprocessor 905 for speeding up cryptographic processing, tamper resistance (tamper resistance) improvement And a security circuit 906 that prevents malfunction of the chip, a power supply circuit 907 that supplies power to the entire chip, an RF (Radio Frequency) interface 908 that realizes non-contact communication and power reception, and the like.

  In addition, since a power source such as a primary battery or a secondary battery cannot be mounted on the non-contact IC card, the power source of the non-contact IC card is usually generated by rectifying the carrier signal received by the antenna coil 909. . Data is mounted on a carrier signal from a reader / writer (not shown), and the non-contact IC card modulates this carrier signal and transmits the data to the reader / writer.

  This will be described with reference to the drawings. In FIG. 15A, the magnetic flux 3 due to the electromagnetic wave radiated from the reader / writer (R / W) 2 passes through the non-contact IC card 4. At this time, the magnetic field intensity at the antenna 909 of the non-contact IC card 4 decreases according to the distance from the reader / writer 2 as shown in FIG. 15B. The rectified power supply voltage obtained by receiving the electromagnetic wave having the electric field strength decreases with distance as shown in FIG. 15C. Communication is possible at a distance where a power supply voltage equal to or higher than the lowest voltage at which the LSI 900 operates normally can be obtained. This range is shown as a communication area in FIG. 15C. As shown in FIG. 16, the signal transmitted by the electromagnetic wave consists of a carrier signal 5 (frequency is 13.56 MHz, for example), and the carrier signal 5 is subjected to, for example, ASK (Amplitude Shift Keying) modulation in the period 6 during which data is transmitted. An envelope 7 made of data is formed on the carrier signal 5.

  As described above, when the non-contact IC card is located outside the communication area of the reader / writer, the power is insufficient or absent. Therefore, in order to store information, it is essential to install a nonvolatile memory that does not require power for storage.

  In the case of a device equipped with a non-volatile memory, such as a non-contact IC card, a non-volatile memory rewriting process (an erasing process, a writing process, and an erasing / writing process in which data is erased once and then written) In the middle of the process, the power supply voltage drops below the operating condition of the chip or stops.

  In particular, when a non-contact IC card is used as a traffic ticket or an event ticket, the non-contact IC card is operated by being held by a person, and the system can manage the state of the LSI chip. It is impossible to detect the power shutdown as in Patent Documents 3 and 4 in advance, and it is not possible to process before the power is completely shut down. This is shown in FIG. A communication area 8 is formed by electromagnetic radiation of the reader / writer 2. When the non-contact IC card 4 moves like a locus 9 by manual operation, communication is possible between the point A that enters the communication area 8 and the point B that leaves the communication area 8, but when the manual operation is fast, During this time, rewriting of the nonvolatile memory may not be completed yet. Therefore, it is essential to deal with the above problems.

  As one of countermeasures, introduction of error detection codes and error detection / correction codes can be considered. However, since rewriting processing of a nonvolatile memory such as EEPROM requires several milliseconds, the above error detection code and error detection / correction code do not exhibit the effect as expected in consideration of changes over time. Can happen.

  As another countermeasure, a method of buffering information to be stored in two planes can be considered. In this method, a flag indicating the selection information of the two-surface buffer is added, and valid information is selected from the information stored in the two buffers according to the content of the flag indicating the selection information, and it is determined to be invalid. This is a method for rewriting new information in the buffer. This method has a feature that even if the flag indicating the selection information is accurate, it can always return to the information before the update even if the power supply is interrupted while the target information is being updated. The nonvolatile memories of Patent Documents 1 and 2 are examples of a storage device that employs such a two-surface buffer. However, there is a problem when the power supply is interrupted while the flag indicating the selection information is updated, and the flag indicating the selection information falls into an indefinite state.

  Here, the operation of the nonvolatile memory will be specifically described as a more detailed description.

  18A, 18B, and 18C show an example of operation of an EEPROM (Electrically Erasable and Programmable Read Only Memory) configured using a MONOS (Metal Oxide Nitride Oxide Semiconductor) memory cell which is one of nonvolatile memories. The memory cell includes a MOS (Metal Oxide Semiconductor) switch T1 and a MONOS memory T2.

  At the time of erasing shown in FIG. 18A, in the selected memory cell 1, 1.5V is applied to the gate Cg of the MOS switch T1, −8.5V is applied to the gate Mg of the MONOS memory T2, and 1.5V is applied to the source line S. The drain line D is set to HZ (open state in which no potential is applied), and the well (well) is set to 1.5V. In this state, holes are injected into the nitride film of the memory T2, that is, the nitride film of the memory cell 1 (parallel hatched portion in the figure), and the threshold voltage of the memory T2 (hereinafter referred to as “Vt”), that is, the threshold voltage of the memory cell 1 is 0V. Less than. This erased state is normally stored as information “1”.

  At the time of writing shown in FIG. 18B, in the memory cell 1, 1.5V is applied to the gate Cg of the switch T1, 1.5V is applied to the gate Mg of the memory T2, and −10.5V is applied to the source line S. D is set to HZ (open state in which no potential is applied), and the well Well is set to -10.5V. In this state, electrons are injected into the nitride film of the memory cell 1, and the Vt of the memory cell becomes 0V or more. This writing state is normally stored as information “0”. When writing, there is a case where writing is performed after erasing once, and this is called erasing / writing.

  At the time of reading shown in FIG. 18C, in the memory cell 1, the gate Mg of the memory T2 is set to 0V, 1.5V is applied to the gate Cg of the switch T1, and 1.0V is applied to the drain line D. Well Well is set to 0V.

  A state of Vt of the memory cell at the time of erasing and writing is shown in FIG. At the time of reading, as shown in FIG. 19, when the memory cell is in the erased state, a memory cell current (hereinafter referred to as “Ids”) flows and the voltage of the drain line D decreases. When the memory cell is in a writing state, Ids does not flow, and the voltage of the drain line D does not decrease. By detecting the decrease in the drain line D voltage due to this Ids, “1” and “0” of the read information are determined.

  By the way, the non-volatile memory has the property that Vt deteriorates with respect to the number of rewrites and the years of use. FIG. 20 shows the situation. That is, due to the deterioration, the Vt of the memory cell in the erased state moves from the negative voltage to 0V along with the storage time, and the Vt of the memory cell in the written state moves from the positive voltage in the 0V direction.

  Normally, when defining the maximum read operation speed (fmax) in which the erased state should not be read at a slower speed, the maximum read is considered in consideration of the decrease in Ids due to the deterioration of Vt in the erased state due to the number of rewrites and years of use. The operating speed is defined. For example, when guaranteeing 10 years, the example of FIG. 20 shows that the Ids in the erased state becomes 10 μA after 10 years and the maximum read operation speed becomes 10 MHz. As a matter of course, Ids immediately after erasure can be read out at several tens of μA and several tens of MHz.

  Similarly, the minimum read operation speed (fmin) that the write state should not be read at a higher speed is defined as well. When guaranteeing 10 years in the example of FIG. 20, the Ids in the write state becomes 1 μA after 10 years, and the minimum read operation speed is 1 MHz. As a matter of course, the Ids immediately after writing can be read at 1 μA or less and 1 MHz or less.

  Here, FIG. 21 shows Vt when erasing and writing are insufficient (when the voltage for erasing and writing is insufficient, or when the time for erasing and writing is insufficient). As can be seen from FIG. 21, the Vt of the insufficiently erased memory cell becomes higher than the Vt of the normally erased memory cell with the storage time, and the Vt of the insufficiently written memory cell is normal. The voltage is lower than Vt of the memory cell for which data is written. In the following description, a case where the memory cell is normally erased is referred to as an erasing process completion state, and a case where the memory cell is normally written is referred to as a writing process completion state.

  In the case of insufficient (that is, abnormal) erasing or writing, the read operation speed in the erased state becomes slow, and data cannot be read at the set maximum read operation speed. In addition, the read operation speed in the writing state is increased, and data cannot be read at the set minimum read operation speed. Depending on the degree of inadequate erasure and writing, the time when data cannot be read may be immediately after erasing or writing, or after several days or years.

  As described above, a non-contact IC card or an LSI in an RF tag is rectified by electromagnetic waves transmitted from an electromagnetic wave transmitter / receiver called a reader / writer or a reader, such as an RF tag as an example of a non-contact IC card or RFID. In the case of generating the power source of this, this insufficient erasure and writing may occur.

  In this case, depending on the distance between the reader / writer or reader and the non-contact IC card or RF tag, the LSI power supply in the non-contact IC card or RF tag may fluctuate or suddenly disappear, and the EEPROM power Insufficient erasure and writing are unavoidable due to fluctuations in erasing and writing voltages, or power interruption during erasing and writing.

  An object of the present invention is to provide a highly reliable semiconductor integrated device capable of detecting insufficient erasure and writing generated during rewriting of a nonvolatile memory, and an IC card and a portable information terminal using the same. There is.

  In order to achieve the above object, a semiconductor integrated device of the present invention is a semiconductor integrated device including a nonvolatile memory. The nonvolatile memory includes a memory cell group divided into a plurality of blocks, and a plurality of blocks. The first area in each of which the information is stored by the erase process, the write process, or the rewrite process by the erase / write process, and the state of the rewrite process provided in each of the plurality of blocks A second area in which a signal to be stored is stored by the rewrite process, and a determination circuit that inputs a signal read from the second area and determines whether the rewrite process in the block is normal or abnormal The signal is composed of at least one bit.

  The signal indicating the status of the rewriting process is a flag, and the normal / abnormal information generated by interruption of the power supply or the like is clarified by attaching the flag indicating the status of the rewriting process to the originally stored information. It becomes possible. Thereby, for example, information is rewritten again, and the reliability of the semiconductor integrated device is improved.

  According to the present invention, it is possible to detect insufficient erasure and writing that occurred during the update of the nonvolatile memory, so that it is expected to improve the reliability of the semiconductor integrated device equipped with the nonvolatile memory. Is done.

  Hereinafter, a semiconductor integrated device according to the present invention, an IC card using the same, and a portable information terminal will be described in more detail with reference to embodiments shown in the drawings. Note that in all the drawings for explaining the present embodiment, the same members or the same kinds of members are denoted by the same reference numerals, and the repeated description thereof is omitted.

  The semiconductor integrated device of this embodiment is equipped with a nonvolatile memory, and the nonvolatile memory is divided into a plurality of blocks.

  Each block includes a first area (data area) for storing information (data) and a second area (flag area) for storing a signal (flag: Flag) indicating the state of block rewrite processing. The erasing process, the writing process, or the erasing / writing process, that is, the rewriting process is performed in units of blocks. A block is a unit for erasing, writing, and erasing / writing to a nonvolatile memory, and is sometimes called a page. The data in the block is read out in units. A unit (Unit) is a minimum unit for reading and referring to data, and bytes and words are allocated. Blocks and units may be the same unit.

  Further, in the present specification, in the case of insufficient (abnormal) writing and erasing, electrons are not sufficiently injected into the memory cell or holes are not sufficiently injected. It means that the voltage is not higher than a predetermined value or the threshold voltage is not lower than a predetermined value.

  FIG. 1 shows an example of a block data format in which data stored in the data area is composed of a plurality of bits and a flag stored in the flag area is 1 bit. Flag (a) is placed after the data string. When insufficient erasure or writing occurs due to power interruption or the like, Vt of the memory cell of the 1-bit flag is Vt of normal erasure as shown in FIG. It becomes a voltage between Vt of normal writing.

  Here, assuming that the maximum read operation speed is 10 MHz and the erase Ids at that time is 10 μA, and the minimum read operation speed is 1 MHz and the write Ids at that time is 1 μA, a memory including a normally erased flag is included. The Ids of the cell is 10 μA or more, and the Ids of the memory cell including the flag that is normally written is 1 μA or less.

  That is, if the memory cell of the flag is normally erased or written, Ids ≧ 10 μA for erasure and 1 μA ≧ Ids for writing. By reading the bit of this flag at the maximum read operation speed and the minimum read operation speed, it can be determined that the rewrite data string has been normally erased or written.

  FIG. 2 shows a configuration example of a circuit that reads flag bits to determine whether erase or write is normal / abnormal. The circuit includes a current mirror circuit composed of two MOS transistors T3 and T4, a flag bit memory cell composed of an NMOS switch T1 and a MONOS memory T2, and a determination circuit 2. The current mirror circuit switches between 10 μA and 1 μA for output, and the output is connected to the drain line DL of the memory cell. The determination circuit 2 includes latch circuits (Latch) 3 and 4, an exclusive NOR circuit (EXNOR) 5 and an inverter 6. The determination circuit 2 inputs the voltage of the drain line DL and performs a determination operation based on the capture signals Tim 1 and Tim 2.

  A method for reading and determining flag bits using the circuit of FIG. 2 will be described below. First, when a constant current of 10 μA is supplied to the drain line DL of the flag bit memory cell and the memory cell is turned on, Ids ≧ 10 μA when normal erasing is performed, so the drain line DL of the flag bit memory cell is At the same time, the output of the inverter 6 becomes Vdd, and at the same time the take-in signal Tim1 is input, and the Q1 output of the latch circuit 3 is latched to Vdd.

  In the case of insufficient erasing or writing, or normal writing, Ids <10 μA, so that the drain line DL of the flag bit memory cell becomes the power supply voltage Vdd and the output of the inverter 6 becomes 0 V at the same time. The signal Tim1 is input, and the Q1 output of the latch circuit 3 is latched at 0V.

  Next, when a constant current of 1 μA is supplied to the drain line DL of the flag bit memory cell and the memory cell is turned on, Ids ≦ 1 μA when normal writing is performed, so the drain line DL of the flag bit memory cell Becomes the power supply voltage Vdd, the output of the inverter 6 becomes 0V, and at the same time the take-in signal Tim2 is inputted, and the Q2 output of the latch circuit 4 is latched at 0V.

  In the case of insufficient writing or erasing or normal erasing, Ids> 1 μA, the drain line DL of the flag bit memory cell becomes 0 V, the output of the inverter 6 becomes Vdd, and at the same time, the capture signal Tim2 is input, The Q2 output of the latch circuit 4 is latched to Vdd.

  In the above, the constant current source by the current mirror circuit is used so that the voltage of the drain line DL can take only one of the power supply voltage Vdd and 0V with respect to various Ids so that the determination can be made reliably. It is to make it.

  Here, when the flag bit is normally erased, the drain line DL of the flag bit memory cell becomes 0V in the first 10 μA determination, and the Q1 output of the latch circuit 3 becomes Vdd, and the flag bit also in the second 1 μA determination. The drain line DL of the memory cell is 0 V, the Q2 output of the latch circuit 4 is Vdd, and the flag read determination output of the exclusive NOR circuit 5 that is the output of the determination circuit 2 is the logical output “1” (Vdd). .

  When the flag bit is normally written, the drain bit DL of the flag bit memory cell is Vdd in the first 10 μA determination, and the Q1 output of the latch circuit 3 is 0 V. The flag bit is also in the second 1 μA determination. The drain line DL of the memory cell is Vdd, the Q2 output of the latch circuit 4 is 0 V, and the flag read determination output of the exclusive NOR circuit 5 is the logic output “1” (Vdd).

  Next, in the case of insufficient erasure, the memory cell current is 1 μA <Ids <10 μA, and in the first 10 μA determination, the drain line DL of the flag bit memory cell is Vdd, and the Q1 output of the latch circuit 3 is 0 V. In the 1 μA determination, the drain line DL of the flag bit memory cell is 0 V, the Q2 output of the latch circuit 4 is Vdd, and the flag read determination output of the exclusive NOR circuit 5 is the logic output “0” (0 V). .

  Even in the case of insufficient writing, the memory cell current is 1 μA <Ids <10 μA, and in the first 10 μA determination, the drain line DL of the flag bit memory cell is Vdd, and the Q1 output of the latch circuit 3 is 0 V. In the second 1 μA determination, the drain line DL of the flag bit memory cell is 0 V, the Q2 output of the latch circuit 4 is Vdd, and the flag read determination output of the exclusive NOR circuit 5 is the logical output “0” (0 V). It becomes.

  That is, when normal erasing or writing is performed, data inversion is not performed in the first and second flag bit reading, and the flag reading determination output of the exclusive NOR circuit 5 is the logic output “1” ( Vdd), and in the case of insufficient (that is, abnormal) erasing or writing, the data is inverted by the first and second flag bit reading, and the flag reading determination output of the exclusive NOR circuit 5 is logical The output becomes “0” (0 V).

  It is possible to determine whether the rewritten data string is normal or abnormal by detecting the data read twice from the flag bit. As described above, the flag area of the present embodiment is not an area for storing specific information such as the conventional power-off flag and identification flag, but is erased when a block is erased and written when a block is written. In other words, the state of rewriting processing is stored as a signal, and this is an area for determining whether normal or abnormal by reading twice with different currents. Here, the first flag bit read is determined to be 10 μA and the second read is determined to be 1 μA. Conversely, the first flag bit read may be determined to be 1 μA, and the second read may be determined to be 10 μA. .

  Further, although the determination is 10 μA and 1 μA, this value varies depending on the EEPROM specification or the system specification, and is not limited to 10 μA or 1 μA.

  Further, the flag bit is not limited to 1 bit, and it is possible to adopt a method of detecting whether erasing or writing is insufficient by using a plurality of bits. The data format in the case of 2 bits is shown in FIG.

  The flags a and b shown in FIG. 3 are erased or written together with the data. The flags a and b are erased at the same time when considering only the case of erasing. a and b are written simultaneously.

  From this point of view, it is meaningless to set the flag to 2 bits, but when erasure → write (erase / write) is performed, writing is performed after erasing together with data. Normally, when data is erased, all bits become information “1” and then written, and depending on the write data, the bits remain information “1” (erased state) or “0” (write It will be changed to the state.

  Here, writing but information “1” (erased state) is referred to as a write inhibit, and referring to the writing in FIG. 18B, the bias condition is 1.5 V at the gate Cg of the switch T1. By applying 1.5V to the gate Mg of the memory T2, setting the source line S to 1.5V, the drain line D to HZ (open state without applying potential), and the well Well to -10.5V. Then, a channel is formed in the memory cell, and the erased state is maintained by preventing the injection of electrons.

  The above-described flags a and b in the data format of FIG. 3 are written after being erased at the time of rewriting, but the flag a is to be written-in inhibit, and the information becomes “1” after the rewriting is completed. b is to be written, and the information becomes “0” after rewriting is completed.

  Here, assuming that normal writing is performed after insufficient erasure, the memory current of the flag a becomes 1 μA <Ids <10 μA, and the data is inverted when the flag bit is read twice. . However, the memory current of the flag b is Ids <1 μA, and it can be seen that the data is not inverted by reading twice and is normal. As a result, it can be seen that the erasure was insufficient and the writing was performed normally, and that the information “1”, which is the current erased state, was not written correctly.

  Next, when considering only the case of erasing, the flags a and b are simultaneously erased. When considering only the case of writing, the flags a and b are simultaneously written. Therefore, the state after erasing or writing is not changed by the flags a and b.

  However, in the case of continuous writing, the threshold voltage of the memory cell increases too much, and when erasing is performed next, the threshold voltage of the memory cell may not decrease to a predetermined threshold voltage. For this measure, there is a case where erasure is always performed before writing, and at this time, the 2-bit flag is valid as in the case of erasure → writing.

  In other words, when writing is performed in a continuous operation (erase → write, write → erase → write, etc.), it is possible to estimate at which stage writing failed in the state of the 2-bit flag.

  FIG. 4 shows an example of a nonvolatile memory in the semiconductor integrated device of this embodiment. The nonvolatile memory 904 includes a memory cell group 1001, a control unit 1002, a boost unit 1003, a buffer and block selection unit 1004, a flag generation unit 1005, a data input buffer 1006, a flag determination unit 1007, and a data output buffer 1008. The When the nonvolatile memory is an EEPROM, the memory cell group 1001 is divided into blocks. Each block includes a data area 1010 and a flag area 1011. The data area 1010 here is in byte units (= 8 bits) and is 1 to n bytes. n represents an integer.

  When the target block is rewritten, the target block must be erased by erasing the target block once. A block in the erased state can execute a writing process. Here, the combination of the erasing process and the writing process that are normally processed as a series of operations is represented as the erasing / writing process as described above.

  First, a case where information is updated in a target block will be described. The target information is temporarily stored in the data input buffer 1006 through the data input. The target block is selected by block designation information input to the buffer and block selection unit 1004 through address input. The block designation information is decoded by the buffer and block selection unit 1004, and the asserted block selection signal is output. This asserted block selection signal enables the block.

  The processing content for the selected block is determined by the control input. When the erasing / writing process is designated, the erasing process is performed as the first stage. At this time, a signal (flag) indicating the erasure process generated by the flag generation unit 1005 is stored in the flag area 1011. For example, when the erased state of the nonvolatile memory has a logical value “1”, a signal indicating the logical value “1” is generated by the flag generation unit 1005. As a second stage, information stored in the data input buffer 1006 is written into the data area 1010. At this time, the flag area 1011 stores a signal indicating the writing process generated by the flag generation unit 1005. At this time, a signal indicating a logical value “0” is generated by the flag generation unit 1005 as a signal exclusive of the contents of the flag at the time of erasure. In the first stage erase process and second stage write process, the data and flag of the target block are processed simultaneously.

  The flag area of each block of the non-volatile memory includes (1) when data is normally written in the data area, (2) when data area data is abnormally erased or written, and (3) data When the data in the area is normally erased, it can be said that the three states are stored in the hole injection amount of the memory cell, that is, the threshold voltage. Further, these three states are identified by flowing currents having two different current values to the drain line DL of the memory cell.

  Since the flag in the flag area is used to determine abnormal erasure and writing of data in the data area caused by fluctuations in the power supply voltage, the timing for writing the flag is preferably the same as or immediately after the data. In this case, “simultaneous” means that the operation is performed according to the same clock signal, and that a deviation of a signal delay is allowed.

  In the erasing process, the writing process, and the erasing / writing process, it is necessary to apply a high voltage of about 12 V to the memory cell, and the booster 1003 generates this high voltage and supplies it to the memory cell. The flag area 1011 must be rewritten and determined under conditions that are stricter than the conditions under which the data area 1010 becomes valid.

  All of these series of processes are controlled by the control unit 1002. Therefore, since an operation clock signal including the booster 1005 is required, the operation clock signal is input from the clock input. In the erasing process, the writing process, and the erasing / writing process, a signal indicating the operation is output from the control unit 1002 from the start of the process to the end of the process. The signal indicating that this operation is in progress may vary in output form depending on the purpose. For example, a level signal may be applied to output another different level during operation, or a pulse signal may be output at the end of processing. If it is not necessary, it may not be output.

  In some cases, an erasing process or a writing process is independently designated as a process for a selected block. When the erasing process is designated alone as the processing contents and the information of the target block is erased, the same process as the first stage erasing process is performed. When only the erasing process is performed, it is not necessary to store the target information in the data input buffer 1006. In this case, the flag is set to the logical value “1”.

  Usually, when information is written in an erased block, the erasing process is unnecessary. When the writing process is designated alone as the process for the selected block, the same process as the second-stage writing process is performed. It is necessary to store target information in the data input buffer 1006. In this case, the flag is set to a logical value “0”.

  Next, a case where information on a target block is read will be described. The target block is selected by block designation information input to the buffer and block selection unit 1004 through address input. The block designation information is decoded by the buffer and block selection unit 1004, and the asserted block selection signal is output. This asserted block selection signal enables the block. Output data from the selected block is once held in the data output buffer 1008 and then sequentially read.

  At this time, the flag of the target block is also read out, and its state is determined and output by the flag determination unit 1007 corresponding to the determination circuit 2 in FIG. As a result of the determination, the erasure process complete state (logical value “1”), the write process complete state (logical value “0”), and other states (values that are neither logical value “1” nor logical value “0”) Must be clearly expressed. If a state indicating a value that is neither a logical value “1” nor a logical value “0” is output, it indicates that the erasing process or the writing process performed prior to the reading is not completed. Become. Normally, in reading, unlike the erasing process and the writing process, it is not necessary to apply a high voltage of about 12 V to the memory cell. Therefore, the booster 1003 does not operate. The control unit 1002 controls all the series of processes. The information stored in the block is valid only when the target block is in the erase complete state or the write complete state.

  Next, detection flow of insufficient erasing / writing of non-volatile memory such as EEPROM that occurs when the power supply of LSI in IC card is cut off suddenly by non-contact IC card etc. Is shown in FIG. 5A.

  Usually, an EEPROM has an ECC (Error Checking and Correcting) area for a certain data string, and detects or corrects data corruption. In addition, by adding the flag bit according to the present invention, it is possible to detect insufficient erasing / writing as well as data destruction. The detection flow shown in FIG. 5A is intended for the case where ECC is added to the data string and flag bits are added. FIG. 5B shows an example of a data format stored in the EEPROM. Each block (Block) includes data (Data), ECC, and a flag (Flag). For example, the block X (Block X) includes data X (Data X), ECC X, and a flag X (Flag X). Flag A,..., Flag X, Flag Y,..., Flag α in this data format represents an area where the signal generated by the flag generation unit 1005 in FIG. 4 is arranged, and Data A,..., Data X, Data Y,..., Data α and ECC A,..., ECC X, ECC Y,..., ECC α represent areas where information output from the data input buffer 1006 in FIG.

  When the EEPROM is being erased / written (E / W is being executed) (S101), when the power is turned off and then powered on again (S102), reading of the EEPROM data string is started (S103). Here, the flow will be described below with a certain data string as the block X.

  Data X (Data X) and ECC X (ECC X) of block X are read (S104), and it is determined using ECC whether or not the data of block X is normal (S105).

  If it is determined that the data has been destroyed, it is notified to the host processing device or the like as data loss. Alternatively, the ECC is read again by reducing the reading speed to 1/2 or the like (S106), and the determination is made (S111). Here, it is necessary to try to restore the data as much as possible because it is possible that IC card users and issuers suffer a great deal of damage due to the loss of data (charges, privacy, etc.). The meaning of reading data and ECC by lowering the reading speed is that there is a possibility that insufficient erasure is performed, and there is a possibility that data can be read normally by reducing the reading speed. It is. That is, if insufficient erasure is performed, as described above, the Ids of the memory cell may become small and the reading speed may be slow. If it is determined in step S111 that the data is destroyed even if the reading speed is reduced, the host processor is notified of the data loss.

  If it is determined in step S105 or S111 that the data is OK, the flag bit is read to check whether the data is normally erased or written (S107).

If it is determined that the erase / write is insufficient and the result is NG, the read block X data and ECC are set in the data and ECC of the block X area as erase / write data (S108). Next, erase / write is executed (S109), and normal erase / write is performed. In order to confirm that normal erasure / writing has been performed, the process returns to step S104 and the subsequent steps are executed.

  Here, since the number of times of rewriting or the number of years of use may be exceeded and normal erasing / writing may not be performed due to deterioration of the memory cell, the number of retries in steps S107 → S108 → S109 → S104 is set in advance. It is desirable to keep it. If the retry count is exceeded, it is recognized that the block cannot be used.

  If it is determined in S107 that normal erasure / writing is performed, the next block is read (S110).

  In FIG. 5A, the flow for confirming the validity of the EEPROM read data when the power is turned on after the power supply is cut off during the erasing / writing of the EEPROM is shown. It is possible to confirm whether erasing / writing has been normally performed by reading. The flow of such confirmation will be described below with reference to FIG.

  A certain data string (here, block X) is erased / written (T101). In the erasing / writing, Data X, ECC X, and Flag X are simultaneously erased / written. After erasing / writing is completed, a flag bit (here, flag X) that is simultaneously erased / written in the block X is read (T102). If the flag bit is read and OK, the next block is erased / written (T103). If the flag bit is read and NG, the block X is erased / written again. When this flag bit is read and checked, ECC may be read and checked simultaneously.

  In this way, normal erasing / writing can be performed. However, since the number of times of rewriting or the number of years of use may be exceeded and normal erasing / writing may not be performed due to deterioration of the memory cell, the number of erasing / writing retries for the same block is set in advance. It is desirable. If the retry count is exceeded, it is recognized that the block cannot be used.

  The method for detecting an insufficient erase / write state of the nonvolatile memory (EEPROM), which is the central technology of the present invention, has been described above.

  Next, the semiconductor integrated device of this embodiment to which the above technique is applied will be described. FIG. 7 shows a configuration example of a non-contact IC card on which the semiconductor integrated device of this embodiment is mounted. The non-contact IC card has a configuration in which an antenna coil 909 is connected to the non-contact IC card LSI 900 which is the semiconductor integrated device of the present embodiment. The non-contact IC card LSI 900 is centered on a CPU 901 that controls and processes the entire LSI, a ROM 902 that stores programs and static parameters, a RAM 903 that is used as a dynamic work area, and information storage and retention. Non-volatile memory 904 used, cryptographic coprocessor 905 for speeding up cryptographic processing, security circuit 906 for improving tamper resistance and preventing chip malfunction, power supply circuit 907 for supplying power to the entire chip, non-contact It includes an RF interface 908 that realizes communication and power reception. The LSI 900 having such a configuration is formed on the same semiconductor substrate to form one chip. Then, by mounting the nonvolatile memory of the present invention shown in FIGS. 1 to 6 and FIGS. 8 to 10 described later on the nonvolatile memory 904, it is possible to improve the reliability of the non-contact IC card.

  Although the configuration of the nonvolatile memory of the present invention is shown in FIG. 4 described above, several block configurations described below can be adopted for the memory cell group 1001 in this configuration.

  FIG. 8 shows an example of the configuration of the block 1100 of the memory cell group 1001 of the nonvolatile memory according to the present invention. The memory cell group 1001 is divided into M blocks 1100 (0) to 1100 (m−1) and processed in units of blocks. The block 1100 has data 1101 stored in the data area 1010 and a flag 1102 indicating the state of the rewrite process stored in the flag area 1011. By providing the flag 1102, the reliability of data can be improved.

  FIG. 9 shows a configuration of another block 1200 of the memory cell group 1001 of the nonvolatile memory according to the present invention. In this example, an error due to a failure other than power interruption, such as a failure of the memory cell itself or a failure of the input / output buffer, is detected to further improve the reliability. Block 1200 includes data 1101 stored in data area 1010, error detection code 1201 for error detection of data 1101 also stored in data area 1010, and status of rewrite processing stored in flag area 1011 It has the flag 1102 showing. The error detection code 1201 is assigned a code that can detect errors in the data 1101 and the error detection code 1201 itself. Naturally, when the block 1200 is in the write completion state, the intended effect is exhibited. Although not complete, it is also possible to detect a write incomplete state.

  FIG. 10 shows a configuration of still another block 1300 of the memory cell group 1001 of the nonvolatile memory according to the present invention. This example further improves reliability by detecting errors due to failures other than power interruption, such as failure of the memory cell itself or failure of the input / output buffer, and correcting the error within the applicable range by itself. Is. Block 1300 is data 1101 stored in data area 1010, error detection / correction code 1301 for error detection / correction of data 1101 that is also stored in data area 1010, and flag area 1011. It has a flag 1102 indicating the state of the rewriting process. The error detection / correction code 1301 is assigned a code that can detect and correct errors in the data 1101 and the error detection / correction code 1301 itself. Naturally, when the block 1200 is in the write completion state, the intended effect is exhibited. Although not complete, it is possible to detect and detect an incomplete writing state.

  FIG. 11 shows a configuration of still another block 1400 of the memory cell group 1001 of the nonvolatile memory according to the present invention. In this case, the data 1101 stored in the data area 1010 of the block 1400 is divided into units, and the erasing process, the writing process, and the erasing / writing process are performed in units of blocks, and the reading is performed in units of units. It is. Although not specifically shown, such a configuration can also be applied to block 1200 of FIG. In this case, the error detection code 1201 is also divided into units. Further, it can be applied to the block 1300 of FIG. In this case, the error detection / correction code 1301 is also divided into units.

  As described above, the non-volatile memory according to the present invention described with reference to FIGS. 1 to 6 and FIGS. 8 to 10 is applied to the semiconductor integrated device (non-contact IC card LSI) mounted on the non-contact IC card shown in FIG. It is expected that the reliability of the non-contact IC card will be greatly improved by installing the memory. Further, the application of the nonvolatile memory of the present invention is not limited to a non-contact IC card, but can be applied to, for example, a contact / non-contact IC card, and the same effect can be obtained.

  FIG. 12 shows an example of a block configuration of a contact / non-contact IC card. In this configuration, the non-contact IC card shown in FIG. 7 is provided with a contact interface, and an antenna coil 1709 is connected to a contact / non-contact IC card LSI 1700. The contact / non-contact IC card LSI 1700 has a CPU 1701 for controlling and processing the entire LSI, a ROM 1702 for storing programs and static parameters, a RAM 1703 used as a dynamic work area, and an information storage / Non-volatile memory 1704 used for holding, cryptographic coprocessor 1705 for speeding up cryptographic processing, security circuit 1706 for improving tamper resistance and preventing chip malfunction, power supply circuit 1707 for supplying power to the entire chip, An RF interface 1708 that realizes non-contact communication and power consultation, a contact interface 1710 that realizes communication and power supply by contact, and a contact terminal 1711 are included.

  The nonvolatile memory 1704 employs a nonvolatile memory according to the present invention. As with non-contact IC cards, power supply means such as a primary battery or a two-time battery cannot be mounted on an IC card, so the power source of a contact / non-contact IC card is usually a non-contact IC during non-contact operation. It is extracted together with information from the carrier signal received from the card reader / writer, and is supplied directly from an IC card reader / writer (not shown) during the contact operation. During non-contact operation, there is no power when the card is located outside the communication area of the non-contact IC card reader / writer or when the power supply from the contact IC card reader / writer is cut off. End up. Therefore, in order to store information, it is essential to install a nonvolatile memory that does not require power for storage.

  Furthermore, the present invention can be applied to a portable information terminal such as a cellular phone equipped with the non-contact IC card or the contact / non-contact IC card, and similar effects can be obtained.

  FIG. 13 shows an example of a block configuration of a mobile phone equipped with a contact / non-contact IC card. A cellular phone 1600 includes an antenna 1601 for transmitting / receiving radio waves, an RF unit 1602 for performing wireless communication processing, a modem unit 1603 for modulating / demodulating communication signals, a codec unit 1604 for encoding / decoding information, and a microphone 1605, speaker 1606, nonvolatile memory 1607 for storing various parameters and information, battery 1608 for supplying power, key operation unit 1609 for instructing various operations, display unit 1610 for performing display, and IC card interface 1611 Consists of. A contact / non-contact IC card 1700 is connected via an IC card interface 1611. In addition, the RF unit 1602, the modem unit 1603, and the codec unit 1604 constitute a communication circuit 1612 for communicating with the outside through the antenna 1601.

  The IC card 1700 normally operates in accordance with a command from an external non-contact IC card reader / writer independently of the mobile phone during the non-contact operation. Further, during the contact operation, it operates according to a command from the mobile phone. For example, taking an electronic ticket as an example, the issuing process is performed by a contact operation via a mobile phone, and the use of the ticket is performed by a non-contact operation. Also in this case, when the battery of the mobile phone has run out during the issuance process, or when the IC card suddenly moves outside the communication area of the external non-contact IC card reader / writer when using the ticket In addition, a state in which there is no power occurs during processing. Also in this example, by using the nonvolatile memory of the present invention, the reliability of the mounted contact / non-contact IC card 1700 can be improved, and further the reliability of the mobile phone 1600 mounted with the same. Can be improved.

  As described above, the nonvolatile memory 1607 is also mounted on the mobile phone 1600 main body. If the nonvolatile memory of the present invention is adopted as the nonvolatile memory 1607, it becomes possible to improve the reliability of the cellular phone 1600 with respect to the power cut or the like generated when the battery runs out.

The figure for demonstrating the data format in embodiment of this invention. 1 is a circuit diagram for explaining an embodiment of a semiconductor integrated circuit according to the present invention. The figure for demonstrating another data format in embodiment of this invention. The block diagram for demonstrating an example of the non-volatile memory in embodiment of this invention. 5 is a flowchart for explaining detection of insufficient erasure / writing in the embodiment of the present invention. The figure for demonstrating the data format in the case of performing detection according to the flowchart shown to FIG. 5A. 6 is a flowchart for explaining erasing / writing performed using flag bits in the embodiment of the present invention. The block diagram for demonstrating the example of the non-contact combined use IC card which mounted the semiconductor integrated device of this invention. The block diagram for demonstrating the block example of the memory cell of the non-volatile memory in embodiment of this invention. The block diagram for demonstrating the other block example of the memory cell of the non-volatile memory in embodiment of this invention. The block diagram for demonstrating the further another block example of the memory cell of the non-volatile memory in embodiment of this invention. The block diagram for demonstrating the further another block example of the memory cell of the non-volatile memory in embodiment of this invention. The block diagram for demonstrating the example of the contact / non-contact IC card which mounted the semiconductor integrated device of this invention. The block diagram for demonstrating the example of the mobile telephone to which the contact / non-contact IC card which mounted the semiconductor integrated device of this invention is connected. The block diagram for demonstrating the example of the non-contact IC card carrying a non-volatile memory. The figure which shows the electromagnetic waves radiated | emitted from a reader / writer to a non-contact IC card. The curve figure which shows the magnetic field intensity of the electromagnetic wave in a non-contact IC card. The figure for demonstrating the communication area | region which can use a non-contact IC card. The figure which shows the example of the carrier signal by the electromagnetic waves radiated | emitted from a reader / writer. The figure for demonstrating the condition where a non-contact IC card moves across a communication area. The figure which shows the example of the operation bias at the time of erasure | elimination of a MONOS type EEPROM. The figure which shows the example of the operation bias at the time of the writing of a MONOS type EEPROM. The figure which shows the example of the operation bias at the time of reading of a MONOS type EEPROM. The curve diagram which shows the relationship between the threshold voltage Vt of a MONOS memory cell, and read-out electric current Ids. The figure which shows Vt degradation in the years of use of a memory cell. The figure for demonstrating the memory cell Vt when inadequate erasing and writing have occurred.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Selected memory cell, 2 ... Determination circuit, 3, 4 ... Latch circuit, 5 ... Exclusive OR circuit, 6 ... Inverter, 900 ... LSI for non-contact IC card, 901 ... CPU, 902 ... ROM, 903 ... RAM, 904, 1704 ... nonvolatile memory, 905 ... cryptographic coprocessor, 906 ... security circuit, 907 ... power supply circuit, 908 ... RF interface, 909 ... antenna coil, 1001 ... memory cell group, 1002 ... control unit, 1003 ... Booster, 1004 ... Buffer and block selector, 1005 ... Flag generator, 1006 ... Data input buffer, 1007 ... Flag determiner, 1008 ... Data output buffer, 1100 ... Block, 1010 ... Data area, 1011 ... Flag area, 1600: Mobile phone, 1700: Contact / non-contact IC card LSI.

Claims (13)

In a semiconductor integrated device including a nonvolatile memory,
The non-volatile memory is
A group of memory cells divided into a plurality of blocks;
A first area in each of the plurality of blocks, in which information is stored by erasure processing, writing processing, or rewriting processing by erasing / writing processing;
A second area provided in each of the plurality of blocks, in which the state of the rewrite process is stored as a signal by the rewrite process;
A determination circuit that inputs the signal read from the second area and determines whether the rewrite processing in the block is normal or abnormal.
A semiconductor integrated device, wherein the signal comprises at least one bit.   2. The semiconductor integrated device according to claim 1, wherein when the determination result of the determination circuit is abnormal, the rewriting process to the first and second regions is performed again.   2. The semiconductor integrated device according to claim 1, wherein the signal determined by the determination circuit is read under a stricter reading condition than the information stored in the first area.   2. The semiconductor integrated device according to claim 1, wherein the erase process completion state and the write process completion state indicated by the signal stored in the second area are mutually exclusive.   2. The semiconductor integrated device according to claim 1, wherein error detection information is included in the information stored in the first area.   2. The semiconductor integrated device according to claim 1, wherein the information stored in the first area includes error detection / error correction information.   2. The semiconductor integrated device according to claim 1, wherein the first area is divided into unit units, rewriting processing is performed in block units, and reading is performed in unit units.   When the above-mentioned signal is composed of 2 bits and an erasing / writing process is performed, one bit is in an erasing process completion state and the other bit is in a writing process completion state, which are mutually exclusive. The semiconductor integrated device according to claim 1. One of the first current at the maximum read operation speed and the second current at the minimum read operation speed is supplied to the memory cell that is the second area in which the signal is stored, and then the other Current of
2. The semiconductor integrated device according to claim 1, wherein the determination circuit determines normality / abnormality using two kinds of voltages exhibited by the memory cell by the first and second currents. An antenna,
Comprising a semiconductor integrated device connected to the antenna having at least a nonvolatile memory;
The non-volatile memory is
A group of memory cells divided into a plurality of blocks;
A first area in each of the plurality of blocks, in which information is stored by erasure processing, writing processing, or rewriting processing by erasing / writing processing;
A second area provided in each of the plurality of blocks, in which the state of the rewrite process is stored as a signal by the rewrite process;
A determination circuit that inputs the signal read from the second area and determines whether the rewrite processing in the block is normal or abnormal.
An IC card, wherein the signal comprises at least one bit.   11. The IC card according to claim 10, wherein the power supply voltage of the semiconductor integrated device is a non-contact type configured to be obtained by rectifying electromagnetic waves received by the antenna.   12. The IC card according to claim 11, wherein the IC card is of a contact / non-contact type further provided with a terminal for receiving power supply from outside. A first antenna;
A communication circuit for communicating with the outside via the first antenna;
An IC card interface connected to the communication circuit;
Comprising an IC card connected via the IC card interface,
The IC card
A second antenna;
A semiconductor integrated device connected to the second antenna and having at least a nonvolatile memory;
Comprising a power supply terminal and a data terminal for connection with the IC card interface,
The non-volatile memory is
A group of memory cells divided into a plurality of blocks;
A first area in each of the plurality of blocks, in which information is stored by erasure processing, writing processing, or rewriting processing by erasing / writing processing;
A second area provided in each of the plurality of blocks, in which the state of the rewrite process is stored as a signal by the rewrite process;
A determination circuit that inputs the signal read from the second area and determines whether the rewrite processing state in the block is normal or abnormal, and the signal includes at least one bit;
The IC card is configured such that a power supply voltage of the semiconductor integrated device is obtained by rectifying an electromagnetic wave received by the antenna, and is configured to receive power supply via the power supply terminal. A portable information terminal which is a contact type.

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