JPS6464469A - Compression and expansion processor - Google Patents

Compression and expansion processor

Info

Publication number
JPS6464469A
JPS6464469A JP62061976A JP6197687A JPS6464469A JP S6464469 A JPS6464469 A JP S6464469A JP 62061976 A JP62061976 A JP 62061976A JP 6197687 A JP6197687 A JP 6197687A JP S6464469 A JPS6464469 A JP S6464469A
Authority
JP
Japan
Prior art keywords
bus
mode
memory
compression
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62061976A
Other languages
Japanese (ja)
Other versions
JP2641858B2 (en
Inventor
Fumitaka Sato
Kyoji Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62061976A priority Critical patent/JP2641858B2/en
Publication of JPS6464469A publication Critical patent/JPS6464469A/en
Application granted granted Critical
Publication of JP2641858B2 publication Critical patent/JP2641858B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve a general purpose without losing a high speed by externally switching a mode through the two types of interfaces of a synchronous pipe line mode and an asynchronous DMA mode. CONSTITUTION:Before code data from a memory 21 is inputted to a compression and expansion processing circuit 1 connected to a reference line buffer memory 6 in a compression and extension processor, set up control data is supplied to the respective input/output interfaces of a system bus 28, an image bus 29 from a CPU 20. At the time of expanding, the contents of the memory 21 are processed in the processor 1 via the bus 28 and stored in an image memory 36. At the time of compressing, the data is inputted to the processor 1 through the bus 26 in the pipe line mode time and by the bus 29 through a DMA controller 22, a two way bus driver 24 or the like. Image data is similarly compressed and expanded to switch the mode without losing the high speed by using a hardware and improve the general purpose.
JP62061976A 1987-03-17 1987-03-17 Compression / expansion processor Expired - Lifetime JP2641858B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62061976A JP2641858B2 (en) 1987-03-17 1987-03-17 Compression / expansion processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62061976A JP2641858B2 (en) 1987-03-17 1987-03-17 Compression / expansion processor

Publications (2)

Publication Number Publication Date
JPS6464469A true JPS6464469A (en) 1989-03-10
JP2641858B2 JP2641858B2 (en) 1997-08-20

Family

ID=13186720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62061976A Expired - Lifetime JP2641858B2 (en) 1987-03-17 1987-03-17 Compression / expansion processor

Country Status (1)

Country Link
JP (1) JP2641858B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289577A (en) * 1992-06-04 1994-02-22 International Business Machines Incorporated Process-pipeline architecture for image/video processing
US5450599A (en) * 1992-06-04 1995-09-12 International Business Machines Corporation Sequential pipelined processing for the compression and decompression of image data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289577A (en) * 1992-06-04 1994-02-22 International Business Machines Incorporated Process-pipeline architecture for image/video processing
US5450599A (en) * 1992-06-04 1995-09-12 International Business Machines Corporation Sequential pipelined processing for the compression and decompression of image data

Also Published As

Publication number Publication date
JP2641858B2 (en) 1997-08-20

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