JPS6476251A - Data bus terminal equipment - Google Patents

Data bus terminal equipment

Info

Publication number
JPS6476251A
JPS6476251A JP23420787A JP23420787A JPS6476251A JP S6476251 A JPS6476251 A JP S6476251A JP 23420787 A JP23420787 A JP 23420787A JP 23420787 A JP23420787 A JP 23420787A JP S6476251 A JPS6476251 A JP S6476251A
Authority
JP
Japan
Prior art keywords
terminal equipment
address
control device
bus control
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23420787A
Other languages
Japanese (ja)
Inventor
Yoshio Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23420787A priority Critical patent/JPS6476251A/en
Publication of JPS6476251A publication Critical patent/JPS6476251A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate to fix a terminal equipment address and to dynamically set the address from a bus control device by sending the terminal equipment address from the bus control device as a command signal. CONSTITUTION:A terminal equipment address setting command signal, which is sent from the bus control device, enters a receiving circuit 7 from a data bus 1. The received command is recognized by a command recognizing circuit 13 and sent to an AND circuit 15 as the command signal. In case 18a that an address is set to the terminal equipment of a high order and in case that the output signal of an FF 16 is not significant, the load signal of a terminal equipment register is generated in the circuit 15 and the terminal equipment address is set. Simultaneously, a terminal equipment address set completing signal is set to the FF 16 and outputted to the terminal equipment of a low order. Accordingly, the terminal equipment address can be dynamically set from the bus control device.
JP23420787A 1987-09-18 1987-09-18 Data bus terminal equipment Pending JPS6476251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23420787A JPS6476251A (en) 1987-09-18 1987-09-18 Data bus terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23420787A JPS6476251A (en) 1987-09-18 1987-09-18 Data bus terminal equipment

Publications (1)

Publication Number Publication Date
JPS6476251A true JPS6476251A (en) 1989-03-22

Family

ID=16967372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23420787A Pending JPS6476251A (en) 1987-09-18 1987-09-18 Data bus terminal equipment

Country Status (1)

Country Link
JP (1) JPS6476251A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03225547A (en) * 1990-01-31 1991-10-04 Alpine Electron Inc Address setting method for terminal
JPH03269753A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd System address imparting system for terminal machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03225547A (en) * 1990-01-31 1991-10-04 Alpine Electron Inc Address setting method for terminal
JPH03269753A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd System address imparting system for terminal machine

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