JPS5572229A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5572229A
JPS5572229A JP14515378A JP14515378A JPS5572229A JP S5572229 A JPS5572229 A JP S5572229A JP 14515378 A JP14515378 A JP 14515378A JP 14515378 A JP14515378 A JP 14515378A JP S5572229 A JPS5572229 A JP S5572229A
Authority
JP
Japan
Prior art keywords
signal
cpu
memory
circuit
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14515378A
Other languages
Japanese (ja)
Inventor
Hideki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14515378A priority Critical patent/JPS5572229A/en
Publication of JPS5572229A publication Critical patent/JPS5572229A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable apparently each CPU system to operate nearly in independent mode, by attaining access to a common-use device through hardware by using a simply-constituted circuit.
CONSTITUTION: Common-use memory M is provided connecting to 1st and 2nd CPUs in common, X and Y addresses from which are inputted to X and Y decoders 1 and 2, whose outputs are supplied to exclusive acceptance circuit 3 to select either CPU, and addresses are led to timing control circuit 4. At the same time, an acceptance disability signal disabling an output signal from the other CPU is applied to circuit 4 and memory control signal XCONT or YCONT is accepted from selected CPU to supply memory M wih either one as control signal M-CONT in accordance with selective signal SELECT and control enable signal CONT-ENA, so that X or YDATA will be inputted to memory M by M-ADRS from multiplexer 5 through X and Y buffers.
COPYRIGHT: (C)1980,JPO&Japio
JP14515378A 1978-11-24 1978-11-24 Information processing system Pending JPS5572229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14515378A JPS5572229A (en) 1978-11-24 1978-11-24 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14515378A JPS5572229A (en) 1978-11-24 1978-11-24 Information processing system

Publications (1)

Publication Number Publication Date
JPS5572229A true JPS5572229A (en) 1980-05-30

Family

ID=15378639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14515378A Pending JPS5572229A (en) 1978-11-24 1978-11-24 Information processing system

Country Status (1)

Country Link
JP (1) JPS5572229A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262259A (en) * 1984-06-08 1985-12-25 Tokyo Electric Co Ltd Access control system for shared memory using plural microprocessors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262259A (en) * 1984-06-08 1985-12-25 Tokyo Electric Co Ltd Access control system for shared memory using plural microprocessors

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