JPS6444043A - Formation of multilayer interconnection structure - Google Patents
Formation of multilayer interconnection structureInfo
- Publication number
- JPS6444043A JPS6444043A JP20109387A JP20109387A JPS6444043A JP S6444043 A JPS6444043 A JP S6444043A JP 20109387 A JP20109387 A JP 20109387A JP 20109387 A JP20109387 A JP 20109387A JP S6444043 A JPS6444043 A JP S6444043A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- layer
- flattened
- interconnection structure
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To obtain a flattened multilayer interconnection structure by removing by etching second and third films under a condition that the second and the third films are equal in etching ratio. CONSTITUTION:In order to remove by etching back an interconnection material on an interlayer film 120 of a first interconnection material 103, it is coated with polystyrene as an etch-back sacrifice film 104. Then, a flattened wiring structure is obtained by etching back under the conditions of equal etching ratios of polystyrene of the film 104 and polysilicon of the material 103 by a dry etching method with SF6 and O2 as reaction gases. Then, a step of forming interconnections of second layer is executed, it is etched back similarly to the case of the first layer to obtain a flattened 2-layer interconnection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20109387A JPS6444043A (en) | 1987-08-11 | 1987-08-11 | Formation of multilayer interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20109387A JPS6444043A (en) | 1987-08-11 | 1987-08-11 | Formation of multilayer interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6444043A true JPS6444043A (en) | 1989-02-16 |
Family
ID=16435281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20109387A Pending JPS6444043A (en) | 1987-08-11 | 1987-08-11 | Formation of multilayer interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6444043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007520059A (en) * | 2003-12-22 | 2007-07-19 | ラム リサーチ コーポレーション | Substrate processing method, plasma chamber and semiconductor device |
-
1987
- 1987-08-11 JP JP20109387A patent/JPS6444043A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007520059A (en) * | 2003-12-22 | 2007-07-19 | ラム リサーチ コーポレーション | Substrate processing method, plasma chamber and semiconductor device |
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