JPS643428B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention generates a video signal for displaying characters such as a channel number and a time display on a display device such as a cathode ray tube (CRT), and also makes switching between these displays extremely efficient. The present invention relates to a large-scale integrated circuit for display that can be performed in a variety of ways.

In recent years, efforts have been made to add various functions to television receivers, and as mentioned above, television receivers with functions that can display channel numbers, time, etc. on specific parts of the screen are now available. It has come to fruition.

FIG. 1 is a diagram showing the state of the screen and its display principle when, for example, the time of 12:35 (12:35) is displayed. The time of 12:35 will be displayed on the screen.

In Figure 2, one dot is made up of two scanning lines and two oscillation output pulses ( _POSC ), and one character is displayed with 5 x 7 dots. This is a block diagram showing the circuit configuration of a conventional large-scale integrated circuit for CRT display capable of displaying Y rows. decimal counter 2, RS flip-flop 3, hexadecimal counter 4,
It consists of an X-base counter 5, a display data memory 6, an N-base counter 7, an RS flip-flop 8, a hexadecimal counter 9, a Y-base counter 10, a character generator (read-only memory) 11, an output circuit 12, and a NOR gate 13. There is. Note that 14 is a terminal to which a vertical synchronizing signal is applied, 15 is a terminal to which a horizontal synchronizing signal is applied, 16 is a terminal to which data is input, and 17 is a terminal to which a signal to the video circuit is output.

By the way, when the display illustrated in FIG. 1 is performed under control by a large-scale integrated circuit having such a circuit configuration, since one line has five characters, the X-adic counter 5 is constituted by a quinary counter. On the other hand, since the number of display lines is one, the Y-adic counter 10 is not necessary. Therefore, Y in the circuit shown in FIG.
The hexadecimal counter 10 is removed, and the overflow output terminal OVF of the hexadecimal counter 10 and the clear terminal CLR of the RS flip-flop 8 are directly connected.

The large-scale integrated circuit for CRT display having the configuration described above performs the following operations.

(1) Input data to be displayed on the television receiver from the terminal 16 to the display data memory 6.

(2) The n-ary counter 7, RS flip-flop 8, and hexadecimal counter are all cleared by the vertical synchronization signal indicating the start of one screen of the television receiver, and the output from the output terminal 17 to the video circuit is disabled. (disabled).

(3) When the horizontal synchronization signal is input after the vertical synchronization signal disappears, the n-ary counter 7 performs a counting operation, and when the horizontal synchronization signal is input n times, it overflows and sets the RS flip-flop 8. . By setting the RS flip-flop 8, a vertical display state is established.

(4) When horizontal synchronization signal is input, m-ary counter 2, RS flip-flop 3, hexadecimal counter 4
and all of the quinary counter 5 are cleared,
Initialization is performed regarding the horizontal display.
As a result, the display is rendered invalid. moreover,
Oscillation of the oscillation circuit section 1 also stops.

(5) When the horizontal synchronization signal disappears, the oscillation circuit section 1 starts oscillating and outputs a signal at a predetermined frequency.

(6) The output signal from the oscillation circuit section 1 is input to the m-ary counter 2, and the m-ary counter 2 overflows due to the arrival of m oscillation output pulses, and the RS
Flip-flop 3 is set. and,
When RS flip-flops 3 and 8 are set together, only those portions that are enabled in both the vertical and horizontal directions will be displayed.

FIG. 3 shows the output A of the character generator 11, the hexadecimal counter 4 and
3 is a diagram showing the relationship between hexadecimal counters 9. FIG.

(7) Read the data addressed by the quinary counter 5 and the contents of the character generator 11 addressed by the hexadecimal counter 4 and the hexadecimal counter 9, and send them to the output circuit 12 and the output terminal 17.
The signal is then output to the video circuit. That is, in the initial state, the quinary counter 5 is addressing the first data 1, and as shown in FIG.
The hexadecimal counter 9 addresses the most significant dot among the seven dots in the vertical direction, and the hexadecimal counter 4 addresses the leftmost dot among the five dots in the horizontal direction. Character generator 11 at this time
There is no character output in the output as shown by the dashed line.

(8) The hexadecimal counter 4 receives the oscillation output pulse from the oscillation circuit section 1, executes a counting operation, and obtains an output corresponding to the address from the character generator 11. In the example shown in FIG. 3, there is no output in the period 0 to 3, there is character output in the period 4 to 5, and there is no output in the period 6 to 9. Note that the period 10 to 11 corresponds to the interval between adjacent characters, and there is no output to the video circuit during this period, regardless of data.

(9) When the hexadecimal counter 4 overflows, 1 is added to the quinary counter 5, and 2 is addressed to display the next data in the numerical memory 6, 12:35. Thereafter, video signals are output in the same manner, and a display signal output of five characters corresponding to one scanning line is obtained. Then, when display signals for five characters are output, the quinary counter 5 overflows, the character generator is disabled, and there is no display signal at all.

(10) Next, when the horizontal synchronization signal is input, 1 is added to the hexadecimal counter 9, and the operations (5) to (9) described above are repeated, resulting in 5 characters corresponding to one next scanning line. Outputs a minute display signal. Thereafter, scanning is performed sequentially in the same manner, and the display ends when the hexadecimal counter 9 overflows.

FIG. 4 is a diagram showing the relationship between the CRT display described above, the scanning line, and the output of the character generator 11. As shown in FIG. 4a, the display (12:
35) is performed during the scanning period from the nth scanning line to the n+13th scanning line. Also, Fig. 4b shows the horizontal synchronizing signal (H _syoc ), and Fig. 4c shows the oscillation circuit section 1.
The output (OSC) signals of Fig. 4, d, e, and f are the nth
This is a timing chart showing the relationship with the output signal of the character generator 1 during the th, n+1, and n+2th scans, and as shown in the figure, the horizontal synchronization signal H _syoc
When the oscillation output disappears, the oscillation output is output from the oscillation circuit section 1, and at the time of the n-th and n+1-th scanning, the character generator 11 outputs character signals at the positions corresponding to the four characters 1, 2, 3, and 5. , In addition, in the (n+2)th position, a character signal is output at a position corresponding to the five characters of 12:35, and 12:35 is displayed as shown in FIG. 4a. In addition, Fig. 4b~
The display based on the output signal f is assumed to be a white display on the screen when the video circuit is at ground level. That is, in the circuit of FIG. 2, when the character signal generator 11 generates character signal outputs of high level "H" as shown in d, e, and f of FIG.
When the transistor that is a component of the output circuit 12 becomes conductive and the level of the terminal 17 becomes the ground level, the video circuit can be selectively brought to the ground level. By the way, when the output signal level of the character generator 11 is at a low level "L", the above-mentioned transistor is turned off and there is no effect on the video circuit, and the image being received is displayed. Further, while the character generator is in an invalid state, the character generator outputs the "L" level regardless of the address and operates so as not to affect the screen.

Figure 4g shows the vertical synchronization signal ( _Vsyoc ), h shows the horizontal synchronization signal ( _Hsyoc ), i shows the time relationship between the character signal output (CHAR), j shows the horizontal synchronization signal (Hsyoc), and k shows the horizontal synchronization signal ( _Hsyoc ). is a diagram showing the relationship between display and character signal output (CHAR), and V _syoc and H _syoc
The relationships other than these are as shown in FIGS. 4b and 4c.

A conventional large-scale integrated circuit for CRT display has the above-mentioned configuration and performs an operation of displaying the time and the like on the screen. By the way, such conventional
Although displays using large-scale integrated circuits for CRT displays were made in terms of time or channels, the number of characters that could be displayed was about 10 at most.
However, as television receivers and video tape recorders have rapidly become more sophisticated, it has become necessary to display a large number of characters, far exceeding the 10 or so characters mentioned above.

Figures 5a and 5b show examples of CRT displays for home video. FIG. 5a shows an example of inputting or confirming a program. The meaning of the screen is that in Program 1 (PROG1) out of many programs, it is Sunday (SUN).
Channel 10 at 10:45 (ON TIME10:45)
Started recording on the VTR at 11:30 (OFF)
This indicates that recording will end at TIME 11:30). Figure 5b is an example of displaying the contents of the tape counter of a VTR, and shows program 1 (PROG).
1) indicates that the tape is recorded in the area from 3000 to 5600 of the tape counter.

Although the two types of screens have been described above, in reality, several other types of displays are required, such as displaying the remaining amount of videotape and simply displaying time.

Next, a case will be described in which the screen shown in FIG. 5 is displayed using a conventional method. FIG. 6 shows an example of the configuration of the data memory 6 according to the conventional method.
By inputting data to the data input terminal 16, display data RAM is input from the RAM control circuit 18.
A write address, write data, and a write signal are generated to the display data RAM 19, and data corresponding to FIG. 5a is written into the display data RAM 19. The state at this time is shown in FIG. FIG. 7 also shows RAM addresses consisting of an X address X and a Y address Y. In Figure 7, the parts where letters such as “P” and “R” are written have their corresponding codes.
Additionally, other parts indicate that code for suppressing display is written in RAM.

Next, the data of the X-axis counter 5 and the Y-axis counter 10 are transferred from the data input terminals 20 and 21 to the display RAM.
19, the contents of the RAM are sequentially read out to the output line 22 according to the values, and a CRT display signal is generated via the character generator 11. However, in the conventional configuration example shown in FIG. 6, in order to display one screen, it is necessary to transfer a large amount of data corresponding to a total of 80 characters (16×5). Furthermore, as mentioned above, as equipment becomes more sophisticated, it becomes necessary to frequently switch between several types of screens. On the other hand, in order to produce equipment at low cost, it is essential that the above control be performed using, for example, a 4-bit, 1-chip microcomputer.

Considering this point of view, using the conventional method, in order to frequently switch the display screen, it is necessary to transfer a large amount of data, which reduces the processing speed or the number of program steps required. This causes great inconvenience.

The present invention was made with the intention of eliminating such inconveniences, and when displaying characters on a CRT, the types of screens to be displayed are limited to a few for certain applications such as VTR televisions and video discs. Furthermore, we focused on the fact that most of each screen consists of a common basic screen, and that display is achieved by placing variable and necessary information in a part of that basic screen. A memory in which data for one or more basic screens is written in a large-scale integrated circuit, and data addressed by this memory and related to the above variable information are stored.
CRT with built-in RAM to keep data transfer to the minimum necessary when changing the CRT display
The present invention aims to provide a large-scale integrated circuit for display purposes.

The present invention will be described in detail below with reference to the drawings. First, the basic screen will be explained using FIG. 8. Figure 5a is an example showing the state of the program, but the screen in Figure 8 shows the dotted line frame with diagonal lines, that is, the unchanging basic part excluding variable parts, based on data according to the program contents. This can be achieved by adding a variable part that changes the displayed content. At this time, the basic part data is total data 80
Of these, there are 66, and on the other hand, the number of variable parts that change depending on the program is 14, indicating that the basic part has an overwhelmingly large number of data.

FIG. 9 shows an example of the configuration of a data memory section according to the present invention. The display according to the present invention will be explained. First, data in the basic screen memory is prepared in advance, and will be explained using the example shown in FIG. In the figure, X and Y indicate the X address and Y address, and ~
corresponds to the variable part, and this part stores an address code that designates the address of the variable part memory where the data of the variable part is stored. 1~
The data indicated by 0 is the data to be displayed. Further, the basic screen memory may have only one screen, or several types of screens may be prepared, and one of them may be selected by the basic screen memory control circuit.

Next, the data of the variable part is transferred to the data input terminal 16.
This signal is stored in the variable section memory 26 via the RAM control circuit 18. At this time, the address where each data is stored corresponds to the position specified in advance when preparing the basic screen. With this kind of configuration, it is possible to specify a fixed location of the variable part based on the basic screen, especially for data that is used redundantly on several types of screens, so there is no need to have duplicate data in the variable part. RAM can be used very efficiently.

FIG. 11 shows an example of the contents of the variable section memory. A case will be described in which the data is displayed after preparation of the data in the variable memory as shown in the figure is completed. First, the basic screen memory 24 is designated by adding the X-base counter output and the Y-base counter output from the data input terminals 20 and 21. “PROG” is used between X address = 0 to 4 and Y address = 0.
〓” data is read from the basic screen memory 24. Since this is data and not a code specifying the variable section memory 26, the data switching control circuit 2
5 outputs this data as is to the output line 22.

Next, when the X address = 5 and the Y address = 0, the data is transferred from the basic screen memory 24 to the variable memory
A code specifying the address of is output. This code immediately specifies the address of the variable section memory 26, and the variable section memory 26 outputs data corresponding to the address content "1". On the other hand, the data switching control circuit 25 detects that the output of the basic screen memory 24 specifies the variable section memory 26 at this point, and sends the output of the variable section memory 26, that is, data "1" to the output line 22. Works to output.

Next, 1 is added to the X address, and the X address =
6. When the Y address becomes 0, data of "〓" (display suppression for one character) is output from the basic screen memory, so the data switching control circuit 25
The variable section memory 26 is switched to the basic screen memory 24, and the data "〓" is output to the output line 22.
The same operation is executed below, and the basic screen memory 24
Also, all data stored in the variable section memory 26 is output. That is, even by using the data memory 6 having the configuration shown in FIG. 9, the display shown in FIG. 5a can be obtained.

By the way, if you think about the data transfer necessary to perform the above display, in the conventional case
It used to be necessary to transfer 80 characters of data, but when the present invention is adopted, only the contents of the variable section memory 26, that is, 14 characters of data, need to be transferred, and the amount of data to be transferred is significantly reduced. There is.

Next, the basic screen memory 24 will be explained. The basic screen memory 24 can be composed of RAM or ROM. When using RAM, there is a method of writing data in the basic screen memory all at once when the power is turned on, and then using it as read-only memory.On the other hand, when using ROM,
The basic screen data required for each application can be written in advance. When implementing semiconductor integrated circuits, ROM memory occupies a fraction of the area of the semiconductor substrate compared to RAM memory, so for applications that require multiple basic screen memories, the basic screen memory can be replaced with ROM. If it is composed of
You can take full advantage of the benefits of ROM memory.

As is clear from the above explanation, the large-scale integrated circuit for CRT display of the present invention can keep the transfer of display data to the minimum necessary and can realize an extremely efficient CRT display.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the state of the screen and its display principle when a predetermined time is displayed, and Fig. 2 is a diagram showing the circuit configuration of a conventional large-scale integrated circuit for CRT display for displaying 5 characters. Fig. 3 is a diagram showing the relationship between the output of the character generator and the hexadecimal and hexadecimal counters when a display is made; Fig. 4 a to l are CRT displays;
A diagram showing the relationship among scanning lines, horizontal and vertical synchronizing signals, oscillation output, and character generator output; Figures 5a and b are diagrams showing display examples; Figure 6 is an example of the configuration of a data memory according to the conventional method. FIG. 7 is a diagram showing an example of display RAM data according to the conventional method, FIG. 8 is an explanatory diagram of the basic screen, FIG. 10
The figure shows an example of the contents of the basic screen memory, and FIG. 11 shows an example of the contents of the variable section memory. 11...Character generator, 12...External output circuit, 14...Vertical synchronization signal application terminal, 15...
...Horizontal synchronization signal application terminal, 16...Data input terminal, 17...Signal output terminal, 18...RAM control circuit, 19...RAM for display data, 20...X
Terminal to which the base counter output is applied, 21...Terminal to which the Y base counter output is applied, 22...Data memory section output line, 23...Basic screen memory control circuit, 24
... Basic screen memory, 25 ... Data switching control circuit, 26 ... Variable section memory.

Claims (1)

[Scope of Claims] 1. A first memory that stores display data consisting of basic screen data and display screen data input from a data input terminal via a first control circuit; a rewritable second memory that stores variable portion data input via a control circuit and is addressed by an address code output from the first memory; a data switching control section for switching output data, a data output line, and an addressing data input terminal for inputting addressing data of the first memory; Said second
When the output data is the address code of the second memory, the data switching control section selects the output data of the second memory, and when it is the remaining output data, the data switching control section selects the output data of the first memory.
1. A large-scale integrated circuit for display, characterized in that the output data of the memory is selected and the data is outputted to the data output line. 2. The large-scale integrated circuit for display according to claim 1, wherein the first memory is comprised of a read-only (ROM) memory.