JPH01248772A - Television receiver - Google Patents

Abstract

PURPOSE:To improve the display quality for channel display or the like by storing display signal from a smoothing circuit written into a memory by means of a memory control means in case of channel display. CONSTITUTION:A changeover switch 6 as a switching circuit outputting switchingly a video signal from an A/D conversion circuit 5 and a character font data from a smoothing circuit 11 based on a switching signal to a frame memory 2 and a control means 12 generating a switching signal corresponding to the output timing of the character font data from the smoothing circuit 11 and controlling write/readout of the output signal from the changeover switch 6 to/from the frame memory 2 are provided to the TV set. The memory control means 12 stores a display signal from the smoothing circuit 11 written into the memory 2 in case of channel display or the like. Thus, the brightness of the contour of the channel display is varied to attain smooth display and the display quality is improved.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a television receiver, and more particularly, the present invention relates to a television receiver that temporarily stores a video signal in a memory such as a field memory or a frame memory, and then reads it from the memory and displays it.
DTV, EDTV, l DTV.

It relates to so-called high-definition televisions such as digital TVs.

<Prior Art> Generally, channel display on a television receiver is performed by superimposing character font data from a built-in character generator on the display screen.

However, in the conventional channel display, since the capacity of the character generator is not sufficient, the display becomes mosaic-like, and the peripheral portions of the displayed characters have a jagged, step-like shape, resulting in poor display quality. For this reason, it is possible to increase the capacity of the character generator, but doing so just for channel display etc. has the disadvantage of high cost.

<Object of the Invention> The present invention has been made in view of the above points, and is characterized by improving the display quality of channel display and the like.

<Structure of the invention> The present invention relates to high-definition televisions, such as HDTVs.

Focusing on the fact that EDTV, IDTV, digital TV, etc. have field memory and frame memory,
In order to effectively utilize such memory to improve the display quality of channel display, etc., the following configuration is provided.

That is, in a television receiver capable of expressing a plurality of gradations by temporarily writing a video signal into a memory and reading it out from the memory for display, a display signal generating means for generating a display signal corresponding to a channel display, etc.; a smoothing circuit that converts the display signal into a multi-bit display signal corresponding to the gradation and smoothes the display by changing the brightness of the outline of the display such as the channel display; , a switching circuit that switches and outputs the video signal and the display signal from the smoothing circuit to the memory; and a switching circuit that generates the switching signal in accordance with the output timing of the display signal from the smoothing circuit; memory control means for controlling writing and reading of output signals from the memory into the memory, and the memory control means controls the display signal from the smoothing circuit written in the memory when displaying a channel or the like. It is maintained in the memory.

According to the above configuration, by changing the brightness of the outline of the display such as the channel display, the outline of the display such as the channel display becomes smooth.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and a television receiver l of this embodiment temporarily writes a video signal into a frame memory 2, reads it from the frame memory 2, and displays it. This is a so-called high-definition television that can express multiple gradations.

In FIG. 1, a video signal from a tuner 3 is subjected to predetermined processing such as synchronous separation and amplification in a video signal processing circuit 4, and then sent to an A/D conversion circuit 5 where it is converted into an n-bit digital signal. Once written into each memory 21 to 2n corresponding to each bit of the frame memory 2 via a changeover switch 6, which will be described later, the analog video signal is read out from the frame memory 2 and given to the D/A conversion circuit 7. It is further amplified by the video output circuit 8 and sent to the CRT 9.
is given and displayed.

Television receiver of this example! In order to improve the display quality of channel display, the following configuration is used.

That is, a display signal generating means 1O generates character font data of the name of the selected broadcasting station as a display signal corresponding to channel display, and a frame memory 20 converts the character font data into multi-bit characters corresponding to gradations. a smoothing circuit 11 that converts into font data and smooths the displayed characters by changing the brightness of the outline of the displayed characters in the channel display; and a video signal from the A/D conversion circuit 5 based on the switching signal. A changeover switch 6 as a changeover circuit that switches and outputs the character font data from the smoothing circuit 11 to the frame memory 2, and generates the switching signal corresponding to the output timing of the character font data from the smoothing circuit 2, The frame memory 2 includes memory control means 12 for controlling writing and reading of output signals from the changeover switch 6 into and from the frame memory 2.

The display signal generating means lO of this embodiment is an operating section! A channel selection control circuit 14 that controls the reading of character font data and tuning data in accordance with the channel selection operation in step 3, and a channel selection data memory I5 in which tuning data such as tuning data and character font data are written. The display signal generating means 10 reads the tuning data in response to the channel selection operation and supplies it to the channel selection control voltage generation circuit 16 in the same manner as in the past, and also displays the character font of the name of the selected broadcasting station. The data is read out and given to the smoothing circuit 11 and memory control means 12 as a display signal.

Generally, in conventional channel display, numbers corresponding to the broadcasting station are displayed, but in this embodiment, the name of the broadcasting station is displayed in letters, for example, r NHKJ.
In order to display such as r NTVJ r TBSJ, character font data of the broadcasting station name is stored in the channel selection data memory 15.

The smoothing circuit 11 is a display signal generating means! From 0! Bit character font data is converted to multi-bit character font data to reduce the brightness of the outline of the displayed character, as will be described later.

The memory control means 12 generates an address signal based on a clock generation circuit 17, a clock from the clock generation circuit 17, and a synchronization signal from the video signal processing circuit 4, and also generates control signals for writing and reading. The generated memory control circuit 18 and this memory control circuit 1
8 and the display signal generating means 10, a switching signal is sent to the changeover switch 6 and a frame memory 2
and a gate circuit 19 that generates a write control signal to.

Figure 2 is a signal waveform diagram of each part in Figure 1, and Figure 2 (
A) is a synchronization signal given from the video signal processing circuit 4 to the memory control circuit 18, and FIG. 2 CB) is a synchronization signal given to the memory control circuit 18.
is a write signal given to the gate circuit 19 from
A period in which this signal is at a high level indicates that writing to the frame memory 2 is in progress. FIG. 2(C) shows a signal given from the memory control circuit 18 to the channel selection control circuit 14, and a high level period indicates a channel display period. FIG. 2(D) shows the character font data given from the channel selection data memory 15 to the gate circuit 19 and smoothing circuit ll, and FIG. 2(E) shows the write control signal output from the gate circuit 19, which is at a low level. Writing to frame memory 2 becomes possible. FIG. 2(F) shows a write instruction signal given from the channel selection control circuit 14 to the gate circuit 19, which instructs writing of character font data into the frame memory 2 during a high level period. FIG. 2(G) is multi-bit character font data output from the smoothing circuit 11, and FIG. 2(H) is the gate circuit 19.
During the period when this switching signal is at high level, the video signal from the A/D conversion circuit 5 is output to the frame memory 2, and during the period when this switching signal is at low level, the video signal is output from the smoothing circuit 11. The character font data of is output to the frame memory 2. In addition, Fig. 2 (A) to (H
), each signal line in FIG. 1 corresponds to (A
) to (H) are attached.

The operation at the time of channel selection will be explained based on this FIG. 2 and the above-mentioned FIG. 1.

First, when the user operates the operation unit 13 to select a desired channel, the channel selection control circuit 14 of the display signal generation means IO stores tuning data and the name of the broadcasting station as channel selection data from the channel selection data memory 15. The character font data is read out, the tuning data is given to the tuning control voltage generation circuit 16 as in the past, and the character font data in FIG. 2(D) is read out from the memory control circuit 18.
C) is applied to the smoothing circuit 11 and the gate circuit 19 in response to the signal indicating the channel display period.

Furthermore, at the same time as outputting the character font data, the channel selection control circuit 14 supplies the write instruction signal shown in FIG. 2(F) to the gate circuit 19 to instruct it to write the character font data into the frame memory 2.

The 1-bit character font data is processed by the smoothing circuit 11.
The data is processed as described later and converted into multi-bit character font data as shown in FIG.

The gate circuit 19 receives the write signal of FIG.
Based on the character font data in FIG. 2(D) and the write instruction signal in FIG. 2(F), the write control signal in FIG. 2(E) and the switching signal in FIG. 2(H) are output. This gate circuit 19 outputs a low-level write control signal to permit writing to the frame memory 2 while the write instruction signal in FIG. 2(F) is at a high level, and also allows writing to the frame memory 2. ) to select a high-level switching signal according to the output timing of character font data.
As a result, the character font data is written to a predetermined address of the frame memory 2, and the video signal from the A/D conversion circuit 5 is written to other addresses.

Further, in order to prevent the character font data written in the frame memory 2 from being erased by writing the video signal, the gate circuit I9 controls the character font data corresponding to the character font data in the channel display period after the character font data writing period ends. As shown in FIG. 2(E), the write control signal is set to a high level to prohibit writing of video signals for only a period of time, thereby retaining the character font data written in the frame memory 2. There is.

Note that reading from the frame memory 2 is performed in the same manner as in the prior art.

Next, processing in the smoothing circuit 11 for smoothing the contours of displayed characters in channel display will be explained.

FIG. 3 is a diagram showing the character A processed by the smoothing circuit 11. The part surrounded by solid lines is the character font data, and the hatched part is the luminance data processed by the smoothing circuit 11. is the part cut in half. In this embodiment, the outline of the displayed character is made smooth by lowering the brightness of the outline of the displayed character.

FIG. 4 is a block diagram of the smoothing circuit II, and FIG. 5 is a diagram showing the positional relationship of display dots for explaining the smoothing operation.

The smoothing circuit 11 determines whether to perform smoothing processing on the three 3-bit first to third shift registers 20 to 22 and the data of each dot, that is, whether to halve the brightness or not. Conversion table 23 gives an output corresponding to
, an inverter 24 , an AND gate 25 , and an OR gate 26 .

This smoothing circuit 11 contains the character font data of the line to be displayed currently (line n in FIG. 5).
Character font data for the lines above and below (lines n-1, n+1 in FIG. 5) are provided from the channel selection data memory 15. The character font data for each line is given to each shift register 20-22, respectively. Also,
Each shift register 20 to 22 includes a clock generation circuit 1
A clock is applied from 7, and character font data is shifted three times in each shift register 2'0 to 22 in response to this clock.

In FIG. 5, "0" is the current display dot, and is the dot that is currently being focused on. Further, "2" is the dot that has just finished being displayed, and "4" is the dot that will be displayed next. Also, "r 8Jr lJr 5" is the display dot of the previous scanning line, and "7" r 3jr 6J is the display dot t of the next scanning line.

FIG. 4 shows a state in which the display dot rOJ in FIG. 5 is being processed, and each shift register 20
Each of the output lines .about.22 is shown with a number corresponding to the display dots 1-8 in FIG.

The conversion table 23 provides the inverter 24 and the OR gate 26 with an output corresponding to whether or not to process the dot based on the data of the dots surrounding the dot of interest. In this example, the dot "0" in Figure 5, which is the dot of interest, is determined to be processed or not based on the data of the surrounding dots, dots "1" to "4" in Figure 5. Determine as follows.

That is, the conversion table 23 has rlJ and r2 in FIG.
J, r2J and "3", "3" and "4" or "4" and "
When there is data in any one of the sets of dots 1", a high level output is output to the inverter 24 and the OR gate 26 in order to halve the brightness of the dot of interest, rOJ in FIG. Further, when there is no data in any of the four groups, a low level output is output to the inverter 24 and the OR gate 26 so that the data of rOJ in FIG. 5, which is the dot of interest, is output as is without being processed.

When the output of the conversion table 23 is at a low level, that is, when no processing is performed for the dot of interest "0", the outputs of the gates 25 and 26 corresponding to the gradation of the frame memory 2 are 1 to n. Regarding the bit, the data of the target dot "0" is output as is.

Furthermore, when the output of the conversion table 23 is at a high level, that is, when the luminance of the dot of interest "0" is halved, the output of the OR gate 26 (1=n-1 bit) is at a high level, and the Output of gate 25 (n
bit) becomes low level, which reduces the brightness by half.

The above smoothing process is performed for each dot of the character font data.

In this example, the data was processed based on the data of the dots "1" to "4" above, below, left and right of the dot of interest "0", but in addition, the data of the dots "5" to "8" in By considering this data, smoother display is possible.

In this way, the brightness of the outline of the displayed character is lowered and smoothed, thereby improving the display quality of the channel display. Furthermore, since the frame memory 2 is effectively used, there is no need to increase the capacity of the character generator.

Furthermore, in this embodiment, channels are displayed by broadcasting station names instead of numbers as in the conventional system, which matches the user's sensitivities and improves recognition.

Furthermore, in this embodiment, the broadcasting station name is displayed in alphabetical characters, but as another embodiment of the present invention, it may be displayed in kanji. This makes the channel selection operation easier.

Although the above-mentioned embodiment describes the channel display, the present invention is not limited to channel display, but can be applied to other screen displays such as volume display.

<Effects of the Invention> As described above, according to the present invention, smooth display is possible by changing the brightness of the outline of a display such as a channel display, so that display quality is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a diagram showing the display characters that have been smoothed, Figure 4 is a block diagram of the smoothing circuit, and Figure 5 is a display dot for explaining the operation of the smoothing process. It is a figure showing the positional relationship of. 2... Frame memory, 6... Changeover switch (switching circuit), IO... Display signal generation means, 11... Smoothing circuit, 12... Memory control means.

Claims (1)

[Claims] (1) In a television receiver capable of displaying multiple gradations by once writing a video signal into a memory and reading it out from the memory for display, display signal generating means generates a display signal corresponding to channel display, etc.; a smoothing circuit that converts the display signal into a multi-bit display signal corresponding to the gradation and smoothes the display by changing the brightness of the outline of the display such as the channel display; and based on the switching signal, a switching circuit that switches and outputs the video signal and the display signal from the smoothing circuit to the memory; and a switching circuit that generates the switching signal according to the output timing of the display signal from the smoothing circuit, and and memory control means for controlling writing and reading of output signals into and from the memory, and the memory control means controls the display signal from the smoothing circuit written in the memory when displaying a channel or the like. A television receiver characterized by being retained in memory.