JPS63994B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a teletext receiver that receives and displays teletext transmitted with information such as characters and graphics superimposed during the vertical blanking period of a television signal, and particularly relates to a teletext receiver that receives and displays teletext transmitted with information such as characters and graphics superimposed during the vertical blanking period of a television signal. This invention relates to a receiver that simplifies tuning adjustment.

Conventional general teletext receivers adjust channel tuning by visually checking the image on the normal TV screen, and then determining the best position for teletext reception when viewing the normal TV image. They considered it to be the best position and made adjustments. However, the best visual position differs depending on the adjuster, and the receivable range of TV images is quite wide, so
Even if the position is the best for viewing television images, it is not necessarily the best position for receiving teletext broadcasts. As has been the case in the past, adjusting the best tuning position for visually seen television images as the best position for teletext reception is unreliable and can cause receiver malfunctions, giving the user a sense of anxiety.

The present invention has been made in view of the above facts, and provides a teletext receiver that can accurately adjust teletext reception to the best tuning position using a simple adjustment method without making adjustments based on television images. It is something.

In particular, the present invention detects the reference start signal (framing code) of teletext broadcasting, displays its output by some method, and adjusts to the best tuning position using this display as a reference.

The present invention is particularly suitable when an EL (electroluminescence) display device or a liquid crystal display device is used as the display device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention shown in the drawings will be described below. FIG. 1 shows a block diagram of one embodiment of the present invention, in which an EL panel is used as a display device.

In FIG. 1, 1 is an antenna and 2 is a tuner. A television signal on which a character signal is superimposed is received by the antenna 1 and sent to the tuner 2. The tuner 2 performs high frequency amplification and frequency conversion as is well known, and inputs the signal to a video detection circuit 3 including a video intermediate frequency amplifier. The video intermediate frequency signal obtained from the tuner 2 is amplified and detected by the video detection circuit 3 to become a composite video signal, which is input to the sync separation circuit 4 and the waveform shaping circuit 5. The synchronization separation circuit 4 extracts a vertical synchronization signal S ₁ and a horizontal synchronization signal S ₂ from the input composite video signal and outputs them in order to synchronize each circuit and synchronize the EL panel display. 5 is a waveform shaping circuit, and the composite video signal input to this waveform shaping circuit 5 has an appropriate amplitude,
After phase compensation and the like, the signal is sliced at an appropriate level and waveform-shaped to a transistor-transistor logic (hereinafter referred to as TTL) level.
The TTL level signal containing a character signal output from the waveform shaping circuit 5 is input to a character data detection circuit 7 controlled by a multiple gate generation circuit 6. The multiplex gate generating circuit 6 outputs a pulse (hereinafter referred to as multiple H) of one horizontal scanning width (hereinafter referred to as 1H width) during the horizontal scanning period of a composite video signal on which character signals are multiplexed. The multiplexed gate generation circuit 6 is constituted by a counter and is reset by the vertical synchronizing signal _S1 inputted from the synchronization separation circuit 4, counts the horizontal synchronizing signal _S2 , and outputs multiplexed H when it matches the preset H. do. The multiple pulses are input to the character data detection circuit 7. This character data detection circuit 7 receives input from the waveform shaping circuit 5.
The TTL level signal is gated by the above multiple pulse and the TTL level signal is converted into a character signal (hereinafter referred to as
(denoted as character data) is detected.

Reference numeral 8 denotes a CR signal detection circuit which outputs a clock run-in signal (hereinafter referred to as CR signal) and a CR signal width signal (hereinafter referred to as CR sampling signal) which are synchronization signals for reproducing the bit clock. the above
The CR pulse and CR sampling signal are created by the signal output from the waveform shaping circuit 5 and the multiple H output from the multiple gate generation circuit 6. The above CR signal,
The CR sampling signal and the multiple H generate clock pulses in the write clock generating circuit 9 for writing character data into the S/R shift register 10 for serial-to-parallel conversion. The write clock generating circuit 9 is provided with a circuit for adjusting the phase of the character data clock. The character data is written into the shift register 10 by the write clock output from the write clock generating circuit 9, and converted into 8-bit parallel data. The 8-bit parallel data is input to an FC detection circuit (framing code detection circuit) 13, where frame synchronization is achieved, and at the same time an error bit check is also performed. The FC detection circuit 13 rises at the end of the framing code, which is a reference start signal for regenerating various codes, and multiplexes H
Outputs a signal that falls at the end (hereinafter referred to as the _PASS signal). The present invention uses this _PASS signal to detect television channel tuning, and the details will be described later.

The _PASS signal is sent to the clock control circuit 12 together with the write clock output from the write clock generation circuit 9.
Enter. The clock control circuit 12 gates the write clock with the _PASS signal and generates a clock for writing valid character data in units of a series of character broadcasts transmitted during one horizontal scanning period. The above-mentioned valid character data writing pulse is applied to the pattern memory 1 which will be described later.
1/8 after being input to the OR gate (not shown) of the clock control circuit 12 together with the display clock outputted from the display clock generation circuit 11 that generates the display clock used when reading data from the 4 etc.
The frequency is divided. The reason why the clock frequency is divided by 1/8 as described above is that data is processed in units of 8 bits, that is, 1 byte. Note that the display clock generating circuit 12 is phase-synchronized with the horizontal synchronizing signal.

Next, the character data converted into parallel data by the shift register 10 is written in byte units to a buffer memory (included in the pattern memory 14). Once data has been written to the buffer memory, subsequent data processing is
This is performed by a CPU (central control unit) 21. The character data written to the buffer memory is processed by the CPU.
21. The read character data is
The key input device 23 is decoded by the CPU 21 and
The character data is stored in the pattern memory 14 and color memory 15 only when it matches the program number specified by
Each is stored in memory. The data stored in the pattern memory 14 as described above is read out to the P-S shift register 24 by the display clock and subjected to parallel-to-serial conversion. The serially converted character data is sent to the EL drive signal mixing circuit 2.
5. On the other hand, the color data stored in the color memory 15 is not sent as color information to be displayed on a normal CRT display device, but is input to a color code conversion circuit 20 in order to extract only concealment or flashing data. The color data input to the color code conversion circuit 20 is converted into a flashing or concealing control signal.
The signal is input to the EL driving signal mixing circuit 25. The EL driving signal mixing circuit 25 outputs the pattern data sent from the P-S shift register 24 to the EL panel 26, and also outputs the pattern data sent from the P-S shift register 24 to the EL panel 26 using the flashing or concealing control signal sent from the color code conversion circuit 20. The pattern data displayed on 26 is displayed and controlled.

The above is an explanation of the configuration and operation of a teletext receiver that uses the EL panel 26 as a display device.The present invention uses the _PASS signal output from the FC detection circuit 13 described above to display That is, the first
Reception status display device 27 on the teletext receiver shown in the figure.
is attached, thereby allowing the FC detection circuit 13 to
It attempts to detect the tuning of a television channel by displaying that a _PASS signal has been output.

FIG. 2 is an example of a circuit that further embodies the reception status display device 27 for realizing the present invention, and by providing a display means as shown in FIG. That purpose can be achieved.

To explain this figure 2, the P _ASS signal has only about 1H period (1 horizontal scanning period), that is, 60 μS, as can be seen from the timing chart shown in Fig. 3, so the P _ASS signal is input directly to the transistor 29. Even if LED 30 is turned on, it is almost impossible to confirm that it is turned on. Therefore, it is necessary to extend the "ON" period of the signal input to the base of the transistor 29 so that the lighting of the LED can be confirmed. In this embodiment shown in FIG. 2, a monostable multivibrator 28 is used to extend the "ON" period of this signal, and the rise of the _PASS signal is deliberately extended to approximately 1V period (one vertical scanning period), or 16ms. (See Figure 4 3).
In this way, by extending the "ON" period of the signal input to the base of the transistor 29, the LED 3
The 0 light can be confirmed.

When adjusting the tuning of a television channel according to this embodiment, if teletext broadcasting is received at the best tuning position, the number of character signals superimposed on the television image should be adjusted at one or more points per 1V (one vertical scanning period). (depends on) Since the P _ASS signal is detected, LED 3 will turn on in 1/60 seconds.
0 lights up, so it appears to be completely lit. However, if the TV channel is not tuned to the best position for receiving teletext, the _PASS signal may not be detected, and the LED 30 may remain off for a long time. Become,
LED30 appears to be blinking. In this way, by checking the lighting status of the LED and adjusting the tuning of the television channel so that the LED is completely lit, it is possible to adjust the tuning of the television channel to the best position for teletext reception. In addition, the tuning range for normal TV images is wider than the best reception tuning range for teletext reception, so even if you adjust the tuning of the TV channel based on the teletext signal, the reception of normal TV images will not deteriorate; Both video and teletext can be adjusted to the maximum reception condition.

As is clear from the detailed description above, the present invention provides a conventional general teletext receiver with a simple display circuit means as shown in FIG. , can be easily adjusted to the best channel tuning condition. Furthermore, even if the best tuning position for both normal television reception and teletext reception is far apart due to the frequency characteristics of the tuner, according to the present invention, it is possible to adjust to the best tuning position for teletext reception. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the teletext receiver of the present invention, FIG. 2 is an example of a circuit of a reception status display device used in the embodiment, and FIGS. 3 and 4 are diagrams of the same embodiment. This is a timing chart for explaining operation. 13... EC detection circuit, 27... Reception status display device, 30... LED.

Claims (1)

[Claims] 1. In a teletext receiver that receives and displays character signals sent with information such as characters and graphics superimposed during the vertical blanking period of a television signal, a reference start signal is transmitted prior to the character signal data. and a means for displaying when the detected signal reaches the optimal reception state for teletext broadcasting, and the television channel can be tuned based on the display. Characteristic teletext receiver.