JPS639392A - Decoding device for high efficiency code - Google Patents

Abstract

PURPOSE:To prevent the occurrence of distortion in which a part of contour of a mobile body appears in the picture image of present block when shifted from a mobile block to a still block by executing a smoothening process only when the still block is continued. CONSTITUTION:A movement judging circuit 3 generates the judging code SJ of 1 bit that indicates the presence or absence of movement from the data of picture elements at the same position between areas of each frame of a three dimensional block. When still blocks are continued, the receiving side uses the data of mean value of data of the last area of prededing block and the leading area of present block in place of the data of next block positioned at the boundary of preceding block. In case of shifting from the area of preceding mobile block to the area of a mean value between frames, the smoothening process is not executed. Thereby, the distortion in which a part of contour of a mobile body in the image of preceding block appears in the image of present block can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency code decoding device that compresses the number of bits per pixel of image data such as a digital television signal.

[Summary of the invention]

This invention allows a television screen to be divided into a number of three-dimensional blocks, that is, n frames belonging to each of n temporally consecutive frames.
The pixel data in the block can be encoded with a compressed number of bits, and the pixel data in the block can be encoded with a compressed number of bits, and the pixel data in the block can be encoded with a compressed number of bits. It also forms transmission data with a reduced number of bits, and also determines the movement of an image within a block, and when there is no movement, a code signal regarding average value information of corresponding pixel data of n areas is generated. By performing so-called frame dropping, which transmits only the
This is a high-efficiency code decoding device that removes redundancy in the time direction.

In this invention, when the block is a stationary block and the temporally previous corresponding block is a stationary block, the average value of the data in the last area of the previous block and the data in the first area of the current block is By using this average value as the data for the first area of the current program,
Jerkiness in the restored image is reduced.

[Conventional technology]

Some known methods of encoding television signals include reducing the average number of bits per pixel or the sampling frequency in order to narrow the transmission band.

The applicant of the present application has proposed a high-efficiency encoding device that does not suffer from the problems of conventional techniques such as DPCM and subsampling, such as generation of aliasing distortion, error propagation, and generation of block distortion.

As described in Japanese Patent Application No. 59-266407, a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block is determined, and a code adapted to this dynamic range is created. A high-efficiency encoding device that performs this has been proposed.

Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed.

Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

The encoding method adapted to these dynamic ranges is
All pixel data within a block was always encoded, regardless of the movement of the block's image.

However, when there is no movement in the image,
As described in the '840 specification, the compression ratio can be further increased by so-called frame drop processing in which only pixel data of one area within a block is encoded.

When this frame drop processing is performed, an average value for each pixel of data in n areas within a block is formed, and this average value is transmitted. By transmitting the average value, the receiving side can effectively interpolate the area where transmission is omitted.

[Problem that the invention seeks to solve]

This invention uses an encoding method adapted to the dynamic range of the three-dimensional block described above, performs frame drop depending on the presence or absence of movement, and averages the corresponding pixel data of n areas within the block at the time of frame drop. The present invention relates to a high-efficiency code decoding device that transmits value information. On the receiving side, data in the (n-1) areas where frames have been dropped are interpolated with average value data. In this case, with simple replacement, there is a problem in that jerkiness, in which the movement of the image becomes unnatural, occurs when transitioning from the previous block in time to the current block.

Therefore, an object of the present invention is to provide a high-efficiency code decoding device that can reduce jerkiness in an image restored on the receiving side by smoothing processing.

Further, the present invention provides a high-efficiency code decoding device in which distortion in which a portion of the outline of a moving object appears to remain due to smoothing processing is prevented from occurring.

[Means for Solving the Problems] The present invention provides temporally continuous n of digital image signals.
Find the maximum value MAX of a plurality of pixel data and the minimum value MIN of a plurality of pixel data included in a block consisting of n regions belonging to each frame, and calculate the maximum value MA
Detecting the dynamic range DR for each block from
For blocks determined to have motion, the input data after minimum value removal within the detected dynamic range DR is encoded with a smaller number of quantization bits than the original number of quantization bits to generate a code signal and to detect motion. In a block determined to be absent, only a code signal related to average value information of corresponding pixel data in n regions is generated, and a code signal related to dynamic range information and at least two of the maximum value MAX and minimum value MTN is generated. In a high-efficiency code decoding device that transmits an additional code and a code signal obtained by encoding and a judgment code SJ indicating the presence or absence of movement, a still block indicated by the judgment code and a block that is temporally previous If the corresponding block of is a stationary block, n
This is a high-efficiency code decoding device characterized in that the average value of the data of the last area and the data of the first area of the previous block is generated as the data of the first area of each area.

[Effect]

Since the television signal has three-dimensional correlation in the horizontal direction, vertical direction, and time direction, the range of change in the level of pixel data included in the same block is small in the stationary portion. Therefore, even if the dynamic range of data PCI after removing the minimum level MIN shared by pixel data in a block is quantized using fewer quantization bits than the original number of quantization bits, almost no quantization distortion will occur. . By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one. Further, if the image of the block is a still image, only the code signal related to the average value of the corresponding pixels of the n areas constituting this block is transmitted. This drop-proofing process makes the compression ratio higher.

In a high-efficiency code decoding device that has such an advantage, when a block is a stationary block and the temporally previous corresponding block is a stationary block, (n-1) areas out of n areas are Replaced by the average value. When transitioning from the previous block to the current block, an average value is formed between the data in the last area of the previous block and the data in the first area of the current block, and this average value is the first area of the current block. will be replaced by the data of Therefore, since the image information of the previous block exists, jerkiness that occurs when changing blocks can be reduced. In addition, since smoothing processing is performed only when a stationary block continues, when moving from a moving block to a stationary block, part of the outline of a moving object in the previous block will be distorted as it appears in the image of the current block. Occurrence is prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description is given in the following order.

a, Configuration of transmitting side, Configuration of receiving side C, Block and blocking circuit d, Encoder e, Decoder f, Guinamino clean range detection circuit g, Variable length encoding, Motion determination circuit i, Jerkiness countermeasure j, Modification Example A, Structure of the Transmitting Side FIG. 1 shows the overall structure of the transmitting side (recording side in the case of a video tape recorder) of this embodiment. For example, a digital video signal (luminance signal) in which one sample is quantized to 8 bits is input to an input terminal indicated by 1. This digital video signal is sent to the blocking circuit 2.
supplied to

The blocking circuit 2 converts the input digital video signal into a signal in which blocks, which are units of encoding, are continuous in the time direction. The output signal of the blocking circuit 2 is supplied to the motion determining circuit 3. The motion determination circuit 3 generates a 1-bit determination code SJ indicating the presence or absence of motion from data of pixels at the same position between areas of each frame of a three-dimensional block (in this example, 6 lines x 6 pixels x 2 frames). This is the circuit where this occurs. The determination code SJ is at a high level for a stationary block with no movement, and the determination code SJ is at a low level for a block with movement.

The input digital video signal from the blocking circuit 2 is A
Supplied to ND gates 4 and 8. A determination code SJ is supplied as another input to the AND gate 4, and an inverted version of the determination code SJ is supplied as another input to the AND gate 8. One A N D gate 4 separates the pixel data of the still block, and this pixel data is supplied to the inter-frame average value forming circuit 5 . The inter-frame average value forming circuit 5 calculates the average values of 36 pixels located at the same position between two areas constituting a block, and replaces these 36 average values with the pixel data of the block. This is a circuit that outputs Therefore, the output signal of the inter-frame average value forming circuit 5 has a two-dimensional block configuration in which the average values are arranged in (6 lines x 6 pixels). The output signal of this inter-frame average value forming circuit 5 is supplied to a two-dimensional encoder 6.

The other AND gate 8 separates the image data of the block with image movement, and this pixel data is supplied to the three-dimensional encoder 9 .

The two-dimensional encoder 6 and the three-dimensional encoder 9 perform encoding with a variable number of bits adapted to the dynamic range of each block, as will be described later. These encoders 6.9 provide the block dynamic range DR, minimum level MIN, and 0 to 5 bit code signal DT.

The output signals of the two-dimensional encoder 6 and the three-dimensional encoder 9 are respectively supplied to a framing circuit 7.10. In this embodiment, the determination code SJ, code signal DT, dynamic range DR, and 31 small values MIN are transmitted. These data are processed by the framing circuit 7. At IO, it is converted into transmission data. The format of the transmitted data is judgment code SJ, dynamic range DR,!
It is possible to use a method in which each data portion consisting of the small-value M I N-code signal DT is encoded with an independent error correction code, and the parity of each error correction code is added for transmission. Further, each of the determination code SJ other than the code signal DT, the dynamic range DR, and the minimum value M I N may be encoded with an independent error correction code. Furthermore, the judgment code SJ, Guinamino Cleanse DR,! Small value MI
N may be encoded with a common error correction code and its parity may be added. The output signal of the framing circuit 7.10 is supplied to the OR gate 12, and the transmitted data is taken out at the output terminal 13 of the OR gate 12. Although not shown,
This transmission data is transmitted (or recorded on a recording medium) as serial data.

b. Configuration of the receiving side FIG. 2 shows the configuration of the receiving (or reproducing) side to which the present invention is applied. The received data from the input terminal 21 is supplied to the judgment code separation circuit 22, and the judgment code SJ is separated. Additionally, additional data and code signals other than the determination code SJ are supplied to the A N D gates 23 and 28 .

The judgment code SJ is supplied as the other input of the AND gate 23, and the inverted judgment code SJ is supplied as the other input of the AND gate 28.

The code signal and additional data of the average value information of the still block are separated by the AND gate 23, and this average value information is supplied to the frame decomposition circuit 24. Further, the code signal and additional data of the moving block separated by the AND gate 28 are supplied to the frame decomposition circuit 29. The frame decomposition circuits 24 and 29 generate the code signal D
T and additional codes DR and MIN are separated and error correction processing is performed. These code signals DT and additional codes are transmitted to a two-dimensional decoder 25 and a three-dimensional decoder 30.
are supplied respectively.

These decoders 25, 30 are connected to the encoder 6 on the transmitting side.
．． Perform the reverse process of step 9. That is, the data DTI after removing the 8-bit minimum level is restored as the representative level, and this data and the 8-bit minimum value MIN are added,
The original pixel data is restored.

The two-dimensional decoder 25 forms a decoded output of the protected area. The output signal of the two-dimensional decoder 25 is supplied to one input terminal a of the switch circuit 26 and to the average value forming circuit 27. The output signal of the average value forming circuit 27 is supplied to the other input terminal of the switch circuit 26. The output signal of the switch circuit 26 is supplied to the OR gate 31. The output signal of the three-dimensional decoder 30 is supplied to the OR gate 31, and the output signal of the OR gate 31 is supplied to the block decomposition circuit 35 and the delay circuit 34 (delay amount Td). The output signal of this delay circuit 34 is the average value forming circuit 2.
7.

A switch circuit 26 provided between the output signal of the two-dimensional decoder 25 and the OR gate 31. Average value forming circuit 27.
The delay amount 834 is provided to prevent jerkiness (unnatural movement) from occurring in the restored image. A signal for controlling the switch circuit 26 is generated by a control pulse generation circuit 33. The control pulse generation circuit 33 includes:
Judgment code SJ is supplied.

The block decomposition circuit 35 is a circuit for converting the decoded data in the order of the blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side. The original digital video signal is taken out at the output terminal 36 of the block decomposition circuit 35.

C. Blocks and Blocking Circuits Blocks, which are units of encoding, will be explained with reference to FIG. In this embodiment, two-dimensional areas An, An+1 to 3 belonging to each of two temporally consecutive frames are used.
A dimensional l block is constructed. In FIG. 3, solid lines indicate lines for odd fields, and broken lines indicate lines for even fields. Six pixels included in each of the six lines of each frame constitute areas An and An+1 of (6 lines x 6 pixels). Therefore, l block consists of (6×6×2=72) pixels.

FIG. 4 shows an example of the configuration of the above-described blocking circuit 2. A frame memory 15 is connected to the input terminal 14, pixel data of the current frame is supplied to the scan conversion circuit 16, and pixel data of the previous frame from the frame memory 15 is connected to the input terminal 14. The pixel data of the frame is supplied to the scan conversion circuit 17. The respective output signals of these scan conversion circuits 16 and 17 are supplied to a synthesis circuit 18 composed of a delay circuit and a switch circuit, and a digital video signal converted into the block order is generated at an output terminal 19 of the synthesis circuit 18. do.

For simplicity, when an image of l frame is divided into four, the previous frame is divided into Al, B1, as shown in FIG. 5A.
．． It is divided into CI and DI areas, and the current frame is A2.
．． B2. It is divided into areas C2 and D2. The scan conversion circuit 16 converts the order of data within one frame into the order of each block area, as shown in FIG. Similarly, the other scan conversion circuits 17 convert the order of data within one frame into the order of each area of the program, as shown in FIG. 5C.

At the output terminal 19 of the synthesis circuit 18, as shown in Figure 5, output data is obtained in which pixel data of four areas included in each of two consecutive frames are converted into block order.

d. Encoder Both the two-dimensional encoder 6 and the three-dimensional encoder 9 are
The two-dimensional encoder 6 and three-dimensional encoder 9, which respectively perform variable length encoding adapted to the dynamic range DR, have the same configuration except that the number of pixels included in one block is different.

FIG. 6 shows an example of an encoder that can be used as the three-dimensional encoder 9.

In FIG. 6, one block of pixel data PD is supplied to a dynamic range detection circuit 42, and the dynamic range DR and minimum diagonal MIN of the block are detected. In the subtraction circuit 41, the minimum value MIN is subtracted from each pixel data to form data PDI after minimum value removal. This data PDI and dynamic range D
R is supplied to a quantization circuit 43, and a code signal DT having a compressed number of bits is obtained from the quantization circuit 43. Dynamic range DR, minimum value M I N, code signal D
T is supplied to a framing circuit 10. In the framing circuit 10, the determination code SJ, the dynamic range D
R, the minimum value M I N , and the code signal DT are converted into serial data as shown in FIG.

The two-dimensional encoder 6 has the same configuration as the encoder shown in FIG. 6 described above, and is supplied with average value data from the inter-frame average value forming circuit 5 as input data.

The quantization circuit 43 is configured by, for example, a ROM.

This ROM contains pixel data PDI (8
A data conversion table for converting data (bits) into a compressed number of bits is stored. In the ROM, a data conversion table is selected depending on the dynamic range DRO size, and a 5-bit code signal DT is output as a readout output.
is taken out. The number of bits of the code signal DT changes in the range of 0 bits to 5 bits depending on the dynamic range DR. Therefore, the effective bit length in the code output from the ROM changes. Valid bits are selected in the framing circuit 7.10.

e. Decoder The two-dimensional decoder 25 and three-dimensional decoder 29 are circuits that perform the opposite process to that of the encoder 6.9.

FIG. 8 shows the configuration of an example of the two-dimensional decoder 25, and shows the dynamic range D from the frame decomposition circuit 24 in the previous stage.
R and code signal DT are supplied to a decoding circuit 44 .

The decoding circuit 44 is constituted by, for example, a ROM, and data at a restoration level corresponding to the average value data after minimum value removal is obtained from the decoding circuit 44 . This data is supplied to the adder circuit 45 and added to the minimum value MIN. Therefore,
As the output signal of the adder circuit 45, a signal at a restoration level corresponding to the average value data is obtained.

In the case of a static block, since drop-proof compression is performed, the output signal of the adder circuit 45 is written into the memory 46, and the average value data of the area where transmission is omitted is retrieved from the memory 46.

The three-dimensional decoder 30 has a similar configuration to the two-dimensional decoder 25. However, in the case of a block with movement, all the pixel data of each area is decoded, and there is no need to provide a memory.

f. Dynamic range detection circuit FIG. 9 shows a two-dimensional encoder 6 and a three-dimensional encoder 9.
In FIG. 9, which shows the configuration of an example of the dynamic range detecting circuit 42 provided in the 1st block, the input terminal indicated by 51 receives information from the blocking circuit 2 for each block to be coded. Image data is supplied sequentially. The pixel data from this input terminal 51 is sent to the selection circuit 52.
and is supplied to the selection circuit 53. One selection circuit 52 selects the pixel data of the input digital video signal and the latch 54.
output data, select the one with the higher level and output it. The other selection circuit 53 selects and outputs the one with a smaller level between the pixel data of the input digital video signal and the output data of the latch 55.

The output data of the selection circuit 52 is supplied to the subtraction circuit 56 and is taken into the latch 54. The output data of the 0 selection circuit 53 is supplied to the subtraction circuit 56 and the latch 58, and is taken into the latch 55. Latches 54 and 55
A launch pulse is supplied from the control section 59. The control unit 59 is supplied from a terminal 60 with timing signals such as a sampling clock and a synchronization signal that are synchronized with the input digital video signal. The control unit 59 has latches 54°55
And a latch pulse is supplied to the latches 57 and 58 at a predetermined timing.

At the beginning of each block, the contents of latches 54 and 55 are initialized. All the latches 54 are initialized with data of "0°," and the latches 55 are initialized with all data of "1." Among the sequentially supplied pixel data of the same block, the maximum level is stored in the latch 54. Further, among the pixel data of the same block that is sequentially supplied, the minimum level is stored in the latch 55.

When the maximum level and minimum level detection is completed for one block, the maximum level of the block appears at the output of the selection circuit 52. On the other hand, the minimum level of the block is generated at the output of the selection circuit 53.

When the detection for one block is completed, latches 54 and 55 are initialized again.

The dynamic range DR of each block is obtained from the output of the subtraction circuit 56 by subtracting the maximum level MAX from the selection circuit 52 and the minimum level MIN from the selection circuit 53. These dynamic range DR and minimum level MIN are controlled by the latch pulse from the control block 59.
They are latched by latches 57 and 58, respectively. The dynamic range DR of each block is obtained at the output terminal 61 of the latch 57, and the minimum value M I N of each block is obtained at the output terminal 62 of the latch 58.

g. Variable length encoding FIG. 10 is used to explain encoding of a variable number of bits adapted to the dynamic range performed by the above-mentioned quantization circuit 43. This encoding is a process of converting pixel data from which the minimum value has been removed to a representative level. The maximum allowable value of quantization distortion that occurs during this quantization (referred to as maximum distortion).

) is set to a predetermined value, for example 4.

FIG. 10A shows that the dynamic range DR is (maximum value MA
The case where the difference between X and the minimum value MIN) is 8 is shown. (DR=8
), the center level 4 is taken as the representative level LO, and (maximum distortion E=4).

That is, when (0≦DR≦8), the center level of the dynamic range is taken as the representative level, and there is no need to transmit quantized data. Therefore, the required bit length Nb is zero. On the receiving side, the minimum value M of the block
Decoding is performed from IN and dynamic range DR using representative level LO as a restoration value.

FIG. 10B shows the case where (DR=17), the representative levels are windowed as (LO=4) and (LL=13), respectively, and the maximum distortion E is 4. Since there are two representative levels LO and LL, (Nb=1).

In the case of (9≦DR≦17), (Nb=1),
The narrower the dynamic range DR, the smaller the maximum distortion E becomes.

FIG. 10C shows the case (DR=35), and the representative level is (LO=4) (L1=13) (L2=22) (L3
= 31) and (E = 4). Since there are four representative levels LO-L3, (Nb=2).

In the case of (18≦DR≦35), (N b = 2
) to be done.

In the case of (36≦DR≦71), eight representative levels (
LO to L7) are used. The 10th diagram is (DR=7
1), the representative level is (L O = 4) (L
L = 13) (L 2 = 22) (L 3 =
31) (L4=40) (L5=49) (L6=58) (
L7=67). 8 representative level LOs
-L7 is set as (Nb=3).

In the case of (72≦DR≦143), 16. representative levels (LO-LI5) are used. Figure 10E is (
DR=143), and the representative level is (L8=
76) (L9=85) (LI 0=94) (L11=1
03) (L12=112) (L13=121) (L14
= 130) (L15 = 139) (LO to L7 are the same as the above values). 16 representative levels (LO-
2 (Nb=4) to distinguish between LI5).

In the case of (144≦DR≦287), 32 representative levels (LO-L31) are used. Figure 10F is (
DR=287), and the representative level is (L16=
148) (L17=157) (118=166) (LL
9=175)...(L27=247)(L2
8=256)(L29=265)(L30=274)(
L31=283) (LO to L15 are the same values as above)
It is determined that In order to distinguish between the 32 representative levels (LO to L31), it is set as (Nb-5). Actually, since the input pixel data is quantized with 8 bits, the maximum value of the dynamic range DR is 255, and it is not typically quantized into bells (L28 to L31).

Television signals within one block are horizontal.

Since there is a two-dimensional correlation in the vertical direction and a three-dimensional correlation in the time direction, the level of pixel data included in the same block varies only small in the stationary portion. Therefore, the minimum level M shared by pixel data within a block
Even if the dynamic range of the data DTI after IN is quantized with a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs. transmission bandwidth can be made narrower than the original one.

h. Motion Determination Circuit FIG. 11 shows an example of the motion determination circuit 3. In FIG. 11, each of 71 and 72 is an area An+Anal belonging to two temporally consecutive frames of one block.
This is an input terminal to which image data of is supplied. This input data is formed by parallelizing the output data of the aforementioned blocking circuit 2 block by block. A terminal indicated by 73 is supplied with threshold data Tf, and a terminal indicated by 74 is supplied with a reset pulse PR.

The subtraction circuit 79 and the absolute value conversion circuit 75 calculate the level difference (
The absolute value of the frame difference) is formed.

The absolute value of this frame difference is compared with threshold data Tf by a comparison circuit 76. The 0 judgment circuit 77 supplies a binary comparison output corresponding to the level relationship between the absolute value of the frame difference and the threshold data Tf to the judgment circuit 77. When the absolute value of the frame difference is less than or equal to the threshold data Tf, it is determined that there is no change between the two, that is, it is a stationary portion. The determination circuit 77 is supplied with a reset pulse PR for each block. A 1-bit output from the determination circuit 77 is taken out to an output terminal 78 as a determination code SJ.

(SJ=1), areas An and A within the block
Since the images of nal are almost the same, the average value of both (A
Only n+An+1)/2 is encoded by the two-dimensional encoder 6. Therefore, one area out of the two areas is protected against dropping. In the case of (SJ=0), 2
Pixel data included in both areas An and An+1 are encoded by the three-dimensional encoder 9.

As described above, by determining whether each block is a stationary portion, it is possible to reduce the transmission of code signals regarding the stationary portion, which occupies a large proportion of the image, and to significantly increase the data compression rate.

It should be noted that other configurations may be used as the motion determination circuit 3, such as one that determines whether the value obtained by accumulating the absolute value of the frame difference between two frames for one block is less than or equal to a threshold value.

i. Countermeasures against jerkiness FIG. 12 shows an example of encoding and decoding operations in this embodiment. As shown in FIG. 5, one area AI, A2 when one frame is divided into four
．． A3. Focus only on A4... AI and A2 are areas covered by two temporally consecutive frames, and both constitute one block. Similarly, each pair of A3 and A4 and A5 and A6 constitute a block.

When the block made up of areas Al and A2 is a motion block, all of the pixel data included in these areas Al and A2 is encoded in a three-dimensional encoder 9 in a way that adapts to the dynamic range. When the block consisting of areas A3 and A4 is a stationary block, the interframe average value (A3+A4)/
2 is encoded in a two-dimensional encoder 6 in a way that adapts to the dynamic range. Similarly, if the block consisting of areas A5 and A6 is a stationary block, the interframe average value (A5+A6
)/2 is a two-dimensional encoder, and the encoder 6 performs encoding adapted to the dynamic range. Therefore, for a stationary block, the pixel data of two regions is reduced to an average value equal to the number of pixel data of one region.

On the receiving side, blocks with motion are decoded in the three-dimensional decoder 30, and areas A1 and A
The pixel data of the block consisting of 2 is restored. on the other hand,
For static blocks, the interframe average value (A3+A
4)/2 is decoded, and the inter-frame average value is used as data for each region of two consecutive frames.

In the simple OR output of the respective decoded outputs of the two-dimensional decoder 25 and three-dimensional decoder 30 obtained in this way, there is a difference in the image between the inter-frame average value data area and the previous area of another block. The movement of the object becomes discontinuous, causing unnatural movement (jerkiness).

In the present invention, smoothing processing is performed in order to prevent jerkiness when transitioning from a temporally previous still block to the region of the inter-frame average value of the current still block. In other words, as shown in Fig. 12, when stationary blocks are consecutive, instead of the data (A5+A6)/2 of the next block located at the boundary with the previous block, the last area of the previous block and the current The data of the average value (A3+A4+A5+A6)/4 of the data in the first area of the block is used. This smoothing process is not performed when moving from the previous motion picture area A2 to the inter-frame average value area (A 3 +A 4)/2.

The above-described smoothing process produces an image in which the image information of the previous still block and the current still block are mixed between temporally consecutive still blocks, so that jerkiness is reduced. In addition, since smoothing processing is not performed when the previous block is a motion block, distortion in which part of the outline of a moving object in the image of the previous block appears in the image of the current block is prevented.

Referring to FIG. 13, an operation for reducing jerkiness of the receiving side configuration shown in FIG. 2 will be described.

FIG. 13A shows the received determination code SJ. This determination code SJ changes in synchronization with changes in the block on the receiving side. 13B shows the decoded data formed in the two-dimensional decoder 25, and FIG. 13C shows the decoded data formed in the three-dimensional decoder 30.
In FIG. 3, as in FIG. 12, only the processing of one area AI-A6 among the four areas of one frame is shown. These areas Al-A6 belong to three temporally consecutive frames. Therefore, as can be understood from the fifth diagram, the omitted portions in the time chart of FIG. 13 include other regions B and C.

A signal regarding D is included.

In the control pulse generation circuit 33 (see Fig. 2), the 13th
As shown in the figure, a timing signal and a judgment signal SJ (Fig. 13A
) &, as shown in FIG. 13E, a control pulse that goes high is formed corresponding to the region at the head of a still block where the previous block is a still block. The switch circuit 26 is controlled by this control pulse. When the control pulse is at a low level, the switch circuit 26 selects the decoded output of the two-dimensional decoder 25 supplied to the input terminal a, and when the control pulse is at a high level, the switch circuit 26 selects the decoded output of the two-dimensional decoder 25 supplied to the input terminal a. The output signal of the value forming circuit 27 is selected.

Further, the delay amount Td of the delay circuit 34 is selected to be (Td=7Ta) when the period of one region is expressed as Ta. Therefore, the delay circuit 34 generates an output signal which is the output signal of the OR gate 31 delayed as shown in FIG. 13F, and is supplied to the average value forming circuit 27. The switch circuit 26 is controlled by the control pulse from the control pulse generation circuit 33, and the OR gate 31 provides a decoded output that has been smoothed when transitioning from a stationary block to a stationary block, as shown in FIG. 13G. It will be done.

j. Modification The present invention is applicable not only to variable length encoding systems but also to fixed length encoding systems. In the fixed length encoding method, 1. Guinami Socle for each block.

The digital signal DR is divided into a number of level ranges determined by the number of quantization bits, and a predetermined code signal of Pino)B corresponding to the level range to which the data after minimum value removal belongs is formed.

In this embodiment, as is clear from FIG. 10, the median values LO and L of each region obtained by dividing the dynamic range are
l, L2, . . . are used as values during decoding. This encoding method can reduce quantization distortion.

On the other hand, pixel data having the minimum level MTN and the maximum level MAX always exist within one block. Therefore, in order to increase the number of code signals with an error of O, as shown in FIG.
2'-1) ((B, m is the number of quantization bits), the minimum level MIN may be set as the representative minimum level LO, and the maximum level MAX may be set as the representative maximum level L3.
The illustrated example shows a case where the number of quantization bits is 2 bits for simplicity.

In the above explanation, the code signal DT, dynamic range DR, minimum value MIN, and determination code SJ are transmitted. However, instead of the dynamic range DR, the maximum value MAX, quantization step, or maximum distortion may be transmitted as the additional code.

In addition, one block of data is processed by a circuit that combines a frame memory, a line delay circuit, and a sample delay circuit.
They may be taken out at the same time.

Further, the three-dimensional block is limited to two frames, but may be made up of data of three or more n frames.

〔Effect of the invention〕

According to this invention, when data in the area of a stationary block is replaced with data of the average value of this block, jerkiness that occurs when blocks change can be reduced, and the stationary block can be Since the smoothing process is performed only when the images are continuous, it is possible to prevent new distortion from occurring due to smoothing, and it is possible to obtain a good restored image.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the transmitting side of a high-efficiency code to which the present invention can be applied, Fig. 2 is a block diagram showing the configuration of the receiving side of an embodiment of the present invention, and Fig. 3 is a block diagram of the unit of encoding processing. A route map used to explain a certain block, Figures 4 and 5 are an example of the configuration of a blocking circuit and a route map for explaining it, Figure 6 is a block diagram showing the configuration of an encoder, and Figure 7 is a transmission diagram. A route map showing the data structure, FIG. 8 is a block diagram showing the configuration of the two-dimensional decoder, FIG. 9 is a block diagram of the dynamic range detection circuit, and FIG. 10 is a route map for explaining variable length encoding. FIG. 11 is a block diagram of an example of a motion determination circuit, FIG. 12 is a route diagram for explaining encoding and decoding operations, FIG. 13 is a route diagram for explaining decoding operations, and FIG. 14 is a route diagram for explaining quantization. It is a route map for explaining another example. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2-blocking circuit, 3: Motion determination circuit, 5: Inter-frame average value forming circuit, 6: 2-dimensional encoder, 9: 3-dimensional encoder, 7
, 10: Framing circuit, 25; Two-dimensional decoder, 30
: 3D decoder, 27: Average value forming circuit, 35 Niblock decomposition circuit. Figure 4: Block 1: Figure 6: Word data Figure 7: 2 blowing decoater Figure 9: 1V key 1: 1a path Figure 11

Claims (1)

[Claims] Find the maximum value of a plurality of pixel data and the minimum value of the plurality of pixel data included in a block consisting of n regions belonging to each of n temporally continuous frames of a digital image signal. At the same time, the dynamic range for each block is detected from the maximum value and the minimum value, and the minimum value is subtracted from the values of the plurality of pixel data to form input data after the minimum value has been removed. Regarding the determined block, the input data after the minimum value removal is encoded within the detected dynamic range with a number of quantization bits smaller than the original number of quantization bits, and a code signal is generated. In the determined block, only the code signal related to the average value information of the data of the corresponding pixels in the n areas is generated, and the code signal is generated based on the dynamic range information and at least two of the maximum value and the minimum value.
In a high-efficiency code decoding device that transmits additional codes, a code signal obtained by the above encoding, and a judgment code indicating the presence or absence of movement, the block is a still block indicated by the judgment code above, and If the previous corresponding block is a static block, the average value of the data in the last area of the previous block and the data in the first area is generated as the data in the first area of the n areas. A high-efficiency code decoding device characterized in that: