JPS6375843A - Abnormality monitor system - Google Patents

Abstract

PURPOSE:To prevent degradation in throughput by monitoring two CPUs by each other and restarting and restoring a faulty CPU by the other normal CPU when one CPU is faulty. CONSTITUTION:If the response to monitor data is not sent within a prescribed time, a break signal 52 is sent from a break signal sending means 35. A first counting means 36 of the CPU which receives this signal generates an interrupt signal 53 at the time of counting a prescribed bit length, and a second counting means 37 outputs a reset signal 54 at the time of counting a bit length longer than said prescribed bit length. A restoration processing part 38 inhibits the output of the reset signal 54 to perform the restoration processing such as retry when receiving the interrupt signal 53, and the processing part 38 responds to a restoration message 55 when the other CPU is restored. Thus, the break signal 52 is stopped and the processing is restarted.

Description

[Detailed Description of the Invention] [Summary] In a processing device equipped with two sets of processor units (CPUs) that mutually monitor abnormal conditions by exchanging monitoring data via a serial interface, after sending the monitoring data, a predetermined When there is no response within the time, a break signal is sent, and the CPU that receives this break signal counts the bit length of the break signal to a predetermined length and generates an interrupt signal and a reset signal.

Restoration processing is performed with the current state held in response to the interrupt signal, and when restoration processing is not possible or when interrupts are not possible, a reset signal is generated to reset each part, and if normal, restoration is performed.

As described above, an abnormality monitoring method is provided in which the disconnection process is performed after attempting the recovery process.

[Industrial application field]

The present invention provides a system in which two sets of CPUs mutually monitor each other, and a CPU that detects an abnormality automatically recovers it.In a processing device that requires reliability of the monitoring system, for example, two sets of CPUs are provided to share functions, and one When a CPU goes down, all processing is performed by the other CPU, but there is a problem in that the processing capacity decreases when the failed CPU is disconnected.

For this reason, there is a need for a processing device that can restart and restore a down CPU and prevent a decrease in processing performance.

[Conventional technology]

Figure 3<a) is a block diagram of an I10 controller that is equipped with two sets of CPUs and controls a plurality of Ilo, and Figure 3 ('b
) is an explanatory diagram of a conventional abnormality monitoring system.

In FIG. 3(a), 1 and 2 are processor units (
CPU, one of the following two sets of CPUs is CPUI.

The other is a CPU 2)) which is connected to a host (not shown) and controls the I/O devices 14 and 15, respectively, and 13 is a switching unit, which together with the CPU 1.2 constitutes an I10 controller. It is something.

In the above I10 controller, the CPUI is ■/○ device 1
4, CPU2 controls l1015, and CPU
The configuration is such that mutual monitoring is performed between U1 and U2, and when one (for example, CPU2) goes down, the other (CPUI) detects this, notifies the switching unit 13, and connects the I10 device 15 to the CPUI. It is something that exists.

Mutual monitoring between the CPUs 1 and 2 is performed using a serial interface (serial IF control unit 6.
11), the monitoring data 50 and 51 are exchanged at fixed time intervals, and when there is no response from the other party within the predetermined time (10), it is determined that there is an abnormality and the I10 device is switched.

[Problem that the invention seeks to solve]

In the conventional abnormality monitoring method described above, even if the abnormal state is a temporary failure and can be recovered, disconnection is performed by a normal CPU.

Therefore, there is a problem in that a processing load is placed on the normal CPU, and the processing capacity of the I10 controller is reduced.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a simple abnormality monitoring method that allows a normal CPU to perform recovery processing.

[Means for solving problems]

For the above purpose, the abnormality monitoring system of the present invention sends out a break signal (52) when monitoring data is not received within a predetermined time, as shown in FIG. 55)
a break signal sending means (35) that stops sending the break signal when the received break signal (35) is received;
52), and when the first set value is reached, an interrupt signal (53) is activated to start the recovery processing section (38).
); and a first counting means (36) that counts the bit length and resets each part when a second set value is reached, which is set to a value that is less than or equal to the first set value. a second counting means (37) that outputs a reset signal (54); and a prohibition means (3) that prohibits output of the reset signal (54).
9), and instructing the inhibiting means (39) to send the reset signal (54).
a recovery processing unit (38) that prohibits the output of and executes a recovery process, responds with the recovery message (55) after the recovery is completed, and cancels the prohibition means (39) when recovery is impossible; and the reset signal. (54) Verify the normality of each part after output,
Each processor unit (CPU1, CPU2) is provided with a reset processing section (40) that sends out the recovery message (55) when it is determined to be normal.

[Effect]

When there is no response to the monitoring data within a predetermined time, a break signal 52 with consecutive spaces is sent out, and the CPU that receives this break signal 52 counts its bit length.

The first counting means 36 generates an interrupt signal 53 when counting a predetermined bit length (first setting value), and the second counting means 37 generates an interrupt signal 53 when counting a predetermined bit length (second setting value). is counted and a reset signal 54 is output.

Upon receiving the interrupt signal 53, the processor saves the current processing state and requests the recovery processing unit 38 to perform recovery processing.

The recovery processing unit 38 prohibits the output of the reset signal 54 and performs recovery processing such as retrying, and when recovery is achieved, returns a recovery message 55 to return control to the processor (return).

As a result, the break signal 52 is stopped and processing is restarted.

If recovery is not possible in the above recovery process, the inhibition of output of the reset signal 54 is canceled and the reset signal 54 is output.

Similarly, a reset signal 54 is output when the interrupt signal 53 is not accepted.

After resetting, each part is tested, and if there is no abnormality, a recovery message 55 is returned to restore the system.

Note that if there is no response to the recovery message 55 within a predetermined time, the CPU on the normal side performs the disconnection.

As described above, a CPU that detects an abnormality transmits a break signal 52 before disconnecting, and causes the abnormal CPU to perform recovery processing.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1, 2, and 3.

, FIG. 2 is a CPU block diagram of the embodiment.

CPU1 and CPU2 have the same configuration, and FIG.
This figure shows the main parts of one of the processor unit CPUs. In the figure, 20 is a serial interface (IF) control unit, 21 is a processor, and 31 is a monitoring data break signal transmitting unit, which corresponds to the break signal sending means 35 and periodically exchanges monitoring data 50 and 51 with the serial interface control unit. 20, and a timer (not shown) transmits a break signal 52 when there is no response for a predetermined time (tl), and when a recovery message 55 is received, the break signal 52 is transmitted.
24 is a counter (first counting means) which transmits an interrupt signal 53 to the processor 21 through the latch circuit 26 when it counts the bit length of the received break signal 52 for a predetermined length (time L2). 26 is a counter (second counting means) that counts the received break signal 52 for a predetermined length (time L3, t3>t2) and outputs a reset signal 54 via an AND gate 28; 27 is a prohibition register (inhibition means 39) in which data for prohibiting the output of the reset signal 54 is written; 29 is a latch circuit that stores the output state of the reset signal 54; and 40 is a reset processing section which is activated after reset. , which tests each part when the reset output is set in the latch circuit 29, and responds with a recovery message 55 if it is normal. 100 is a bus line composed of an address bus, a data bus, etc.

In the CPU having the above configuration, the supervisory data break signal generating section 31 operates normally, and the break signal processing means 22 shown by the dotted line in FIG. 2 operates when a break signal is received.

In the following operation explanation, the normal side will be referred to as the CPUI.

The abnormal side is CPU2, and the reference numeral in FIG. 2 is CPU2. When indicating the CPU1 side, (CPUI) is added to distinguish it.

Further, the symbols other than the CPU are those shown in FIG. 3.

The recovery operation will be explained below with reference to the first report.

The CPU I and the CPU 2 each periodically receive the monitoring data 50 (CPU
I) and 51 (CPU2) to each other via the serial interface control unit 20.20 (CPUI).

When the CPU 1 does not receive the monitoring data 51 from the CPU 2 within a predetermined time (tl), the monitoring data break signal transmitter 32 (CPUI) sends a break signal 5 to the CPU 2.
Send 2.

As mentioned above, the break signal 52 is a space (“0
In the CPU 2 that receives the break signal 52, the counters 24 and 25 count the internal clock 56 of the serial interface control unit 20 using the break signal 52 as an enable signal, and the counter 24 counts the internal clock 56 of the serial interface control unit 20. When the value (t2) is counted, the carry output C is latched in the latch circuit 26 and an interrupt signal 53 is output to the processor 21.

Thereby, the processor 21 saves the current processing state and starts the recovery processing section 31.

The recovery processing unit 31 sets the prohibition register 28 to prohibit the output of the counter 25, that is, the output of the reset signal 54, and executes the recovery process.

When the recovery process is completed, a recovery message 55 is sent to the CPUI and control is returned to the processor 21 (return).
When the break signal is stopped, the operation is resumed from the time the abnormality occurred based on the saved data.

If recovery is not possible, the prohibition register 28 is reset to permit reset output, and the counter 25 outputs the reset signal 54 after a predetermined time (t3), and the CPtJ
2 returns to the initial state.

In the reset CPU 2, the reset processing section 40 is activated, reads the launch circuit 29, and if the reset output is set, it recognizes that an abnormality has been detected and tests each section, and if normal, sends a recovery message 55 to the CPUI. Send.

As described above, the interrupt signal 53 and the reset signal 54
However, if the recovery process is not possible, the CP
Detachment is performed by the UI.

That is, the CPU 1 transmits the break signal 52 for a certain period of time.
When the connection continues, the switching section 13 is commanded to switch the I10 device 15 to C.
Switch to PUI side.

Although not shown, the counters 24 and 25 are reset when the serial data is "1".

As described above, the break signal 52 is sent before disconnection, and the abnormal side performs recovery processing based on this break signal, making it possible to recover from a temporary failure due to software runaway.

(Effects of the Invention) As explained above, the present invention provides a system in which a CPU that detects an abnormality issues a break signal and automatically recovers. The effect of preventing performance deterioration in is extremely large.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram explaining the principle of the present invention (part 1), FIG. 1(b) is a diagram explaining the principle of the present invention (part 2), FIG. 2 is a CPU block diagram of the embodiment, and FIG. (a) is a block diagram of a conventional I10 controller, and FIG. 3 (bl is an explanatory diagram of a conventional abnormality monitoring system). In the figure, 1.2 is a processor unit CPU. 3 is a switching unit, and 6.11 is a serial interface. (IF) control unit, 14, 5 is an I10 device, 20 is a serial interface (IF) control unit 21 is a processor, 24.25 is a counter, 26 is a latch circuit, 27 is an inhibit register, 28 is an AND gate, 29 is a A latch circuit, 31 is a monitoring data break signal transmitting section, 35 is a break signal sending means, 36 is a first counting means, 37 is a second counting means 38 is a recovery processing section, 39 is an inhibiting means, and 40 is a reset processing section. , 50.51 is monitoring data, 52 is a break signal, 53 is an interrupt signal, 54 is a reset signal, 55 is a recovery message, and 56 is an internal clock.

Claims (1)

[Claims] Monitoring data (50, 5
1) In a processing device equipped with two sets of processor units (CPU1, CPU2) that exchange and monitor each other and disconnect when each detects an abnormality, a break signal ( 52) and also sends a recovery message (55
); and a recovery processing unit that counts the bit length of the received break signal (52) and when it reaches a first set value. An interrupt signal (53) that activates (38)
); and a reset signal that counts the bit length and resets each part when a second set value set to at least the first set value is reached. (54), a second counting means (37) that outputs the reset signal (54), and a prohibition means (3) that prohibits the output of the reset signal (54).
9), and instructing the inhibiting means (39) to send the reset signal (54).
a recovery processing unit (38) that prohibits the output of and executes a recovery process, responds with the recovery message (55) after the recovery is completed, and cancels the prohibition means (39) when recovery is impossible; and the reset signal. (54) Verify the normality of each part after output,
A reset processing unit (40) that sends out the recovery message (55) when it is determined to be normal is connected to each processor unit (CPU1, CPU2).
), wherein a processor unit that detects an abnormal state sends out the break signal (52) to perform recovery processing.