JPS634210B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for diagnosing other systems in a storage program controlled information processing system in which control systems are duplicated.

The conventional method for diagnosing other systems in a duplex system was to cause both systems to operate synchronously using the same program, and to compare the results.

In such a conventional system, both systems must always perform the same operation and collate the results, resulting in a large waste of processing capacity of the control system.

Additionally, when a failure occurs, the normal system and abnormal system are tightly coupled, so depending on the type of failure, there is a risk that the failure will spread from the abnormal system to the normal system, resulting in a system down. It was hot.

An object of the present invention is to provide a method for diagnosing other systems in a redundant system that can eliminate the drawbacks of the prior art described above, reduce wasted processing capacity, and prevent a failure in an abnormal system from spreading to a normal system. It's about doing.

A feature of the present invention is that the dual system is a standby system, and when a failure occurs in the regular system, the system is switched to the backup system, and the diagnostic program is transferred from the backup system to the regular system via a transfer device. However, there is a method for diagnosing other systems in which this system is made to perform fault diagnosis and the results are sent back to the standby system.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system configuration diagram of an embodiment of the other-system diagnosis method according to the present invention.

Here, 1A and 1B are control systems A and B, respectively.
The processors 2A, 2B are the same memory, 3A,
3B is the same peripheral control device, and corresponds to, for example, a peripheral memory control device or a communication path control device in an electronic exchange; 4A and 4B are the same bus; 5A and 5B are the same transfer device; and 6 is the same peripheral control device. System control.

First, the outline of this embodiment will be explained based on FIG.

Normally, for example, control system A becomes the regular system and performs control processing, and control system B becomes the backup system and stands by, so that it can immediately take over control and processing in the event of a failure in the regular system. It's summery.

During execution of control/processing, for example, peripheral control device 3
When a failure occurs in A, the processor 1A learns of the failure from a failure detection report from the peripheral control device 3A itself or from failure detection by a program.

When a failure does not have a significant impact on system control and processing, system switchover is not performed, and when it has a significant impact, system switchover is performed to ensure that the entire system is not affected by the failure. do.

This system switching is performed by the system control 6 in response to a signal from the processor 1A of the failed control system A, and from then on, the control system B becomes the regularly used system.

After system switching, the processor 1B transfers the transfer device 5B,
After the diagnostic program is transferred from the memory 2B to the memory 2A via the processor 5A, a signal to start diagnosis is sent to the processor 1A.

As a result, the processor 1A performs fault diagnosis based on the diagnostic program, and transfers the data to the transfer device 5.
The diagnostic data is sent to the processor 1B via A and 5B.

The processor 1B analyzes this, determines the location of the failure, and displays a failure indication to that effect.

This allows maintenance personnel to perform appropriate processing.

Next, FIG. 2 is a block diagram of related parts of one embodiment of the system control 6 in FIG. 1.

Here, 61 is a failure information reception gate, 62
is a fault information holding flip-flop; 63 is an interrupt flip-flop; 64 is an AND gate;
5 is a device number sending circuit, and 66 is a delay circuit.

When the processor 1A of the regular system, for example the control system A, detects a fault, the fault information is sent to the system control 6.

In the system control 6, this fault information passes through a fault reception gate 61 and inverts a fault information holding flip-flop 62.

Furthermore, its output Q is connected to the interrupt flip-flop 6.
3, and its output Q becomes an interrupt signal INT for the standby processor 1B, which should be normal.

On the other hand, when the interrupt response signal INT AK is returned from the processor 1B, this and the output Q of the interrupt flip-flop 63 are ANDed by the AND gate 64, and the output is used to determine the device number. The sending circuit 65 is activated and the device number information related to the failure is sent to the bus 4B.

Thereby, the processor 1B reads the device number information from the bus 4B, can identify the device in which the failure has occurred (for example, the peripheral control device 3A), and operates to prepare for other system diagnostic processing.

That is, as mentioned above, the processor 1B
A diagnostic program necessary for diagnosing the failed control system A is transferred to the control system A via the transfer devices 5B and 5A.

On the other hand, with the activation of the device number sending circuit 65,
The output of the AND gate 64 is input to a delay circuit 66 to allow time for the processor 1B to reliably receive the device number information, and the interrupt flip-flop 63 is reset by the output of the delay circuit 66.

Note that the fault information holding flip-flop 62 is
Before that, it was reset by the interrupt response signal INT AK.

The transfer operation of the diagnostic program will be specifically explained below.

FIG. 3 shows transfer devices 5A and 5B in FIG.
This is a block diagram of one embodiment of the present invention, and only the part related to the transfer from the control system B to the control system A is shown, but there is a similar diagram for the opposite direction.

Here, 51 is an address decoder, 52 is
A transfer request flip-flop, 53 is a transmission register, 54 is a transmission gate, 55 is a timing register, 56 is a reception circuit, 57 is a reception register, 58 is a memory control circuit, and 59 is a NAND gate.

When the processor 1B receives a system switching instruction from the system control 6, it becomes the regular system and starts controlling and processing the system, but first it transfers the diagnostic program to the control system A that is in trouble. I do.

In this case, an address related to the diagnostic program is set in the address decoder 51 via the bus 4B.

The address decoder 51 decodes this,
It sends an interrupt signal INT to the processor 1A through the cable driver, pair cable, and cable receiver, and also sends the transfer request flip-flop 5.
2, and also sets bus 4 to the reception register 53.
Import the data related to the diagnostic program on B.

The output Q of the transfer request flip-flop 52 is ANDed with the status signal S from the memory control circuit 58 (indicating that the control system A is ready to receive data) at the NAND gate 59, and the output is sent to the transmission gate. 54 gate signal, the transmission gate 54
is opened and the data in the reception register 53 is sent onto the data line DL.

On the other hand, the gate signal is also input to the timing register 55, causing it to start counting the clock CLK.

When the timing register 55 counts the time for the data on the data line DL to become sufficiently stable,
sends out output Q _B , which is a cable driver,
It passes through the pair cable and the cable receiver, becomes a set signal for the reception register 57, causes the data on the data line DL to be taken in through the reception circuit 56, and activates the memory control circuit 58.

Moreover, the time longer than the output Q _B (at least
According to the output Q _C corresponding to the time when the reception register 57 can reliably receive the data on the data line DL,
Reset the interrupt request flip-flop 52.

The memory control circuit 58 controls the data in the reception register 57 to be sent onto the bus 4B, and also sends out a memory activation signal E to activate the memory 2.
Write data to B.

This write address AD is uniquely determined in advance as one for the diagnostic program, and its first address is specified.

When the transfer of the diagnostic program is completed, the processor 1B again issues an interrupt request to the faulty processor 1A in the same manner as described above.

Thereby, the processor 1A knows that the diagnostic program has been stored in the memory 2A, and operates the diagnostic program.

When the diagnosis is completed, the processor 1A, conversely,
The diagnostic results are transferred to the processor 1B via transfer devices 5A and 5B.

This operation is performed by a reverse circuit (not shown) similar to the case of transferring the diagnostic program described above.

Based on the diagnosis result, the processor 1B identifies the fault location (for example, the package number of the peripheral control device 3B, etc.) and transfers the data to the transfer device 5B,
It can be sent back via 5A and displayed on the fault display circuit of fault system A.

As explained above in detail, according to the present invention, the regular system operates independently, and when it becomes a failure, it is immediately switched to the normal standby system, and the system can no longer operate. At the same time, the failure diagnosis of the failure system can be performed.
Since there is no wasted processing power in the system, and there is no tight coupling between processors, failures in the faulty system will not spread to the normal system, resulting in significant improvements in efficiency and reliability of the redundant system.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an embodiment of the other system diagnosis method according to the present invention, FIG. 2 is a block diagram of related parts of an embodiment of the system control 6, and FIG. 3 is a diagram of the same transfer device. 5A and 5B are block diagrams of one embodiment. FIG. 1A, 1B...Processor, 2A, 2B...Memory, 3A, 3B...Peripheral control device, 4A, 4B
... Bus, 5A, 5B ... Transfer device, 51 ... Address decoder, 52 ... Transfer request flip-flop, 53 ... Transmission register, 54 ... Transmission gate, 55 ... Timing register, 56 ... Receiving circuit, 57 ... Reception register, 58 ... Memory control circuit, 59 ... NAND gate, 6 ... System control, 61 ... Failure information reception gate, 6
2... Fault information holding flip-flop, 63...
Interrupt flip-flop, 64...and gate,
65...Device number sending circuit, 66...Delay circuit.

Claims (1)

[Scope of Claims] 1. In a multi-system diagnostic method for a storage program controlled information processing system in which the control system is duplicated,
Of the duplicated control systems, the first system is a regular system and the second system is a standby system, and when a failure occurs in the first system, the second system is activated based on the failure information regarding this. a system switching step of switching the system to the regular system; a step of transferring a diagnostic program from the second system to the failed first system via a transfer device provided between the two systems; a step in which the first system executes the diagnostic program in parallel with the normal operation of the second system; a step in which the first system independently determines the end of the execution; and a step in which the first system executes the diagnostic program in parallel with the normal operation of the second system; Step 2 of returning to the system and based on this,
A system for diagnosing other systems, characterized in that the second system has a step for identifying a fault location. 2 In the method described in claim 1,
The transfer device has the same configuration for both systems, and is started by the processor of its own system, and starts and controls the processor and memory of the other system.
A cross-system diagnostic method that allows mutual transfer of diagnostic programs, fault diagnosis results, and other necessary data. 3. In the method described in claim 1 or 2, both systems are controlled by a system control, and the system control receives fault information from the processor of the faulty system and retains it. requests an interrupt to the processor in the normal system, and receives the interrupt response signal.
A method for diagnosing other systems that sends out device number information related to a failure and stops interrupt request signals after a predetermined period of time. 4 In the method described in claim 1,
The dual systems are mutually coupled via a bus line, and the above-mentioned diagnostic program is transferred and the execution result of the above-mentioned diagnostic program is returned via the bus line.