JP2966966B2 - Redundant device for programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system of a standby type programmable controller which is used in a control for which a system down is not allowed in a programmable controller for controlling a plant system, for example.

[0002]

2. Description of the Related Art Conventionally, as an example of such a type of a redundant controller for a programmable controller, there is one configured as shown in FIG. In this configuration, a duplex unit 3 is arranged between two programmable controllers PC1 (hereinafter, referred to as a controller 1) and a programmable controller PC2 (hereinafter, referred to as a controller 2).

The duplexing unit 3 includes a monitoring unit 5 that monitors the controllers 1 and 2 of each other, controls a switching signal between the active side and the standby side based on the monitoring result of the monitoring unit 5, and controls the transmission / reception state of docking data. It has a duplex control unit 6 for inputting and outputting data to 1 and 2 and a buffer memory 7.

A stator bus (STS1) 8 for notifying and detecting the operating state of the controller 1 is arranged between the monitoring unit 5 and the controller 1, and between the monitoring unit 5 and the controller 2, A status bus (STS2) 9 for notifying and detecting an operation state is provided.

[0005] Between the dual control unit 6 and the controller 1,
An interrupt bus 10 (INT1) for notifying the transmission and reception of the switching signal and the tracking data and a control bus 12 (C
NT1), and an interrupt bus 11 (INT2) and a control bus 13 (CNT2) for notifying transmission / reception of a switching signal and tracking data are disposed between the duplex control unit 6 and the controller 2.

A data bus (DBS1) 14 for transmitting and receiving tracking data is arranged between the buffer memory 7 and the controller 1, and a data bus for transmitting and receiving tracking data between the buffer memory 7 and the controller 2. A bus (DBS2) 15 is provided.
An IO bus (IOBS1) 16 is arranged between the controller 1 and the I / O unit 4, and the I / O unit 4
An IO bus (IOBS2) 17 is arranged between the units 4.

Now, assuming that the controller 1 is on the operating side and the controller 2 is on the standby side, the monitoring unit 5 of the duplex unit 3 grasps the status of both controllers 1 and 2 via the status buses 8 and 9. The working controller 1
The tracking data, which is the control result, is periodically written to the buffer memory 7 of the duplex unit 3 via the data bus 14, and when the writing is completed, it is notified to the duplex control unit 6 of the duplex unit 3 via the control bus 12, and the duplex control unit 6 When the standby controller 2 is notified via the interrupt bus 11, the standby controller 2 reads out the tracking data via the data bus 15 and takes in the tracking data. When the reading is completed, it notifies the duplication control unit 6 of the duplication unit 3 via the control bus 13. The duplication control unit 6 receives the request, and operates the controller 1 on the operation side.
The completion of reading is notified via the interrupt bus 10. During this time, the controller 1 of the operating system does not write the tracking data of the next cycle.

If the controller 1 on the operating side goes down due to a fatal abnormality, the duplexing unit 3 detects this via the status bus 8 and the duplexing control unit 6 sends it to the standby side via the interrupt bus 11. The switching signal is notified to the controller 2. When the controller 2 on the standby side receives the switching signal, it rises to the operating side and continues to execute the control based on the tracking data that has been captured so far.

[0009]

In the conventional system described above, a duplex system is established while the duplex unit 3 always intervenes. Therefore, the redundant unit 3
Must have high reliability.

Therefore, the present invention can monitor the operation state of each other and transmit and receive tracking data only by the function of the controller without using the redundant unit, and can always detect the operation state of the other party and perform the backup operation with high accuracy. An object of the present invention is to provide a programmable controller duplex device that can be controlled.

[0011]

According to the present invention, to achieve the above object, one of the two program controllers is in an operating state and the other is in a standby state in preparation for backup. monitoring the state of a partner, working side detects that it waiter Once down continues executing control operation side, there is to prevent the system down, detecting and notifying the state of the programmable controller of the other party to each other physician Status / command bus and status / command bus input / output port for interfacing the same, and execution result information which is data for the programmable controller to continuously execute control at the time of backup to the partner programmable controller. Data bus and interface with it It comprises a chromatography data bus interface, and a buffer for receiving and transmitting the execution result information
In a programmable controller redundant device,
It divides the execution state of its own process controller into a plurality of phases and constantly notifies each of them via the status / command bus to the other process controller. From the other process controller phase and its own process controller phase, the And a phase management table for determining a phase to be changed next , and controlling the next backup operation processing.

[0012]

According to the present invention, only a status / command bus, a status / command input / output port for interfacing the status / command bus, and a data bus and a data bus interface for interfacing the data bus are provided. A highly reliable programmable controller duplication device can be configured.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the present invention, in which a programmable controller PC1 (hereinafter referred to as a controller 20), a programmable controller P
C2 (hereinafter referred to as the controller 21) is configured as follows, and a status / command bus 30 and a data bus 31 are arranged between them.

The controllers 20 and 21 have the same configuration, control the entire system, and output a reset signal from a reset signal line for switching between a transmission / reception mode and a reset mode.

A status signal and a command signal can be exchanged bidirectionally via a status / command bus 30, and an interrupt can be generated in a partner by sending a command signal. The status / command input / output ports 24 and 25 capable of resetting the status signal output to zero by issuing a reset signal to the reset signal lines 32 and 33 from, and temporarily store the received tracking data. Buffer memories 28 and 29 for
Data bus 31 connecting between buffer memories 28 and 29
When,

Buffer memories 28 and 29 and main bus 3
4, 35, and can exchange data bidirectionally, and can switch between the transmission / reception mode and the reset mode by reset signals from the reset signal lines 32, 33 from the processors 22, 23, Further, in the transmission / reception mode, data is transferred to the buffer memory
8 and 29 can be written directly, and the data in the own buffer memories 28 and 29 can be read.
Data bus interfaces 26 and 27, which cannot read and transmit only data 8 and 29,

The memories 36 and 37 in which phase transition management data for determining the backup operation of the controller described later are stored in advance, and the I / O interface 38 and
39.

Each of the memories 36 and 37 has a phase transition management table 200 as shown in FIG. 2, in which phase transition management data as shown in an enlarged view 201 is stored in advance, and the own phase is stored in the Y-axis 203. The other party's phase 202 is placed in each phase row, and its own phase 204 to be transited next is obtained on the X-axis from the correlation. In the figure, reference numeral 205 denotes a check direction of the opponent's phase, 206 denotes a direction of detecting the next phase of the user, 207 denotes a current own phase, 208 denotes a next transition phase, and 209 denotes a current opponent phase.

In such a configuration, the status / command input / output ports 24 and 25 can notify their counterpart controllers by a status signal via the status / command bus 30 as their phases as a phase. Status of other party is indicated by status bus / command 30
Can be known as a phase through. Then, the phase 209 of the current opponent corresponding to the row of the current own phase 207 from the phase transition management table 200
Is checked in the direction of 205, and if there is a corresponding one, the next transition is to be made in the 206 direction at that time.
08 is taken out and its processing is executed.

Now, when an error occurs in the active controller, for example, 20, the processor 22 automatically makes the signal on the reset signal line 32 inactive and clears its own status signal output from the status / command input / output port 24 to zero. I do. Thereby, the controller for example 21 of the standby side, by the status signal of the other status / command output port 25 becomes zero clear condition, it can detect the error down opponent, standing as running side at the timing Can be raised. When the command signal is output via the status / command bus 30, an interrupt can be input to the other controller, and the command signal can be used for notifying a transmission completion interrupt signal or the like of tracking data. The data bus interfaces 26 and 27 allow the operating side to directly transmit tracking data to the other buffer memories 28 and 29 via the data bus 31. When notifying the other party of the controller a transmit complete interrupt signal through the status / command bus 30, waits side complete interrupt is generated transmission, tracking data written in the buffer memory 29 at the timing of its <br/> Can be received, and upon completion of the reception, the completion of reception can be notified to the operating side through the status bus / command bus 30.

A specific embodiment of the present invention will be described below with reference to FIGS. Figure 3 is a block diagram showing the configuration, the controller 40 and 41 includes a processor 42 and 43 performs overall control, described later program execution process (Fig. 4), tracking processing (FIG. 5), collected by La <br/> Tsu King data reception process (FIG. 6), monitor the process (FIG. 7)
11 and a memory P that stores a plant control program (73 in FIG. 4).
44, 45, memories D 46, 47 capable of storing operation data and I / O data, and I / O units 56, 57
I / O interface 5 for interfacing with
Between 4,55 and status / command output port 49 to interface between the stator bus (SBS) 62 and the command bus (CBS) 63, a bus Ffamemori 52, 53 and main bus 58, 59 Data bus interfaces 50 and 51, buffer memories 52 and 53 for temporarily storing received tracking data, and a status / command input / output port 4
Reset the 8,49, the reset signal line switches the operation mode of 且 one data bus interface 50, 51 6
0, 61 and status / command I / O ports 48, 4
9, a command bus 63, a data bus 64 connecting between the data bus interfaces 52, 53, the processors 42, 43, and the memory P.
And 44 and 45, and the memory D 46,47, the I / O interface 54 and 55, and the status / command input and output ports 48 and 49, data interface 50, 51
And I / O interfaces 54 and 55, and I / O buses 65 and 66 connecting between the I / O units 56 and 57.

Status / command input / output port 48
Is configured as shown in FIG.
Is once latched by the register with reset 481, and is output as it is when the reset signal 486 of the reset signal line 60 is inactive.
86 is active, the register with reset (O
R) 481 is reset to zero and the output becomes zero. The input of the status bus 487 is once input to the register (RR) 48.
2 and can be read at any time.

The output of the command bus 488 is once latched by a register with reset (OR) 483. When the reset signal 486 is active, it is output as it is. When the signal is inactive, the register with reset 483 is reset to zero and the output is zero. Become. The input of command bus 488 is once latched in register (RR) 484 and can be read at any time, and is simultaneously latched in interrupt output register (IR) 485 so that an interrupt is signaled via interrupt line 490. The status / command input / output port 49 has the same configuration as the status / command input / output port 48 described above.

The data bus interfaces 50 and 5 shown in FIG.
1 indicates that the transmission of data is transmitted through a transmission gate (not shown). If the reset signal is inactive, data is transmitted to the data bus 64; if active, the data is not transmitted to the data bus 64. The data reception is written to the buffer memory 52 as it is. The data in the buffer memory 52 can be read as it is.

Next, a method of creating a phase transition management table will be described with reference to the phase transition diagram of FIG.
As shown in the phase transition diagram of FIG. 9, the phase 300 includes a power ON (power ON) 302, a semi-standby 303, and a standby 3
04, operating 305, independent operation 306, and down / power OFF (power OFF) 307.

The power ON 302 indicates when the power is turned on, the quasi-standby 303 indicates preparation for operation or standby, and
04 indicates a state of being switched to operation at any time, operating 305 indicates a state in which a program is being executed, and single operation 306 indicates that the operating side is operating without the standby side waiting. In the phase 300, the next phase is determined based on the correlation between the own phase and the phase of the opponent.

The memories D 46 and 47 store a phase transition management table 400 shown in FIG. 10 for determining the next phase. In this table 400, one's own phase is set as a row 401, and an opponent's phase 403 is arranged in each row, a row of the corresponding one's own phase is checked, and if there is a corresponding opponent's phase, the next phase 402 of the column
Has the structure that can be taken out as the next phase to be transitioned.

The memories P 44 and 45 store an overall control program shown in FIG. 11 and start execution when the power is turned on. That is, when the power is turned on (500), the process is started (501), first, an initialization process is performed (502), the entire initialization is performed, and then a phase transition check process is performed (503). The phase to be changed next is taken out from the phase of the opponent and the phase of the opponent, and the corresponding phase 504 of the single operation processing phase 504, the active processing phase 505, the standby processing phase 506, and the reference standby processing phase 507.
Execution can be shifted to the routine 507. When a new phase is entered, a predetermined program execution process is executed (508), and a next phase transition check process is executed (509), so that a phase to be shifted next can be taken out. Execute the program execution process (50
8) At this time, when an abnormality is detected, a down process is performed (510).

The phase transition check processing (600)
As shown in FIG. 12, first, the own phase is output to the partner controller 608 (601), and then the phase of the partner controller 608 is read (602). Then, based on the phase transition management table (200 in FIG. 2), the next phase to be transitioned is extracted (603). This phase is compared with the current one's own phase (604). If the phases are the same, it is determined that there is no transition, and a return without transition (606) is made. If they are different, a return with transition is made (605).

Next, the operation of the redundant apparatus for a programmable controller configured as described above will be described. Now, in FIG. 11, the power is turned on (500, 5
01), an initialization process is first executed according to the overall control program (502), and the controller 4 shown in FIG.
If 0 and 41 are normal, the processors 42 and 43 connect the status / command input / output ports 48 and 49 and the reset signal lines 60 and 61 to the data bus interfaces 50 and 51.
Of the data bus interface 50, 51 is set to the transmission / reception mode. Then, as a result of executing the phase transition check processing by turning on the power of the own phase (503), the next phase to be transited is taken out and the processing of the corresponding phase is performed (504 to 507). At this time, the phase transition check processing 503 checks the power-on row of the phase transition management table 400 shown in FIG. 10, and sets the next phase to be semi-standby. When the quasi-standby phase process 507 is entered, the phase transition check process 503 is performed again to take out the next phase. At this time, if the opponent's phase is power-off, the single operation processing phase 504 is performed.
If it is in operation, the standby process phase 506 is taken out and the next phase process is executed. Otherwise, the quasi-standby processing phase is taken out and the quasi-standby phase processing 507 is executed again. When the single operation process 504 and the active process 505 are executed, the program execution process 508 is executed, and the program execution process 71 shown in FIG.

Here, assuming that the controller 40 is the active side and the controller 41 is the standby side, the processor 42 of the active side controller 40 executes the program execution processing 71 shown in FIG. Execute repeatedly. Among them, the batch input / output processing 72
Is executed, I / O data is input from the I / O unit 56, written to the collective input / output memory 461 included in the memory D 46, and the operation result of the previous cycle of the collective input / output memory 461 is supplied to the I / O unit 56. Output. Next, a plant control program, which is a user application, is executed (73), a calculation is performed based on the I / O data in the batch input / output memory 461 and the data in the data memory 462 in the memory D 46, and the result is batch input / output. Write to the memory 461 and the data memory 462.

Next, a tracking process 80 shown in FIG. 5 is executed, and first, the reception completion signal 9
0 is input via the status bus 62 to check whether the previous reception has been completed (81) and wait until the reception is completed. Upon completion, the data is read from the data memory 462 and the batch input / output memory 461 in the tracking data transmission processing 82, and transmitted to the buffer memory 53 of the standby controller 41 as tracking data. When the transmission is completed, a tracking transmission completion notification process 83 notifies the standby controller 41 of a transmission completion interrupt signal 91 via the command bus 63, and starts the tracking data reception process 89 of the standby controller 41.

In the standby processor 43, the tracking data reception processing 100 shown in FIG. 6 is started and executed by the transmission completion interrupt signal 109 of the active controller 40. First, a tracking data reading process 101 is executed to read the tracking data transmitted to the buffer memory 52 and take it into the memory D 47 including the batch input / output memory 471 and the data memory 472. When the loading is completed, a reception completion signal 108 is notified to the operating controller 40 through the status bus 62. The operating-side controller 40 executes a phase transition check process 75 shown in FIG. 4, takes out the next phase, continues the process if it is the same as the current one, and shifts to the relevant phase process if it is different.

In the above-described embodiment, an example has been described in which the controller 40 is set as the active side and the controller 41 is set as the standby side. However, the reverse operation is the same, and the description is omitted.

As described above, the controllers 40, 4
Status / command input / output ports 48 and 4 for interfacing a status bus 62 and a command bus 63 for exchanging a status signal and a command signal with each other.
9, a bus interface 50 for interfacing a data bus 64 for transmitting and receiving tracking data,
51 and buffer memories 52 and 53 for receiving tracking data are added, and the controllers 40 and 41 are connected by a status bus 62, a command bus 63, and a data bus 64, whereby a duplex system can be configured. Further, for example, if the active controller 40 has failed, the reset signal 60 is deactivated by the processor 42 so that the standby controller 40
Is cleared to zero, that is,
In the down phase, the abnormality of the operating controller 40 can be automatically detected, and at the same time, the transmission of the bus interface 50 of the data bus 64 is automatically stopped. That is, since a fail-safe function is inevitably provided, a highly reliable duplex system can be constructed. Furthermore, the operation state of the controller can be managed by phases, and the phase to be processed next can be clearly determined from the opponent's phase and your own phase using the phase transition management table, simplifying the program processing configuration Can be.

[0036]

According to the present invention, a highly reliable duplex system can be constructed without using a duplex unit, and a phase transition management table is provided for controlling the state of the controller, thereby enabling the next processing. It is possible to provide a redundant controller for a programmable controller that can simplify the program processing configuration, improves the reliability, and can easily change the backup processing by rewriting the phase transition management table according to the purpose. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a redundant device of a programmable controller according to the present invention.

FIG. 2 is a view showing a phase transition management table for explaining memories 36 and 37 in FIG. 1;

FIG. 3 is a block diagram showing a specific embodiment of the present invention.

FIG. 4 is a view showing a program execution process executed by an active controller for explaining the operation of FIG. 3;

FIG. 5 is a view showing a tracking process executed by an active controller for explaining the operation of FIG. 3;

FIG. 6 is a view showing a tracking reception process executed by a standby controller for explaining the operation of FIG. 3;

FIG. 7 is a diagram showing a monitoring process executed by a standby controller for explaining the operation of FIG. 3;

FIG. 8 is a diagram showing an equivalent circuit of the status / command input / output port of FIG. 3;

FIG. 9 is a diagram showing a state of a controller for explaining the operation of FIG. 3 in a phase transition.

FIG. 10 is a diagram showing a phase transition management table of FIG. 3;

FIG. 11 is a view for explaining the overall control program of FIG. 3;

FIG. 12 is a diagram showing a phase transition check process for explaining the operation of FIG. 3;

FIG. 13 is a block diagram showing a schematic configuration of an example of a conventional redundant device for a programmable controller.

[Explanation of symbols]

40, 41 ... programmable controller, 42, 43
... Processors, 44, 45 ... Memory P, 46,47 ... Memory D, 48,49 ... Status / command input / output ports, 50,51 ... Data bus interface, 52,5
3 buffer memory, 54, 55 I / O interface, 60, 61 reset signal line, 62 stator bus, 63 command bus, 64 data bus, 65, 66
... I / O bus.

Claims (1)

(57) [Claims] 1. The method according to claim 1, wherein:
One is in the operating state, and the other is in the standby state in preparation for the backup. The program controllers monitor each other's state, and when the operating side goes down, the standby side detects it and continues to control the operating side. and, there is to prevent the system down, and status / command bus output port to the status / command bus and interface it to detect and notify the state of the programmable controller of the other party to each other physician, the programmable controller A data bus for transferring execution result information, which is data for continuously executing control during backup, to a partner programmable controller, a data bus interface for interfacing the data bus, and receiving and transmitting the execution result information And a buffer for
In duplex device Programmer llama logic controllers with, via the status / command bus it together divide the execution status of its process controller into a plurality of phases and notifies all times the process controller of the opponent, the process controller phase and their opponent programmable controller duplexing device from the process controller of phase and phase management table for determining the phase to be transitioned to the next own process controller, comprising a was characterized by controlling the next backup operation process.