JPH05307491A - Method and device for switching multiplexing processor - Google Patents

Abstract

PURPOSE:To attain compact duplexing by incorporating a CPU with a means which judges the state of the CPU of the other party and decides that it becomes an ordinary working system. CONSTITUTION:The CPU consists of the CPU-A1 and the CPU-B1, and they are connected respectively to a transmission line 50 and a system bus 60, and usually, the CPU-A1 is the ordinary working system, and inputs data from an input/output device (I/O) 3, and executes arithmetic operation in a micro- processing unit(MPU) 4, and instructs the I/O 3 and outputs the data to the same. The CPU-B1 of a standby system is inhibited from accessing the I/O 3 since an SYSBEN signal 113 is turned OFF, and receives the data from the CPU-A1 through the transmission line 50, and executes the same arithmetic operation as the CPU-A1, and stands by. When the CPU-A1 stops, an ordinary working/standby judgement circuit 5 detects that the CPU-B1 is turned to the ordinary working system by the turning-OFF of an SYSRUN signal 101, and turns ON the SYSBEN signal 113, and the CPU-B1 starts write-in to the I/O 3.

Description

Description: TECHNICAL FIELD The present invention relates to a method and an apparatus for switching a multiplex processing apparatus in which processing apparatuses (hereinafter referred to as CPUs) are multiplexed.

[Conventional technology]

 Various methods have been devised and put to practical use in the past, in which processing devices such as digital controllers are multiplexed to avoid an uncontrolled state and improve the operating rate.

For example, as described in JP-A-53-121544, in addition to a main CPU and a backup CPU, an interrupt for a control start command is given to the main CPU and a control stop command is issued to the backup CPU. A main CPU operation command device that gives the interrupt of the main CPU, an interrupt circuit that gives the output of the failure stop detection circuit of the main computer to the backup CPU as an interrupt for the control start command, etc. are provided, and the main CPU becomes abnormal. In such a case, it is known to switch to a back-up CPU and continue control.

 Another conventional example is disclosed in Japanese Patent Laid-Open No. 59-20056. This is a method in which when a failure occurs in the active (usual) system, the standby (standby) system in the active system determines the extent of the other's failure, and the normal device becomes the active system. It is carried out by the equipment of the above and operates as a dedicated system for duplication.

 Further, as another conventional method for duplicating a CPU that shares I / O, there is JP-A-55-110352.

This is a method in which hardware that determines the control right by mutual operation signals is installed, and only the CPU that has the control right executes the output routine. No consideration was given to I / O competition between both CPUs due to signal input from I / O.

 The above-mentioned prior art does not take into consideration the failure of the intermediate hardware required for switching and the occurrence of I / O contention because both CPUs perform I / O processing. There was a problem when the control performance deteriorated due to / O competition.

 A first object of the present invention is to eliminate the CPU external switching hardware, realize compact duplication, and quickly switch to the standby system when an abnormality occurs while the regular system continues to occupy I / O. It is to provide a CPU duplication switching method that enables the above.

 In view of the above-mentioned problems, a second object of the present invention is to obtain a high operating rate with compactness, determine the state of the standby system and determine whether or not the switching operation is possible when a minor failure that allows continuous operation occurs in the regular system. An object of the present invention is to provide a deciding method and apparatus for switching a multiplexing processing device.

 A third object of the present invention is to provide a system in which the normal system and the standby system are all configured with the same hardware to ensure the ease of maintenance and which can be used by the CPU alone. ..

[Means for solving problems]

 The first purpose is to connect the SYSRUN signal indicating that it is operating as the CPU normal system to the partner CPU with the wired OR of the open collector, judge the status of the partner CPU, and select the normal system depending on the status of this signal. Incorporating a means to determine that the standby system CPU into the standby system by prohibiting access to the I / O of the standby system CPU and controlling data of the standby system by the data sent from the standby system through the transmission path. It is achieved by performing the same control.

 The second purpose is to connect the SYSBUP signal, which indicates that one of the two processing units is waiting, to both CPUs with an open collector wired OR, and this signal is output when a failure occurs. This can be achieved by activating the standby system processing device only when it is impossible to detect this signal and determining whether or not to continue operation of the regular system according to the degree of the failure.

 The third purpose is that the external circuit for switching between the two CPUs is not required, and the duplex switching can be realized only by connecting the SYSRUN signal and SYSBUP signal (only SYSRUN signal in some cases) of both CPUs. It can be achieved by configuring as possible.

 In the present invention, the SYSRUN signal is a signal indicating whether or not the partner CPU is running as a regular (master) CPU. As a result, when the CPU tries to run, the CPU can determine that the SYSRUN signal is in the standby system when it is ON and in the normal system when it is OFF. Further, since the CPU which is the standby system excludes the input / output processing with the I / O and opens the input / output gate when the SYSBEN signal is OFF, the I / O contention does not occur.

 Also, by giving control information from the standby CPU to the standby CPU via the transmission line, the standby system can stand by while performing the same operation as the standby system without using I / O. It will be possible and will not cause inconsistent changes to the outside when switching.

 The SYSBUP signal indicates that the standby processing unit is operational. When an error occurs, if the standby system processing device can operate, it switches to the standby system, but if it does not operate, it does not switch, and the normal system processing device continues or stops operating. In other words, the degree of abnormality (fault) is judged within the regular processing unit as a major fault or a minor fault. In the case of a major fault, it must be stopped, but if it is a minor fault, it can be handled within the regular system process. Therefore, the operation can be continued and the operation rate can be improved.

Furthermore, the function as an independent processing device can be exerted when there is no waiting system from the beginning.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

 FIG. 1 shows a CPU duplication system which is an embodiment of the present invention.

 In FIG. 1, the CPU comprises a CPU-A1 and a CPU-B1, which are connected to a transmission line 50 and a system bus 60, respectively. Normally, the CPU-A1 becomes a regular system, inputs data from the input / output device (I / O) 3, and performs calculations in the microprocessing unit (hereinafter referred to as MPU) 4 to I / O3. Outputs commands and data. The CPU-B1 that has become the standby system is prohibited from accessing the I / O3 (at least the write operation) because the SYSBEN signal 113 is OFF.

The CPU-B1 receives the data from the CPU-A1 via the transmission path 50, executes the same calculation as the CPU-A1, and stands by. When the CPU-A1 stops, the normal / standby determination circuit 5 detects that the SYSRUN signal 101 is turned off and the system should become the normal system, and the SYSBEN signal 113 is turned on, and the CPU-B1 makes the I / O. Start writing to.

 The SYSRUN signal 101 is a run signal or wired OR signal output from the CPU-A1 and CPU-B1 with an open collector. 40-A1, 40-B1 and 40-A2, 40-B2 are wired OR gates, respectively.

 The bus interface unit 20 is an input / output control unit for the I / O 3, and in the standby state, the SYSBEN signal 113 from the regular / standby detection circuit 5 outputs the output.

 The traffic signal 30 (A, B, N) is a traffic signal (hereinafter referred to as M / S signal) for deciding whether to become a normal system or a standby system at reset start after power-on. ..

 The signal line 102 is a signal line (referred to as a SYSBUP signal) indicating that one of the CPU-A1 and the CPU-B1 is waiting, and is a standby output from the CPU-A1 and the CPU-B1. The signal is a wired or signal.

In this embodiment, the relationship between the meaning of the signal line and the voltage level (high level is described as “H” and low level is described as “L”) is as follows.

The internal configuration of the CPU will be described below with reference to FIG.

 Inside the CPU is a microprocessor (MPU) 4, a memory (MEM) 9 and a basic part consisting of a selection circuit (SEL) 8 for selecting a data exchange destination with the MPU 4, an M / S signal 30, a SYSRUN signal 101, and a SYSBUP. Input port 6 for fetching signal 102 and SYSBEN signal 113 into MPU4, normal / standby determination circuit 5 for outputting SYSRUN signal 101, SYSBUP signal 102 and SYSBEN113, and an error flip-flop that stores that an error has occurred. A loop 117, a peripheral control unit such as a reset circuit 401 that generates a reset signal when the power is turned on, a bus interface unit 20 for exchanging data between the I / O 3 and the MPU 4 via the system bus 60, and a data exchange with another CPU. It is divided into transmission devices 7 that exchange data.

 When the RESET input 169 is input, the MPU 4 starts its operation, reads the instruction stored in the memory 9, and performs data transfer and arithmetic processing among the I / O 3, the transmission device 7, and the memory 9. The MPU 4 outputs an address signal 110, a strobe signal (STB) 111, and a read / write control signal (R / W) 112 at the time of reading an instruction and at the time of data transfer, fetches the data signal 109 at the time of reading, and at the time of writing. The data signal 109 is output. Whether or not the MPU 4 is stopped is output from the MPU 4 as a STOP / RUN signal 167. When an error is detected in MPU4, MPUERR signal 166 is output. As typical MPU error detection functions, various detection functions such as undefined instruction execution error, unimplemented address access error, and self-diagnosis error have been devised and put into practical use. The details differ depending on the type of the microprocessor, and the present invention does not depend on the detection mechanism itself, so the detailed description will be omitted.

 In some cases, obstacles are classified into major obstacles that prevent continuous operation and minor obstacles that allow continuous operation.

The classification of the serious failure and the minor failure depends on the applied system, but the failure of the transmission device 7 may be a minor failure in the sense that the MPU 4 can operate normally.

 The selection circuit (SEL) 8 receives the address signal 110, the STB signal 111, and the R / W signal 112 output from the MPU 4, inputs the input port 6, the memory 9, the transmission device 7, and the run flip-flop (RUN- FF) 505, error flip-flop 117, back-up flip-flop 301, and select signals 106, 108, 107, 105, 164 and 304 are output.

 The MEM 9 receives the selection signal 108 from the SEL 8 and outputs the data of the address indicated by the address signal 110 as the data signal 109 when the R / W signal 112 is read. Similarly, when the R / W signal 112 is write, the data of the data signal 109 is stored in the address indicated by the address signal 110.

If a memory error such as a duty error detection occurs during memory reading, MEMERR signal 165 is output.

 When the selection signal 106 is output, the input port 6 outputs the states of the M / S signal 30, SYSRUN signal 101, SYSBUP signal 102, and SYSBEN signal 113 to the data bus 109 to inform the MPU 4. The M / S signal 30 is wired so that it is output from the normal system CPU and input to the standby system CPU, so that the normal system becomes "H" and the standby system becomes "L", and the normal system when the power is turned on. / Used for standby system judgment.

Run Prefectural Pufu Rotsu flop 505 when the selection signal 105 is output, is excisional / reset according to the state of the first data bus that is output from MPU4 bits (a 2 ⁰ bits in this example). The MPU 4 sets the RUN-FF 505 when starting the execution of the application program and resets when stopping the application program due to an error or the like.

 The normal / standby selection flip-flop (hereinafter referred to as M / S-FF) 506 is set when the RUN-FF 505 is set by the AND gate 510 and the SYSRUN signal 101 is "H", and as a result, the output of the AND gate 504 is output. A certain SYSBEN signal 113 becomes "H", the transistor 502 is turned on, and the SYSRUN signal 101 becomes "L".

 When the RUN-FF 505 is reset, the M / S-FF 506 is also reset, the SYSBEN signal 113 is "L", the transistor 502 is OFF, and when the other CPU does not set the SYSRUN signal 101 to "L", the pull-up resistor 501 is reset. Accordingly, the SYSRUN signal 101 becomes "H". On the other hand, when the RUN-FF 505 is set and the partner CPU has already set the SYSRUN signal 101 to "L", the M / S-FF 506 is not set and the SYSBEN signal 113 remains "L". When the partner CPU stops from this state and the SYSRUN signal 101 becomes "H", the M / S-FF 506 is set and the SYSBEN signal 113 and the SYSRUN signal 101 become "L".

 When the SYSBEN signal 113 is "L", the output gates of the bus interface unit 20 are all open or in a 3-state state so that there is no interference with the system bus. When the SYSBEN signal 113 becomes "H", the output gate of the bus interface unit 20 is enabled and the I / O 3 can be accessed via the system bus 60.

SYSBUP flip flop 301 when the selection signal 304 is output, is excisional / reset according to the state of one bit of the data bus to be output from the MPU 4 (a 2 ⁰ bits in this example). The MPU4 sets this flip-flop when its own CPU enters the standby state, and resets this flip-flop when the application program is stopped due to an error or the like and the standby system is switched to the active system.

 When the SYSBUP flip-flop 301 is set, the transistor 302 is turned on and the SYSBUP signal 102 becomes "L".

 When the SYSBUP flip-flop 301 is reset, the transistor 302 is turned off, and when the partner CPU does not set the SYSBUP signal 102 to "L", the SYSBUP signal 102 becomes "H" by the pull-up resistor 303.

 The error flip-flop 117 is reset by the RESET signal 169 input to the reset terminal (R) and set by the signal 170 input to the set terminal (S). The RESET signal 169 is an output signal of the reset circuit 401, and is generated when the power is turned on or when a reset switch (not shown) is generated. A signal 170 is an OR signal from the OR gate 115 of the MEMERR signal 165 and the MPUERR signal 166 and is generated when an error in the memory 9 or the MPU 4 is detected. Further, when the output signal 164 of the SEL8 is issued to the clock terminal (CK) of the flip-flop 117 by the data write operation from the MPU4, the state of the signal 104 is written in the flip-flop 117. With this function, the flip-flop 117 can be set and reset by a program, and it is used as an error output when the CPU detects an abnormality and the CPU detects it.

 The transmission device 7 exchanges data with another CPU via the transmission path 50.

 The duplication switching operation will be described below with reference to FIG.

 First, when the power is turned on, the CPU resets (200), takes in the M / S signal of the input port, and judges H / L (201). In case of "H", RUN-FF is set and the application program is started (203). In the case of "L", a certain delay time (202) is set to prevent both CPUs from becoming the normal system at the same time, during which the run flip-flop is set and the application program is started (203).

 At the beginning of the application program, first the input support SYSBEN signal is judged (204).

In the case of "H", the CPU becomes a normal system and RESETs SYSBUPFF301 (212), transmission signal input processing (205), I / O signal input processing (206), calculation processing (207), I / O signal output processing The control is executed in the order of (208) and the transmission signal output process (209), and the process is repeated. When "L", the CPU becomes a standby system, sets SYSBUPFF301 (211), and executes control in the order of transmission input processing (205), I / O signal input processing (206), and arithmetic processing (207). , And so on.

 As described above, the CPU that is the standby system can stand by while performing the same arithmetic processing with the same data as the normal system CPU without outputting to the I / O. If the standby CPU stops due to an error occurrence, the standby CPU learns that the SYSBEN signal at the input port has changed to "H" and determines that its own CPU should become the standby system. The transmission I / O signal output processing (208) and the transmission signal output processing (209) that have not been executed up to now are started.

 Next, the processing of the CPU when a failure occurs will be described with reference to FIG. When a failure occurs (220), first, it is determined whether the failure is a serious one or a minor one (221). If it is a minor failure, refer to the SYSBUP signal (222). If the SYSBUP signal is "H", there is no CPU to back up, so the operation is continued (223).

 If it is a serious obstacle, the RUN flip-flop 505 is reset (224), and the SYSBUP flip-flop 301 is reset (225) and stopped (226).

 In the above-described embodiment, the part including the flip-flop 506, the gates 504 and 510 is described as a hardware logic, but it is obvious that it can be realized by the program processing of the MPU4.

 As described above, the standby CPU executes the same calculation as the normal CPU based on the data from the transmission, waits, and starts the I / O output processing when the normal system is stopped. Duplex switching can be realized without any impact.

 Furthermore, according to this example, when the service system stops due to a serious failure, it automatically switches to the standby system, and when the service system has a light failure and the standby system exists, the service system closes. The standby system can be automatically switched to the standby system. If the standby system has a minor failure and there is no standby system, the standby system can continue to run without stopping, and the operating rate can be improved.

 Although the present embodiment has been described with respect to the duplicated system, it can be applied not only to the duplicated system but also to a multiple system by setting the delay 202 in FIG. 3 to a different value for each CPU.

 According to the present invention, in a CPU multiplexing system that shares I / O, by providing a signal line indicating the status of each CPU and a normal / standby selection circuit in the CPU, the CPU can be processed without adding external hardware. Can be realized.

 Although the standby CPU does not output I / O, it waits by performing the same operation using the same input data as the normal CPU, so that the normal CPU does not conflict with I / O. It is possible to occupy O, and there is an effect that CPU multiplexing can be realized without causing any change to the outside even when switching.

 Further, according to the present invention, a special device is not required outside the CPU, and by adding a small amount of hardware to each CPU, it is possible to use the redundant hardware system, the redundant storage system, and even the same hardware independently. It is possible to realize a dual CPU that is compact and has a high operating rate.

[Brief description of drawings]

 FIG. 1 is a diagram showing a CPU duplication system according to an embodiment of the present invention, FIG. 2 is a diagram showing an internal configuration of the CPU in FIG. 1, and FIGS. 3 and 4 are respectively It is a flowchart for operation | movement description of FIG. 101 ... SYSRUN signal, 102 ... SYSBUP signal, 113 ... SYSBEN signal, 505 ... Run flip-flop (RUN F / F), 301 ... SYSBUP flip-flop (SYSBUP F / F), 4 ... MPU, 6 ... input port, 9 ... memory, 20 ... bus interface.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Asahi 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory (72) Inventor Junju Saito 5 Omika-cho, Hitachi-shi, Ibaraki 2-1-1, Hitachi Ltd., Omika Plant (72) Inventor, Wataru Sasaki 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Incorporated, Hitachi Ltd., Omika Plant (72) Inventor, Akihiro Wakita Hitachi, Ibaraki Prefecture 3-2-1 Saiwaicho, Ichi, Hitachi, Ltd. (72) Inventor Shinichi Kawada 4026, Kujimachi, Hitachi, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (17)

[Claims] 1. A plurality of processing devices that share an input / output device are provided, at least one of which is a standby system, and the rest are standby systems. When the standby system stops, one standby system automatically In a method of switching a multiplexing processing device configured to switch to a normal system, a first signal line indicating that the plurality of processing devices are a normal system or a standby system, and at least one of them is a processing line. The processing device is connected by a second signal line indicating that the processing device is operating, and each processing device is connected to the second signal line when the power supply is turned on and the first signal line indicates a normal system at the time of a set start. When the first signal line indicates a standby system, a signal indicating that the second signal line is operating is output by outputting a signal indicating that the second signal line is operating. A special feature is that it detects the stoppage and operates as a standby processing device. The method of switching the multiplex processing device to be used. 2. The multiplexing switching method according to claim 1, wherein one end of the first signal line is grounded and is connected to another processing device. 3. The normal system processing device according to claim 1 stops the output of the second signal line when an abnormality occurs, and the standby system processing device stops the output of the second signal line. And a signal indicating that the signal is operating on the second signal line is output, and the switching method of the multiplexing processing device is characterized in that. 4. A method of switching a multiplexing processing device, wherein the second signal line in claim 1 is connected by a wired OR gate having an open collector gate output output from each processing device. 5. The operating system processing device according to claim 1, after confirming that no signal is output to the second signal line, confirms that the normal system processing device is operating on the second signal line. If the signal shown above is output and the signal has already been output to the second signal line, wait until the output stops, check that the output has stopped, then output the signal to the second signal line, The standby processing device outputs a signal indicating that it is operating to the second signal line after confirming that no signal is output to the second signal line after a lapse of a predetermined time, When the signal is already output to the signal line, it waits until the output stops, and after confirming that it has stopped, it outputs the signal to the second signal line. Method. 6. A first signal line indicating that the two processing units are to be a normal system or a standby system, and a second signal indicating that at least one of the processing units is operating. An input port and a power source, which are connected to the processing device, judge whether the system is a normal system or a standby system according to the state of the first signal line and detect whether or not an output is made to the second signal line. An output port that determines whether or not to output a signal to the second signal line based on the states of the first signal line and the second signal line obtained from the input port at the time of a reset start based on turning on or when an abnormality occurs Is provided, and the processing device operates as either a regular system or a standby system. 7. A switching device of a multiplexing processing device according to claim 6, wherein one end of the first signal line is grounded and connected to one processing device. 8. The switching device for a multiplexing processing device according to claim 6, wherein the second signal line is connected by a wired OR gate having an open collector gate output output from each processing device. 9. A first signal line indicating that the two processing units are a normal system or a standby system and a second signal indicating that at least one of the processing units is operating. Connected to a line, and depending on the states of the first signal line and the second signal line, when one processing device is operating as a standby system, the other becomes a standby system, and when the standby system processing device stops In a method of switching a multiplexing processing device in which a standby processing device operates, a third signal line indicating whether one of the two processing devices is in a standby state is connected to the two processing devices, and when a failure occurs, A method of switching a multiplexing processing device, comprising determining whether or not the standby processing device operates in accordance with the contents of the third signal line. 10. The method for switching a multiplexing processing device according to claim 9, wherein one end of the first signal line is grounded and connected to another processing device. 11. The second and the third aspects of the invention are set forth in claim 9.
The third signal line is the switching method of the multiplex processing device, which is connected by a wired OR gate with an open collector gate output from each processing device. 12. In claim 9, when a light failure capable of continuing operation occurs in the normal processing device, the normal processing device outputs a signal to the third signal line. If so, stop sending the output to the second and third signal lines to stop the operation, and continue the operation unless a signal is output to the third signal line. Characteristic Multiplexing device switching method. 13. A first signal line indicating that the two processing units are a normal system or a standby system and a second signal indicating that at least one of the processing units is operating. Connected to a line, and depending on the states of the first signal line and the second signal line, when one processing device is operating as a standby system, the other becomes a standby system, and when the standby system processing device stops In a switching device of a multiplexing processing device in which a standby processing device operates, a third signal line indicating whether or not one of the two processing devices is in a standby state is connected to the processing device. Is an input port that determines whether the system is a normal system or a standby system based on the state of the first signal line, and detects whether or not an output is made to the second signal line and the third signal line. The number obtained from the input port at set start or when an error occurs A first flip-flop that determines whether to output a signal to the second signal line depending on the states of the first signal line, the second signal line, and the third signal line, and is operable as a standby processing device. A switching device for a multiplexing processing device, characterized in that a second flip-flop for outputting a signal to the third signal line is provided in a state. 14. The first aspect of claim 13
One of the signal lines of is a switching device for multiplex processing equipment that is grounded and connected to other processing equipment. 15. The multiplexing processing device according to claim 13, wherein the second and third signal lines are connected by a wired OR gate having an open collector gate output from each processing device. Switching device. 16. A processing system comprising two processing units sharing an input / output device, one of which is a standby system and the other of which is a standby system. When the standby system stops, the standby system automatically switches to the standby system. In the switching device of the multiplex processing device configured as described above, two processing devices are connected by a signal line indicating whether or not they are operating as a regular system, and the processing device is A means for the self-processing unit to determine whether it should become the standby system or the standby system, and if the standby system stops due to an abnormality at the time of failure, the standby system immediately detects this and switches to the standby system. A switching device for a multiplexing processing device, characterized in that it is provided with a switching means. 17. The processing system according to claim 16, wherein the normal system processing device makes the shared I / O device accessible, and the standby system processing device prohibits access to the I / O device. Alternatively, a switching device for a multiplexing processing device, which is characterized by prohibiting at least output of access to an input / output device.