JPS6360489A - Data processor - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Branch] The present invention relates to a data processing device for tone reproduction.

[Prior Art] Conventionally, display devices such as CRTs have either displayed only binary data or only displayed multi-valued data.

When displaying only binary data, multi-value data is converted to binary data using dithering or density pattern methods, etc., and is expressed in pseudo-halftones, resulting in lower gradation and resolution, moiré, etc. However, it had the drawback of deteriorating image quality.

Furthermore, in the case of only displaying multivalued data, there are drawbacks such as it takes time and effort to convert binary data to multivalued data, and the amount of data increases enormously.

[Purpose of the present invention] When a multivalued image and a binary image are mixedly output, the multivalued image part can be reproduced with multivalued data and the binary image part can be reproduced with binary data. Images have gradation, and characters can be displayed clearly and with strong contrast.

Furthermore, by setting a multi-value data part and a binary data part, mixed reproduction of halftones, characters, etc. can be made possible with high image quality and flexibility.

Furthermore, high-quality reproduction was made possible by embedding characters in halftone images and performing logical operations on characters and background images.

[Example] Fig. 1 shows an example of the present invention, where 1 is a storage medium for multi-value data, and one pixel is represented by 4 bits (hereinafter referred to as multi-value data).
, 2 is a binary data storage medium represented by 1 pixel and 1 bit (hereinafter referred to as binary memory), 3 is a multilevel video signal that is data read out from multilevel memory 1, and 4 is a binary memory A binary video signal, which is data read from 2, 5
is a selection signal that gives an instruction to select either the multilevel video signal 3 or the binary video signal 4. 6 selects a multilevel video signal 3 and a binary video signal 4 according to the instruction of the selection signal 5.
This is a data switch that selectively switches between A D/A converter 7 converts the video signal selected by the data switch 6 from digital to analog. Reference numeral 8 denotes an amplifier that amplifies the CRT 9 so as to modulate the brightness of the video signal converted to analog. 10 is vertical synchronization to CRT,
A synchronization signal 11 provides horizontal synchronization, and a multi-value read signal 11 provides an instruction to read data from the multi-value memory 1, which also specifies the address of the memory. Reference numeral 12 is a binary read signal that gives an instruction to read data from the binary memory 2, and also specifies the address of the memory. A control circuit 13 controls writing and reading of the memories 1 and 2 and selection of the memories 1 and 2.

FIG. 2 is a diagram showing an example of displaying multivalued data 4 in a rectangular area in binary data, and FIG. 3 is a diagram showing an example of specifying the above-mentioned rectangular area.

FIG. 4 is a diagram showing an example of displaying multivalued data in a free area in binary data, and FIG. 5 is a diagram showing an example of specifying the above-mentioned free area.

The operation of this embodiment will be described using a display example as shown in FIG. In advance, WX, WY, WW in Fig. 3,
Each parameter of WH is given. Next, by outputting the multi-level read signal 11 and the binary read signal 12 in accordance with the synchronization signal 10, the multi-level video signal 3 is output from the multi-level memory 1, and the binary video signal 4 is output from the binary memory 2. .

Initially, the selection signal 5 is set to select the binary video signal 4, and when the point specified by wx and wy is reached, the selection signal 5 selects the multi-value video signal 3 by a width corresponding to W. I'll make it like that. When the above operation is performed for the line designated by WH, a display as shown in FIG. 2 is produced. In addition, it has a memory for control, and as shown in Figure 5, 0°゛ and "°1"
If the selection signal 5 is "O", the binary video signal 3 is set as the content of the control memory as the selection signal 5.
If "1" is selected, the multilevel video signal 4 is selected, and a display as shown in FIG. 4 is obtained.

The above can be similarly performed in the case of displaying binary data in multivalued data as shown in FIG.

That is, 5 in FIG. 5 is a selection signal for giving an instruction to select the type of calculation between the multi-value video signal 3 and the binary video signal 4, and 6 is a selection signal for giving an instruction to select the type of calculation between the multi-value video signal 3 and the binary video signal 4. The configuration is such that a logical operation is performed between the video signal 3 and the binary video signal 4. Other parts that are the same as the reference numerals in FIG. 1 correspond to each other.

FIGS. 7 and 8 are diagrams showing examples of how the selection signal 5 of FIG. 6 is applied. FIG. 9 is an example showing the relationship between the selection signal 5 and the type of calculation, and FIG. 10 is an example in which actual data is applied in that case. First, as shown in FIG. 7, when changing the type of calculation in a rectangular area, the parameters WX, WY, WW, and WH are set in advance. Synchronization signal 10
By outputting the multi-level read signal 11 and the binary read signal 12 in accordance with the
A binary video signal 4 is output from the value memory 2. While the selection signal 5 is 0'', the logic operation unit 6 outputs the multi-level video signal 3.
Bit-by-bit AND of the binary video signal 4 is performed, and when the selection signal 5 becomes "1", the bit-by-bit OR of the multi-value video signal 3 and the binary video signal 4 is performed. If the area division is determined as shown in FIG. 3 and the content of the control memory is the selection signal 5, then the first
Four types of calculations as shown in the table can be performed for each area. next,
The output of the logic operation unit 6 is converted into an analog video signal by a D/A converter 7, amplified by an amplifier 8, and displayed on a CRT 9. Various other calculations can be considered for the calculation shown in FIG. 9, and negative/positive conversion is easily possible by inverting a multivalued video signal.

[Effects] As described above, text and photographic images can be reproduced in high quality.

[Brief explanation of drawings]

1 and 6 are data processing block diagrams of an embodiment of the present invention, FIGS. 2 and 4 are display example diagrams, FIGS. 3 and 5 are explanatory diagrams of selection signals, and FIGS. FIG. 8 is a diagram showing how to give a selection signal specifying the type of calculation. FIG. 9 is a diagram showing an example of the relationship between selection signals and calculations, and FIG. 10 is a concrete diagram in which the above calculations are used. 1 is a multilevel memory, 2 is a binary memory, 3 is a multilevel video signal, 4 is a binary video signal, and 5 is a selection signal.

Claims (1)

[Claims] 1. An apparatus capable of reproducing images having gradations, which has separate memory for multi-value data and memory for binary data, reads data separately from each memory, and reproduces a multi-value data memory. Data processing is characterized in that the data read from the memory is made into a multi-value video signal, the data read from the binary memory is made into a binary video signal, and the logical operation of the two types of video signals is performed and output. Device. 2. A data processing device according to item 1, wherein the type of logical operation is selectively switched.