JP2670443B2 - Image information processing device - Google Patents

Description

The present invention relates to a composite image information processing device. [Prior Art and Problems to be Solved] In a conventional image information processing apparatus, for example, a processing apparatus that processes binary image information that handles a document, a character, a drawing, and the like, and a halftone image (multivalued image) such as a photograph ) There is a multi-valued image information processing device that handles information. The binary image information processing device emphasizes resolution rather than gradation expression according to the characteristics of documents, drawings, etc., and the multivalued image information processing device emphasizes gradation expression rather than resolution according to characteristics of photographs. ing. Therefore, for example, when an image in which characters and photographs are mixed is input to the conventional image information processing apparatus, the binary image information processing apparatus has a difficulty in expressing gradation of the photograph portion, and the multi-valued image information processing apparatus However, there is a problem in detail expression of the character part. In addition, multi-valued image information can be converted into 2 by dither method, density pattern method,
It may be replaced with value image information and expressed in pseudo halftone, but there is a limit, and similarly, there is a drawback that image quality is deteriorated due to deterioration in gradation and resolution, moire, and the like. Further, there is a method in which the character portion and the halftone portion of the document information are identified and only the halftone portion is expressed by a pseudo halftone such as a dither, but there is a drawback that the gradation and resolution are deteriorated. [Object, Solving Means, and Action] An object of the present invention is an image information processing apparatus that eliminates the above drawbacks. That is, the image information processing apparatus of the present invention includes a multi-valued memory that stores multi-valued data, a binary memory that stores binary data, and a control corresponding to each pixel of the binary data and the multi-valued data. A control memory that stores data in association with a two-dimensional area where the binary data and the multivalued data are output, a multivalued data stored in the multivalued memory, and a binary memory Control means for controlling the reading of binary data, and multi-valued data and binary data read by the control of the control means are logically combined and controlled based on the control data stored in the control memory. The synthesizing means and the output means for outputting the data synthesized by the synthesizing means. As a result, it is possible to perform display and printing with high resolution and high gradation in which multivalued images are mixed in an arbitrary area. [Embodiment] FIG. 1 shows an example of a CRT display device in which binary image information such as characters and figures and multivalued image information such as photographs are mixedly displayed, and a mixed area of multivalued image information is arbitrarily set. To do. Reference numeral 1 denotes a multi-value data storage medium for displaying multi-value image information, which is indicated by 4 bits per pixel (hereinafter referred to as multi-value memory). 2 denotes storage of binary data for displaying binary image information. In the medium, one pixel represents one bit (hereinafter referred to as a binary memory), 3 is a multi-valued video signal which is data read from the multi-valued memory 1, and 4 is data read from the binary memory 2. Certain binary video signal, 5 is multi-level video signal 3
Is a selection signal that gives an instruction to select one of the binary video signal 4 and the binary video signal 4. A data switch 6 selectively switches between the multi-value video signal 3 and the binary video signal 4 in response to an instruction from the selection signal 5. A D / A converter 7 converts the video signal selected by the data switcher 6 from digital to analog. Reference numeral 8 is an amplifier that amplifies the CRT 9 so as to perform brightness modulation by the video signal converted into analog.
10 is a sync signal that gives vertical and horizontal syncs to the CRT, 11
Also addresses the memory with a multi-valued read signal that gives an instruction to read data from the multi-valued memory 1. 12 is 2
Gives an instruction to read data from the value memory 2
The value read signal also addresses the memory.
Reference numeral 13 is a control circuit for controlling writing and reading of the memories 1 and 2 and selection of the memories 1 and 2. FIG. 2-1 is a diagram showing an example of displaying multi-valued data in a rectangular area in binary data, and FIG. 2-2 is a diagram showing an example of address control for designating the rectangular area. . FIG. 4 is a diagram showing an example of displaying multi-valued data in binary data in a free area, and FIG. 5 is a diagram showing an example of a control memory for designating the free area. The operation of this embodiment will be described with respect to the display example shown in FIG. In advance, WX, WY, W in Fig. 2-2
Each parameter of W and WH is given. Next, by outputting the multi-valued read signal 11 and the binary read signal 12 in synchronization with the synchronization signal 10,
The multi-valued memory 1 outputs a multi-valued video signal 3, and the binary memory 2 outputs a binary video signal 4. First, the selection signal 5 is set to select the binary video signal 4, and when the point designated by WX, WY is reached, the selection signal 5 selects the multi-valued video signal 3 by the width corresponding to WW. To If the above operation is performed for the line specified by WH,
The display as shown in FIG. 2-1 is performed. This point will be explained easily with the circuit of FIG. 3-1 and the time chart of FIG. 3-2. In FIG. 3A, an X counter and a W counter are pixel clocks, that is, counters for counting dots. The former is for obtaining a point WX, and the latter is for obtaining a point WX + WW. Y counter and H counter are horizontal sync signals,
HSYNC, a counter that counts lines, the former is WY
The latter is for obtaining the point of WY + WH.
Each counter is preset with WX, WW, WY, and WH parameters. The location where the multi-valued image is mixed can be changed in the X and Y directions according to the numerical value of the parameter. A circuit for determining the selection signal 5 by these counters and their outputs is included in the control circuit 13. Now, reading is started from the addresses of the memories 1 and 2 corresponding to the point 0 in FIG. 2-2. It is also assumed that 0 point is the reference point for starting display and corresponds to VSYNC. The X counter starts counting the pixel clock by the input of HSYNC, and sets the flip-flop FF _{2 when} counting WX. With WX count, start counting W counter, and W counter is WW
When it counts, FF ₂ is reset. Thus 3rd
As shown in the figure, the selection signal 5 ″ in the H direction is obtained by the output of FF _2. However, since the display has not reached WY in the vertical (V) direction, the memory read selection is not performed yet. The count of the Y counter is counted by VSYNC. Line scanning progresses, HS
If the Y counter counts only WY for YNC, Flip Flow FF ₁
Set. Then, the counting of the H counter is started. When the H counter counts only WH, FF ₁ is reset. As a result from FF ₁ is V direction selection signal 5 'is obtained. "The the selection signal 5 for the data switcher 6 (the output of the gate G _1). The signal 5 is" H direction selection signal 5 periods are out of the V-direction selection signal 5 'binary video signal when the 1 " A multi-valued video signal is reproduced and output in place of 4. The selection signal 5 in the screen changes to the first "1" (third-third).
Multi-value read signal 11 only in response to WX ₁ ) in Fig. 2
Can be output to start the read address of the multi-valued memory 1. By doing so, it is possible to display or print a specific halftone image to be reproduced at an arbitrary place. In this case, the control circuit 13 outputs the address data from the address 0 of the multi-valued memory 1 to the memory 1 for the first time in terms of WX and WY in FIG. If the sizes of the parameters WW and WH are made to correspond to the size of the multilevel memory 1, the capacity of the memory 1 can be reduced (Fig. 3-3). It is convenient to put a photo of your face. In this case, by shifting the read line of the memory 1 in the Y direction in synchronization with each time the selection signal 5 changes to "1" for each line, the halftone information by the multivalued data of the memory 1 is transferred to WW and WH. Can be fitted. It also has a memory for control, and as shown in Fig. 5, "0"
The area is defined by "1" and "1", and the content of the control memory is used as the selection signal 5. When the selection signal 5 is "0", the binary video signal 3 is selected, and when it is "1", the multilevel video signal 4 is selected. If selected, a display as shown in FIG. 4 can be obtained. The method using the control memory will be described later as an image area memory. The above can be similarly performed in the case of displaying binary data in multi-valued data as shown in FIG. That is, reference numeral 5 in FIG. 6 denotes a selection signal for giving an instruction to select the type of operation of the multi-valued video signal 3 and the binary video signal 4, and 6 denotes the multi-valued video signal 3 according to the instruction of the selection signal 5. And a binary video signal 4 are logically operated. Others correspond to those having the same reference numerals in FIG. FIG. 7 and FIG. 8 are diagrams showing an example of how to give the selection signal 5 of FIG. FIG. 9 is an example showing the relationship between the selection signal 5 and the type of calculation, and FIG. 10 is an example in which actual data is applied in that case. First, as shown in FIG. 7, when changing the type of calculation in a rectangular area, the parameters WX, WY, WW, and WH are set in advance. If the multi-valued read signal 11 and the binary read-out signal 12 are output in accordance with the synchronization signal 10, the multi-valued memory 1 outputs the multi-valued video signal 3 and the binary memory 2 outputs the binary video signal 4. While the selection signal 5 is "0", the logical operation unit 6 performs AND of each bit of the multi-valued video signal 3 and the binary video signal 4, and when the selection signal 5 becomes "1", the multi-valued video signal For each bit of 3 and binary video signal 4
OR is performed. Further, if area division is defined in the control memory as shown in FIG. 8 and the content of the control memory is the selection signal 5, four kinds of calculations as shown in FIG. 9 can be performed for each area. . Next, the output of the logical operation unit 6 is set to D /
It is converted into an analog video signal by the A converter 7, amplified by the amplifier 8, and displayed on the CRT 9. The calculation shown in FIG. 9 can be variously considered, and if only one of the multi-valued video signal 3 and the two-valued video signal 4 is prioritized, the multi-valued and binary values can be switched as described above. By reversing the bits, negative / positive conversion can be easily performed. In addition, connect a laser beam printer instead of CRT9,
The amplifier 8 modulates the brightness of the beam or the lighting width of the beam to form a multivalued latent image on the photoconductor, develops it, and transfers it to a cut sheet of one page to form a print image. In this case, the signal generated by beam detection at each beam scan is
Set to YNC and output data for each line. The output start signal for one page of cut paper is VSYNC. [Effects of the Invention] According to the present invention, a region for combining multi-valued data and binary data can be set to an arbitrary shape, so that a combining process of multi-valued data and binary data can be performed according to a user's request. Can be done in various ways and freely.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 6 are data processing block diagrams of an embodiment of the present invention, FIGS. 2-1 and 4 are display example diagrams, FIGS. 2-2 and 5
FIG. 3 is an explanatory view of a selection signal, FIG. 3-1 is a selection control circuit, FIG. 3-2 is a time chart of FIG. 3-1, FIG. 3-3 is a schematic diagram of the memory 1, FIGS. The figure shows how to give a selection signal for specifying the type of operation. FIG. 9 is a diagram showing an example of the relationship between the selection signal and the calculation, and FIG. 10 is a concrete diagram to which the calculation is applied.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Shigeki Miura               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc.                (56) References JP-A-61-139161 (JP, A)                 JP-A-60-19358 (JP, A)                 JP-A-61-98065 (JP, A)

Claims (1)

(57) [Claims] A multi-valued memory for storing multi-valued data, a binary memory for storing binary data, control data corresponding to each pixel of the binary data and the multi-valued data, the binary data and the multi-valued data. A control memory that stores the data and the two-dimensional area corresponding to the output, and a control that controls reading of the multivalued data stored in the multivalued memory and the binary data stored in the binary memory Means, a synthesizing means for synthesizing the multi-valued data and the binary data read under the control of the control means by performing logic synthesis control based on the control data stored in the control memory, and the synthesizing means. An image information processing apparatus, comprising: an output unit that outputs output data. 2. The image information processing apparatus according to claim 1, wherein the control data is a value indicating a logical sum or a logical product of binary data and multi-valued data.