JPS6334369Y2 - - Google Patents

Description

[Detailed Description of the Invention] Some television receivers are designed so that when the channel is switched, the channel number 2 is displayed on the television screen 1 together with the image for a certain period of time, as shown in FIG.

In this case, the signal displayed as channel number 2 is generated by a character generator, but if the size of channel number 2 is, for example, 64 dots (horizontal) x 32 dots (vertical), then number 2 Since each character requires 256 bytes (=64 x 32/8), 10 characters from "0" to "9" require 2560 bytes of ROM as a character generator. But in reality, something like this
Since there is no ROM, it ends up being 4KB (4096 bytes).
ROM is required, but with such a large capacity
ROM is expensive.

Furthermore, if the capacity of the ROM is made smaller, the price will be reduced, but then the displayed channel number 2 will become smaller and the shape of the characters will become unnatural, making it difficult to see.

Furthermore, as shown in Figure 1, the channel number 2
When displayed, this hides the broadcast image and is a nuisance.

This idea attempts to eliminate these problems.

Therefore, in this invention, when the channel number 2 is displayed, for example, as shown in FIG. 2, it is displayed in the form of a slit.

An example of this will be explained below. In addition, in this example, the channel number 2 is two digits,
Each digit is represented by 64 dots in the horizontal direction and 16 dots in the vertical direction, and at this time, as shown in Figure 3 (in Figure 3, 3 is the displayed dot,
Solid lines indicate lines for odd fields, dashed lines indicate lines for even fields), 1 for each field.
There are slits on every other line, so the vertical direction is 62
This is the case when the line is a display section.

In FIG. 4, 11 is an electronically tuned tuner, 18 is a tuning control circuit, and the resonant circuit of the tuner 11 is constituted by, for example, a variable capacitance diode. Ec is supplied and a desired channel is selected.

Then, the video intermediate frequency signal of the selected channel is taken out from the tuner 11, this signal is supplied to the video detection circuit 13 through the video intermediate frequency amplifier 12, and a luminance signal is taken out, and this signal is sent through the video amplifier 14. It is supplied to the picture tube 15. Further, at this time, horizontal and vertical deflection currents are supplied from the deflection circuit 16 to the deflection coil 17.

Further, a channel data signal Sc corresponding to the channel selection voltage Ec, that is, indicating the channel currently being received, is extracted from the control circuit 18, and
When switching channels, a pulse Pc indicating that the channel has been switched is taken out.

In addition, 21 indicates a character generator,
This is composed of a ROM with a capacity of 2KB, for example, and has channel numbers 2 from "0" to "9".
Pattern data Dp is written.
In other words, the pattern data Dp is 128 bytes per channel number 2 (lower address is A ₀
-A ₆ ) are used. Therefore, by specifying the upper addresses A ₇ -A ₁₀ , the start address of the pattern data Dp for each channel number 2 is selected. Also, lower address A ₀
~ _A6 , as schematically shown in FIG. 5, each address corresponds to the channel number 2 in the vertical direction, and every 16 addresses corresponds to the channel number 2 in the horizontal direction. And 128
= 16 x 8, so 8th address will be allocated in the horizontal direction, and the overall horizontal direction will be
It becomes 64 bit.

Therefore, among the lower addresses _A0 to _A6 of the character generator 21, addresses _A0 to _A3 are set to "1".
By incrementing the address of the character generator 21 in the vertical direction, the address
By incrementing A ₄ to _{A 6} by "1", the address of the character generator 21 changes in the horizontal direction.

Furthermore, 22 is a 4-bit latch, 23 is an octal counter, and 24 is a hexadecimal counter.
The outputs of counter 23 are supplied to addresses A ₇ to _{A 10} of character generator 21, the outputs of counter 23 are supplied to addresses A ₄ to _{A 6} of character generator 21, and the outputs of counter 22 are supplied to addresses A 4 to A 6 of character generator ₂₁ . _Q4
is the address A ₀ of the character generator 21
_A3 is supplied. Therefore, if the output of the latch 22 is changed by 1, the address of the character generator 21 changes by 128 addresses, so the pattern data for channel number 2 is changed.
Dp can be changed. Also, latch 22
If the output of the counter 23 is incremented by "1" while _the output _of By incrementing the output bits by "2", that is, by incrementing the output bits _Q1 to _Q4 by "1", it is possible to sequentially obtain data in the vertical direction regarding the pattern data Dp.

Further, 25 indicates a microcomputer, which has, for example, a 4-bit parallel processing CPU, a ROM in which a program for displaying channel numbers is written, a RAM for a work area, and ports for input/output. It is a so-called 1-chip microcomputer. And this microcomputer 25
are supplied with signals Sc and Pc from the control circuit 18, as well as horizontal synchronization pulse Ph and vertical synchronization pulse Pv from the deflection circuit 16, and signals ADC and ADD that address the character generator 21 based on the signal Sc. is formed. This signal ADC is a 4-bit signal that specifies addresses A ₇ to A ₁₀ of the character generator 21 through the latch 22, that is, specifies pattern data Dp every 128 bytes. This is a 3-bit signal that specifies addresses A ₄ to _{A 6} of the character generator 21 through the counter 23, that is, specifies the horizontal address of channel number 2.

Then, when these address signals ADC and ADD are formed and output, a flag pulse indicating this is generated.
Pf is also output.

Further, in the microcomputer 25, when the pulse Pc is supplied, a display permission signal Pd which becomes "1" only during the period when the channel number 2 is displayed is generated.

Furthermore, in the microcomputer 25, the synchronization pulse
Based on Pv and Ph, as shown in FIG. 2, a signal Sv that becomes "1" is generated during the vertical display period Tv of channel number 2, and "1" during the horizontal display period Th of channel number 2. Signal Sh that becomes 1”
is formed. Therefore, the period Th in the period Tv
Then, Sv="1", Sh="1", and channel number 9 is displayed.

The pulse Pr is also taken out from the microcomputer 25. This pulse Pr is obtained when Tv=“1”, and this pulse Pr is supplied to the counter 24 as a reset pulse, and the horizontal synchronizing pulse Ph is supplied as a count input. Therefore, for each field period,
When the period Tv is reached, the count value Q ₀ of the counter 24
~Q ₄ changes from “all 0” to “1” for each horizontal scan
At this time, the output Q ₁ ~
_Q4 is incremented by "1" every two horizontal periods, and the output _Q0 is alternately inverted between "0" and "1" every horizontal period.

Further, 26 is an 8-bit parallel input/serial output shift register, 31 is a monostable multivibrator that specifies the starting point of the horizontal display position of channel number 2, and 34 is a start/stop oscillation circuit. Oscillation is started when triggered by the output of the vibrator 31, and 128 synchronous dot clocks DCK corresponding to the horizontal dots of channel number 2 are formed. Furthermore, 35 is an octal counter, and 36 is a 9-digit counter.

According to such a configuration, the multivibrator 3 is activated by the horizontal synchronizing pulse Ph from the deflection circuit 16.
1 is triggered, a pulse Pt synchronized with the pulse Ph is taken out as shown in FIGS. 6A and 6B, and this pulse Pt is supplied to the oscillation circuit 34 for a period t ₄ as shown in FIG. 6C. 128 dot clocks DCK are formed at ~t ₆ . The period t ₄ to _{t 6} corresponds to the horizontal display period Th, and the first 64 clock DCKs correspond to the 10th position of channel number 2, and the latter 64 correspond to the 1st position of channel number 2. do.

This clock DCK is supplied to the counter 35 as a count input, and the horizontal synchronizing pulse Ph is supplied to the counter 35 as a load pulse, and the counter 35 is preset to "all 1" for each pulse Ph. Therefore, as shown in FIG. 6D, the counter 35 outputs a pulse DCK.
A carrier output Pa is obtained every 8 pulses DCK from the start time _t4 .

This pulse Pa is supplied to the counter 36 as a count input, and the horizontal synchronization pulse Ph is supplied to the counter 36 as a reset input. Therefore, the counter 36 obtains a carry output Ps at time _t5 of the ninth pulse Pa, that is, the first pulse in the latter half of the pulse DCK, as shown in FIG. 6E.

(i) Then, when the channel is switched at any time, the channel selection voltage Ec changes, the desired channel is received, and its image is displayed on the picture tube 15.

(ii) Then, at the start of the display period Tv,
A pulse Pr is formed based on the pulse Pc, and the counter 24 becomes "all 0" due to this pulse Pr.
will be reset to Therefore, the lower addresses _A3 to _A0 of the character generator 21 are "all 0".

(iii) Furthermore, in the first horizontal scanning period of the display period Tv, signals ADC and ADD indicating the 10th position of channel number 2 are formed at time t ₁ based on the signal Sc shown in FIG. 6F. is supplied to the latch 22 and the counter 23, and a flag pulse Pf is formed at time _t2 as shown in FIG.
This is supplied as a load pulse to the latch 22 and counter 23 through the OR circuit 37, and the signals ADC and ADD are supplied to the latch 22 and counter 23.
loaded into.

Therefore, the character generator 21 receives the channel number 2 by the outputs of the circuits 22 to 24.
This means that the start address of the pattern data Dp indicating the 10th place has been specified.

(iv) Subsequently, when the horizontal display period Th begins at time _t4 , the dot clock DCK and the pulses Pa and Ps are activated by the pulse Pt as shown in FIG. 6 C to E.
is obtained. And pulse Pa is counter 2
3 as a count input, so
The address of the character generator 21 increases by 16 addresses from the first address specified in item (iii) for each pulse Pa, that is, from the fifth
The first row of the diagram increases horizontally. Therefore, the pattern data Dp of the first row is sequentially read out from the character generator 21 in 8 bits (1 byte) for each pulse Pa.

(v) This read pattern data Dp is loaded in parallel into the shift register 26 by the pulse Pa, and taken out in series by the dot clock DCK, so that the pattern data Dp is loaded from the register 26 in one bit per dot clock DCK. obtained in sequence.

(vi) At this time, the counter 24 is "all 0" and Q ₀ = "0", so the inverter 27
The output of is "1". Further, the signal Pd is "1" during a predetermined period after the channel is switched, and the signals Sv and Sh are during the display period Tv and Th.
is “1”.

Therefore, the pattern data from register 26
Dp is supplied to the video amplifier 14 through the AND circuit 28 and further through the AND circuit 29, and is mixed into the luminance signal. Therefore, during the period _t4 to _t5 , the first line of the 10th channel number 2 is displayed on screen 1, superimposed on the broadcast image.

(vii) On the other hand, when the signals ADC and ADD at the 10th position of channel number 2 are loaded into the latch 22 and the counter 23 by the pulse Pf at time t ₂ , the microcomputer 2
5, address calculation for the first pattern data Dp of channel number 2 is immediately started based on signal Sc, and _as shown in FIG.
Start address of the first pattern data Dp of
ADC and ADD are output.

(viii) Then, at time t ₅ , channel number 2
At this time, the pulse Ps is supplied as a load pulse to the latch 22 and counter 23 through the OR circuit 37, so the display of the channel number 2 formed in section (vii) is completed. The first address signals ADC and ADD are loaded into the latch 22 and counter 23.

Therefore, after time t ₅ , the same operations as in (iv) and (v) are performed, and during the period t ₅ to _{t 6} , the first line of channel number 2 in the 1st position is displayed as a broadcast image on screen 1. displayed in an overlapping manner. In addition, after time t ₆ , Sh="0"
It is.

(ix) Next, in the second horizontal scanning period of the display period Tv, the operations in sections (iii) to (viii) are repeated.

However, in this case, the counter 24 is counting the horizontal synchronizing pulse Ph, but the counter 24 is counting the horizontal synchronizing pulse Ph.
Since the outputs Q ₁ to _{Q 4} of 4 are incremented by "1" every two horizontal periods, even in this second horizontal scanning period, the outputs from the character generator 21 are different from those in the first horizontal scanning period. The same pattern data Dp is obtained and the register 26
supplied to

However, at this time, the output Q ₀ of the counter 24
Since is "1", the pattern data Dp from the register 26 is blocked in the AND circuit 28 and is not mixed into the luminance signal.

Therefore, channel number 2 is not displayed during the second horizontal scanning period.

(x) Subsequently, in the third horizontal scanning period of the display period Tv, the operations (iii) to (viii) are repeated.

In this case, the counter 24 counts the horizontal synchronizing pulse Ph, and the outputs Q ₁ to _{Q 4} are incremented by "1", and Q ₀ = "0".
Therefore, the character generator 21 is addressed in the second row of FIG. Therefore, the third
In the th horizontal scanning period, the second line of channel number 2 is displayed.

() Thereafter, the above-described operation is repeated, and channel number 2 is displayed every other horizontal period.

Then, when the bottom line of channel number 2 is displayed, the microcomputer 21 sends the signal ADC,
ADD is no longer output and Sv="0"
become.

() The above operation is repeated for each field period. Then, when a predetermined time has elapsed after switching the channel, Pd becomes "0" and the channel number 2 is no longer displayed. Note that after this point, signals ADC, ADD, etc. are not output.

Thus, according to this invention, when switching channels, channel number 2 is displayed on screen 1, but in this case, especially according to this invention, channel number 2 is displayed in a slit shape, and the number Even if 2 is increased or the number of dots is increased to make the character shape more natural, the capacity of the character generator 21 can be made smaller, for example, 2 KB as mentioned above, and the cost can be reduced. Moreover, in the conventional display circuit, it can be realized by simply increasing the counter 24 by one bit, and from this point of view as well, it is inexpensive.

Furthermore, since the channel number 2 is displayed in a slit shape, it is less likely to interfere with the broadcast image.

In the above description, in order to suppress the display to zero when the channel number 2 is one digit, space pattern data may be prepared in the character generator 21 and read out. Furthermore, in the above description, the position of the dot 3 can be changed between odd and even fields. Further, the channel number 2 may be displayed every even number line. moreover,
It can also display digital information such as the time.

[Brief explanation of the drawing]

1 to 3, 5, and 6 are diagrams for explaining this invention, and FIG. 4 is a system connection diagram of an example of this invention. 21 is a character generator, and 25 is a microcomputer.

Claims (1)

[Claims for Utility Model Registration] Pattern data is extracted from a character generator, this pattern data is mixed with a luminance signal, and the mixture is superimposed on the image based on the luminance signal on the screen of a picture tube to display channel numbers, etc. based on the pattern data. In the television receiver configured to display the image, a gate circuit is provided in the signal line for the pattern data between the character generator and the picture tube, and the character generator is controlled by n times the horizontal scanning period (n is an integer of 2 or more), and a control signal that changes at n times the horizontal scanning period is supplied to the gate circuit to display the channel number etc. in a slit shape. TV receiver.