JPS63293861A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63293861A JPS63293861A JP13011487A JP13011487A JPS63293861A JP S63293861 A JPS63293861 A JP S63293861A JP 13011487 A JP13011487 A JP 13011487A JP 13011487 A JP13011487 A JP 13011487A JP S63293861 A JPS63293861 A JP S63293861A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum
- silicon oxide
- passive state
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002253 acid Substances 0.000 claims abstract description 6
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 abstract description 29
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 18
- 239000011229 interlayer Substances 0.000 abstract description 9
- 238000005260 corrosion Methods 0.000 abstract description 7
- 230000007797 corrosion Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 2
- 238000004381 surface treatment Methods 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 2
- 238000007598 dipping method Methods 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 238000006467 substitution reaction Methods 0.000 abstract 1
- 239000003518 caustics Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体素子
上の金属配線の表面処理方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for surface treatment of metal wiring on a semiconductor element.
従来、半導体素子表面に金属、主にアルミニウムを用い
て配線を形成するが、アルミニウムはその表面上に微量
に残った腐食性の物質によって腐食しやすい。この腐食
を抑える方法としてはアルミニウムの配線が完了した後
に水又は適切な溶媒で充分に洗浄を行なうとか、あるい
は適切なガス中で加熱処理するとか、あるいはＲＦ放電
によるガスプラズマ処理をして、腐食性物質を除去する
ことがなされていた。Conventionally, wiring is formed using metal, mainly aluminum, on the surface of a semiconductor element, but aluminum is easily corroded by trace amounts of corrosive substances remaining on the surface. Methods to suppress this corrosion include thorough cleaning with water or an appropriate solvent after aluminum wiring is completed, heat treatment in an appropriate gas, or gas plasma treatment using RF discharge to prevent corrosion. It was done to remove sexual substances.
上述したような腐食を防ぐ方法は積極的に金属の表面状
態を耐腐食性に変化させるものではないため、処理が不
充分であった場合や、充分であっても経時変化に伴う金
属表面の周囲の雰囲気の変化により、腐食性物質の再付
着が起り金属の腐食が発生するという欠点がありた。The above-mentioned methods of preventing corrosion do not actively change the surface condition of the metal to make it corrosion resistant. There was a drawback that corrosive substances redeposited due to changes in the surrounding atmosphere, resulting in metal corrosion.
本発明の半導体装置の製造方法は金属配線が形成された
半導体基板を酸化力のある酸に浸漬し金属配線表面に不
動態膜を形成する工程を有している。The method for manufacturing a semiconductor device of the present invention includes the step of immersing a semiconductor substrate on which metal wiring is formed in an oxidizing acid to form a passive film on the surface of the metal wiring.
第１図は本発明の一実施例の工程順を断面図で示した。 FIG. 1 is a sectional view showing the process order of an embodiment of the present invention.
第１図の（ａ）は金属配線形成直後の断面図であり、硅
素基板１上に形成された酸化硅素膜２の上に厚さ２μｍ
のアルミニウム膜３を堆積し、フォトレジストによりバ
ターニングを行い。エツチングを施した後フォトレジス
トを除去した所であシ、アルミニウム３表面に腐食性の
特質４（ＯＨ″″、Ｃｔ−等）が付着している状態を示
している。次に第１図の（ｂ）に示したようにアルミニ
ウム３を酸化力のある硝酸を主成分とする酸に浸漬する
ことにより表面処理を施し、アルミニウム３表面に付着
した腐蝕性の物質４を置換除去し、アルミニウム３表面
を不動態５の膜を形成する。アルミニウム３は表面近傍
のみ不動態化し内部状態は変わらない。FIG. 1(a) is a cross-sectional view immediately after metal wiring is formed, and a silicon oxide film 2 with a thickness of 2 μm is formed on a silicon substrate 1.
An aluminum film 3 is deposited, and patterning is performed using photoresist. After etching and removing the photoresist, it is shown that corrosive properties 4 (OH'''', Ct-, etc.) are attached to the surface of the aluminum 3. Next, as shown in FIG. 1(b), the aluminum 3 is surface-treated by immersing it in an acid whose main component is nitric acid, which has oxidizing power, to remove corrosive substances 4 that have adhered to the surface of the aluminum 3. The aluminum 3 is replaced and removed to form a passive state 5 film on the surface of the aluminum 3. Aluminum 3 is passivated only near the surface, and the internal state remains unchanged.
次に第１図の（Ｃ）に示すように配線の上から保護膜と
して酸化硅素膜６を２μｍ堆積させる。次に第１図の（
ｄ）に示すように酸化硅素膜６上に７オトレジストを塗
布し、電極端子に用いるべき部分をバターニングしてア
ルゴンのスパッタエッチにて酸化硅素膜６とアルミニウ
ム３表面の不動態とをエツチング除去して電極開口部７
を形成して電極として用いられるようにする。Next, as shown in FIG. 1C, a silicon oxide film 6 with a thickness of 2 μm is deposited as a protective film over the wiring. Next, in Figure 1 (
As shown in d), 7 photoresist is applied on the silicon oxide film 6, the part to be used as the electrode terminal is patterned, and the silicon oxide film 6 and the passive state on the surface of the aluminum 3 are etched away by argon sputter etching. and electrode opening 7
is formed so that it can be used as an electrode.
第２図は本発明を多層配線へ応用した例の断面図である
。半導体基板１上の酸化硅素膜２上に第１配線アルミニ
ウム８を２μｍ堆積し、不′４ｈ態５を前記の方法によ
り形成後第２層間膜として酸化硅素膜９を０．４μｍ堆
積する。その後第１配線アルミニウムと第２配線アルミ
ニウムの間の電界をシールドすることと、第２配線アル
ミニウムのカバレッジ向上を目的とした平坦化のための
絶縁膜の絶縁膜の酸化硅素膜１４のエツチングのストッ
パーとすることとを目的として層間アルミニウム１０を
０．１μｍ堆積しバターニングを行なった後前記の方法
で不動態５を形成する。その後平坦化のだめの埋め込み
用の酸化硅素膜１４を２μｍ堆積、異方性のエツチング
で不動態５表面が絽出するまでエツチングし、さらに１
μｍの酸化硅素膜１１を堆積する。酸化硅素膜１１上に
第２配線アルミニウム１２を２μｍ堆積後表面に不動態
５を形成し、その上に絶縁膜１３を堆積する。この実施
例では第１．第２配線アルミニウム８．１２上に各々不
動態５を形成したことと、層間アルミニウム１０上に不
動態５を形成したことで配線アルミニウム間の絶縁膜を
薄くすることが可能で、しかも層間アルミニウム１０上
の不動態５をストッパーとすることにより充分な平坦化
のためのエツチングを行うことができるという利点があ
る。更には層間アルミニウム１０の作用により一層微細
化された＃ｌｌ造でも配線アルミ間に電界の相互作用が
働かないという利点もある。。FIG. 2 is a sectional view of an example in which the present invention is applied to multilayer wiring. A first wiring aluminum 8 is deposited to a thickness of 2 .mu.m on the silicon oxide film 2 on the semiconductor substrate 1, and after forming an inactive 4H state 5 by the method described above, a silicon oxide film 9 is deposited to a thickness of 0.4 .mu.m as a second interlayer film. Thereafter, an etching stopper is applied to the silicon oxide film 14 of the insulating film for planarization to shield the electric field between the first wiring aluminum and the second wiring aluminum, and to improve the coverage of the second wiring aluminum. For the purpose of this, interlayer aluminum 10 is deposited to a thickness of 0.1 .mu.m, and after patterning, a passivation layer 5 is formed by the method described above. After that, a silicon oxide film 14 for embedding the flattening layer was deposited to a thickness of 2 μm, etched by anisotropic etching until the surface of the passive state 5 was exposed, and then
A silicon oxide film 11 having a thickness of μm is deposited. After a second wiring aluminum 12 is deposited to a thickness of 2 μm on the silicon oxide film 11, a passivation film 5 is formed on the surface, and an insulating film 13 is deposited thereon. In this embodiment, the first. By forming the passive state 5 on each of the second wiring aluminum 8 and 12 and forming the passive state 5 on the interlayer aluminum 10, it is possible to thin the insulating film between the aluminum wirings, and moreover, it is possible to thin the insulation film between the aluminum wirings 10 and 10. There is an advantage that etching for sufficient planarization can be performed by using the upper passive state 5 as a stopper. Furthermore, due to the action of the interlayer aluminum 10, there is also the advantage that no electric field interaction occurs between the wiring aluminum even in the finer #ll structure. .
以上説明したように本発明は金属配線を形成後、酸化力
をもつ酸により、配線近傍の腐食性の物質を置換、除去
することと、金属表面自体を不動態化することにより、
時間経過による配線の腐食を防ぐこと示出来るという効
果があシ、また金属の不動態の化学的に安定な性質を応
用利用して実施例で示したようなエツチングによる平坦
化を行うときのストッパーとして用いたシ、不動態自身
が絶縁物であることを多層配線に利用して層１′！′ｌ
膜を薄く出来る等の効果がある。As explained above, the present invention replaces and removes corrosive substances near the wiring with an oxidizing acid after forming the metal wiring, and passivates the metal surface itself.
It has the effect of preventing corrosion of wiring over time, and can also be used as a stopper when planarizing by etching as shown in the example by making use of the chemically stable properties of the passive state of metal. The fact that the passive state itself is an insulator is utilized in multilayer wiring to create layer 1'! 'l
This has the effect of making the film thinner.
第１図は本発明の半導体装置の製造方法の一実施例の縦
断面図、第２図は本発明を多層配線に応用した他の実施
例の縦断面図である。
１・・・・・・硅素基板、２・・・・・・酸化硅素膜、
３・・・・・・アルミニウム、４・・・・・・腐食性物
質、５・・・・・・不動態、６・・・・・・酸化硅素膜
、７・・・・・・電極開口部、８・・・・・・第１配線
アルミニウム、９・・・・・・層間絶縁膜Ａ（酸化硅素
ｉ）、１０・・・・・・層間アルミニウム、１１・・・
・・・層間絶縁膜Ｂ（酸化硅素膜）、１２・・・・・・
第２配線アルミニウム、１３・・・・・・絶縁膜（酸化
硅素膜）、１４・・・・・・平坦化用酸化硅素膜。
代理人 弁理士 、内 原 −・′〜］゛２・・・
（。
帛 １ 図
第２ 図FIG. 1 is a vertical cross-sectional view of one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a vertical cross-sectional view of another embodiment in which the present invention is applied to multilayer wiring. 1... Silicon substrate, 2... Silicon oxide film,
3... Aluminum, 4... Corrosive substance, 5... Passive state, 6... Silicon oxide film, 7... Electrode opening Part 8...First wiring aluminum, 9...Interlayer insulating film A (silicon oxide i), 10...Interlayer aluminum, 11...
...Interlayer insulating film B (silicon oxide film), 12...
Second wiring aluminum, 13... Insulating film (silicon oxide film), 14... Silicon oxide film for planarization. Agent: Patent attorney, Uchihara −・′～]゛2...
(. 帛 1 fig. 2
Claims (1)
浸漬し前記金属配線表面に不動態膜を形成する工程を有
することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising the step of immersing a semiconductor substrate on which metal wiring is formed in an oxidizing acid to form a passive film on the surface of the metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13011487A JPS63293861A (en) | 1987-05-26 | 1987-05-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13011487A JPS63293861A (en) | 1987-05-26 | 1987-05-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63293861A true JPS63293861A (en) | 1988-11-30 |
Family
ID=15026286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13011487A Pending JPS63293861A (en) | 1987-05-26 | 1987-05-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63293861A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025418A (en) * | 1988-06-23 | 1990-01-10 | Toshiba Corp | Surface treatment of metal film and selective deposition of metal film |
| JPH09232539A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Manufacture of semiconductor device |
| US5863834A (en) * | 1996-03-06 | 1999-01-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
1987
- 1987-05-26 JP JP13011487A patent/JPS63293861A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025418A (en) * | 1988-06-23 | 1990-01-10 | Toshiba Corp | Surface treatment of metal film and selective deposition of metal film |
| JPH09232539A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Manufacture of semiconductor device |
| US5863834A (en) * | 1996-03-06 | 1999-01-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
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