JPS63204880A - Mh code signal decoding system - Google Patents

Abstract

PURPOSE:To prevent a coding error due to the coding of an MH code signal generated from a point on the way of a scanning line by outputting only a pattern data converted from an MH code signal as a valid image pattern signal after a scanning line start signal is detected from said inputted MH code signal. CONSTITUTION:If a scanning line start signal detection circuit 3 detects a scanning line start signal and the signal is latched by a latch circuit 4, an AND circuit 5 supplies an enable signal from an enable signal generation means 2 to a gate 6, so that a pattern data decoded by a pattern conversion ROM 1 is transmitted to a device in the following devices, and thus the pattern is made a valid one. Such a pattern data thus made valid is a data only after the arrival of a scanning line start signal, i.e., a data from the beginning of each scanning line. In such a way, an erroneous detection due to lock of the number of picture elements caused by starting the decoding an MH code signal corresponding to an interim point on a scanning line, can be prevented.

Description

[Detailed Description of the Invention] [Summary] After a scanning line start signal is detected from an input MH code signal, this MH code signal is converted into pattern data and only pattern data is output as an effective image pattern signal. , a decoding error caused by decoding an MH code signal from the middle of a scanning line is prevented.

[Industrial application field]

The present invention relates to a method for decoding a well-known MH code as a compression code used for transmitting image information such as by facsimile.

[Conventional technology]

The above MH code is a code in which an appropriate number of pixels on one scanning line of a screen such as a facsimile are assigned to one code, and the number of pixels represented by one MH code is constant. do not have. In other words, even if the number of pixels on one scanning line is constant, M indicates the state of the pixels on this scanning line.
The number of H codes is not fixed, so in order to identify MH code data corresponding to one scanning line of the screen, an EOL is set at the end of one scanning line's worth of MH codes, that is, at the beginning of the scanning line.
A code is added, and when a page ends, an RTC code consisting of six consecutive EOL codes is added.

In the conventional example shown in FIG. 3, a received signal is demodulated into the above-mentioned MH code signal by an MH code receiver 201 and stored in a reception memory 203 via a bus 202.
This MH code signal is directly memory access transferred from this memory 203 to a buffer register 205 under the control of a direct memory access controller 204.

The MH code signal read from the buffer register 205 is read by the pattern conversion ROM 206 as pattern data of the number of bytes determined by this code, and is once converted into serial data by the parallel/serial converter 207 and then sent to the serial/parallel converter 208. However, since one clock corresponds to one pixel, the clocks applied as the read clock to the parallel-to-serial converter 207 and the read clock to the serial-to-parallel converter 208 are obtained by counting these clocks. The count value is equal to the number of pixels on the scan line.

Therefore, when the pattern conversion ROM 206 outputs pattern data, it simultaneously sends data indicating the number of bits of the pattern, that is, the number of pixels, to the enable signal generation circuit 206.
9 so that only valid bit data is processed by the serial/parallel converter 208. In this way,
The output of the serial/parallel converter 208, in which only valid bits are converted into parallel signals, is temporarily stored in a register 210, and then stored in a decoded data memory 211 and used for image reproduction.

In such a decoding circuit, the number of effective pixels after the decoding of the MH code signal starts is counted as the specified number of pixels on one scanning line, for example, 1728 pixels in the Chinese direction of A4 size paper, that is, 1728 clocks. The EOL signal indicating the end of a scanning line, that is, the start of the next scanning line, is
If detected by the detection circuit 212, this means that part of the data for this scanning line is missing, and if the next EOL signal has not yet been read out from the buffer register 205 when counting 1728, then Extra data will be inserted as data for this scan line.

In order to detect such an error in the reproduced pattern, the parallel-to-serial converter 207 and the serial-to-parallel converter 2 are supplied via the AND circuit 212 during the generation of the enable signal by the enable signal generating circuit 209.
A counter 213 is provided to count the clocks applied to the buffer register 205, and when the EOL detection circuit 215 detects an EOL signal indicating the end of a scanning line, that is, the start of the next scanning line, from the readout output of the buffer register 205, the counter 213
13 is restarted to start counting the clock, and the comparison circuit 214 compares the count value of this counter 213 with the prescribed value. When these values match (the match output outputted from the knee and the EOL detection circuit 21
EOR which takes the exclusive OR with the EOL detection signal from 5.
By providing circuit 216, the coincidence output or E
The EOR circuit 216 outputs an error signal when only one of the OL detection signals is output. The EOL detection circuit 215 also has an EOL signal counting function for detecting six consecutive EOL signals added at the end of each member of the image and generating a page end signal.

[Problem that the invention seeks to solve]

In the above conventional technology, when decoding is started from an MH code signal corresponding to the middle of a scanning line, the number of pixels on this scanning line of the decoded output does not reach the specified number, so the next EOL signal is detected. At that time, the count value of the counter 213 did not reach the specified value corresponding to the number of pixels on one scanning line, so an error signal was output and the decoding circuit had to be restarted.

In addition, in the conventional technology, when restarting when the above error occurs, the next scanning line start code (EOL signal) is detected by software, so the number of pixels on one decoded scanning line is It is necessary to prepare programs with different processing contents for cases where the error is larger than a predetermined number of pixels and when the error is small, which makes the software complex and difficult to develop. Not only that, but the error processing execution time also increases.

The present invention aims at simplifying the software and speeding up the processing when an error occurs by performing the processing when an error as described above is detected by hardware.

Means for Solving Problem C] As shown in FIG. 1, there is a pattern conversion read-only memory 1 that converts an input MH code signal into pattern data, and a pattern conversion read-only memory 1 that converts the input MH code signal into pattern data, and the validity of the pattern data converted and output by this read-only memory. Enable signal generating means 2 that generates an enable signal during the period, and scanning line start signal detecting means 3 that detects a scanning line start signal from the input MH code signal.
, a latch circuit 4 that is set by the signal detected by this detection means as a scanning line start signal and reset when an error occurs, and a logical product that takes the logical product of the output of this latch circuit and the enable signal. A circuit 5 is provided so that the pattern output from the pattern conversion read-only memory is output as a valid image pattern signal by outputting a decoded data validation signal from this AND circuit.

[For production]

For example, the MH code signal from the buffer memory is applied to the pattern conversion ROMI and the scanning line start signal detection circuit 3, and the pattern conversion ROMI outputs pattern data with a bit length determined by the decoded MH code, and also outputs the pattern data with the bit length determined by the decoded MH code. The enable signal is sent to the generating means 2 and the enable signal is supplied to the AND circuit 5 during the period.
Until the scanning line start signal is detected from the MH code signal applied to the scanning line start signal detection circuit 3 and latched by the latch circuit 4, the output of this latch circuit is "0°", so the AND circuit Since the decoded data validation signal is not output from the gate 5 and the output means illustrated as the gate 6 is also in a cut-off state, the data decoded by the pattern conversion ROM 1 is ignored.

When the scanning line start signal detection circuit 3 detects a scanning line start signal and the detection signal is latched by the latch circuit 4, the AND circuit 5 transfers the enable signal from the enable signal generating means 2 to the gate. 6 and sends the pattern data decoded by the pattern conversion ROMI to a subsequent device.

According to this configuration, the pattern data to be validated is the data after the arrival of the scanning line start signal, that is, the data from the beginning of each scanning line, so it is decoded from the MH code signal corresponding to the middle of the scanning line. By starting the process, it is possible to prevent error detection due to insufficient number of pixels.

Note that the latch circuit 4 need not necessarily be reset for each scanning line, since it is sufficient to continue decoding while the decoding circuit is operating normally.

Therefore, once set, the configuration is such that it remains set and is reset when an error is detected.

〔Example〕

FIG. 2 shows an embodiment of the decoding method according to the present invention.
Components corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1, and components corresponding to those in the conventional example in FIG. 3 are given numerals with 100 subtracted. Ta.

The received signal is demodulated into the above-mentioned MH code signal by the MH code receiver 101 and stored in the reception memory 103 via the bus 102, and this MH code signal is sent from the memory 103 to the direct memory access controller 10.
4, direct memory access transfer is performed to the buffer register 105.

The MH code signal read from the buffer register 105 is read out as pattern data of the number of bits determined by this code by the pattern conversion ROMI as parallel data of one pie unit, and is supplied to the parallel-to-serial converter 107.
At the same time, data indicating the number of bits of the pattern data is sent to the enable signal generation circuit 2.

The pattern data obtained as parallel data by the ROM 1 is once converted into serial data by the parallel to serial converter 107 and then transferred to the serial to parallel converter . No pattern data is output from the serial/parallel converter 108 unless it is supplied to the parallel converter.

On the other hand, the MH code signal from the buffer register 105 is applied to the EOL detection circuit 3, and when an EOL signal is detected in this MH code signal, the EOL signal detection output is sent to the latch circuit 4 and latched. The scan line start detection signal is output until the latch circuit is reset by the output of the OR circuit 118 due to error detection or restart.

This scanning line start detection signal energizes the AND circuit 5, and when the enable signal is supplied from the enable signal generation circuit 2, the AND circuit 5 generates a decoded data validation signal indicating that the decoded data is valid. It is supplied to the serial/parallel converter 108, from which it is transferred as a parallel signal of 1 bit per clock, or in other words, a parallel signal of 1 byte every 8 clocks, to the register 110 for storage. , the clock supplied from the AND circuit 112 to the serial/parallel converter 108 during the existence period of this scanning line start detection signal is supplied to the counter 113 to count this clock.

Therefore, the count value of the counter 113 indicates the number of pixels output from the serial/parallel converter 108.

The count value of this counter 113 is set to 1 by the comparator 114.
A number corresponding to the number of pixels on the scan line, 172 in the above example
8, and during the period when these numbers do not match, it is “0”.
This comparator outputs an output of "1" level, and an output of "1" when these counts match.

Therefore, from the EOR circuit 116 whose input terminals are supplied with the output of the comparator 114 and the "1" level EOL detection signal from the EOL detection circuit 3, only one of the signals input to these input terminals is "1". It produces an output when The "1" output of this EOR circuit 116 becomes a signal indicating that there is an error in decoding.

In the present invention, during a period in which the EOL signal indicating the start of a scanning line is not detected, "1" is output from the latch circuit 4.
Since there is no scanning line start detection signal at the ``'' level, the data decoded from the MH code signal by the pattern conversion ROMI is not output from the serial/parallel converter 108, and the EOL detection signal from the EOL detection circuit 3 is Since the output of the latch circuit 4 is cut off by the AND circuit 117 supplied to one input terminal, the EOR circuit 1
The error signal from 16 is also not output.

The error content detector 118 determines whether an error has occurred, an error due to an insufficient number of pixels, or an error due to an insufficient number of pixels, based on the temporal relationship between the coincidence signal from the comparator 114 and the EOL detection signal from the EOL detection circuit 3. The detection results are used for error processing.

In the case of an error in which the number of pixels is insufficient, that is, an error in which the count value of the counter 113 is less than the number of pixels on one scanning line when the EOL signal is detected, the latch circuit 4 is reset and each pixel on this scanning line is is replaced with the data of each corresponding pixel on the previous scanning line and stored in the decoded data memory 111.
The read address of the receiving memory 103 for direct memory access transfer from 3 to the buffer register 105 is set to 2 from the address from which the EOL signal was read.
This decoding circuit is automatically restarted by setting the address to ~3 bytes earlier so that this EOL signal and the data of the scanning line following this signal are transferred to the buffer register 105 by direct memory access.

Additionally, if an EOL signal is detected after the number of pixels on a scanning line exceeds a specified value, all data for the pixels on this scanning line will be invalidated, and the data for each pixel on the previous scanning line will be stored in the decoded data memory. 111 as data regarding pixels on this scanning line, and the read address of the receiving memory 103 for direct memory access transfer from the receiving memory 103 to the buffer register 105 is set to 2 to 2 from the address from which the EOL signal was read. Set it to the address 3 bytes before, and this EOL
The decoding circuit is automatically restarted so that the signal and the data of the scan line following the signal are transferred to the buffer register 105 by direct memory access.

〔Effect of the invention〕

According to the present invention, even when decoding is started from the middle of a scanning line, decoding is automatically started from the next scanning line, so that no error signal is generated, and software that performs processing when an error occurs A special effect is achieved in that they can be made the same.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the invention, FIG. 2 is a block diagram showing an embodiment of the invention, and FIG. 3 is a block diagram showing a conventional example. 1 is a pattern conversion read-only memory, 2 is an enable signal generation means, 3 is a scanning line start signal detection means, 4 is a latch circuit, and 5 is an AND circuit.

Claims (1)

[Scope of Claims] A pattern conversion read-only memory (1) that converts an input MH code signal into pattern data, and an enable signal that generates an enable signal during the valid period of pattern data converted and output by this read-only memory. A generating means (2), a scanning line start signal detecting means (3) for detecting a scanning line start signal from the input MH code signal, and a scanning line start signal detecting means (3) which is set when the detecting means detects a scanning line start signal and an error signal. a latch circuit (4) that is reset when the signal is detected, and an AND circuit (5) that takes the AND of the output of the latch circuit and the enable signal, and the output of the AND circuit generates the pattern described above. A decoding method for an MH code signal, characterized in that a pattern output from a conversion read-only memory is output as an effective image pattern signal.