JPS62141875A - Preventing system for propagation of decoding error - Google Patents

Abstract

PURPOSE:To prevent the propagation of decoding error by inserting a pattern not in existing in a code word to a specific location in a frame at the transmission side and stopping the decoding corresponding to the location of the pattern or neglecting a part of data at the decoding side so as to match the location. CONSTITUTION:In providing a unique word and decoding a variable length code without ineffective bits in which the bits are rearranged, a specific pattern not in existing in the code word is inserted to a specific position in the frame, e.g., at the 50-th position at the transmission side. When the specific pattern is outputted from a selector 4, a variable length code circuit 6 detects it and informs it to a control signal generating circuit 11. On the other hand, the 50-th signal is inputted from a counter 9 and no specific pattern detection signal comes from the variable length code detection circuit 6, a signal to an output control terminal OC of an FF 7 is brought into an H level by the circuit 11 to hold the preceding data. When the specific pattern detection signal comes and the signal from the counter 9 has a younger number than the 50-th number, the operation of FFs 1-3 is stopped until the number reaches the 50-th number and the decoding during the period is stopped.

Description

[Detailed Description of the Invention] [10 Requirements] When decoding a signal that has a unique word indicating the beginning of a frame and in which variable-length codes are rearranged so that they are continuous without invalid bits, the transmitting side Insert a pattern that is not in the code word at a specific position in the frame, check whether the pattern is at the specified position, and if it is not at the specified position, stop decoding or delete some data. The propagation of decoding errors is prevented by ignoring them and aligning the positions.

[Industrial application field]

The present invention provides a signal in which a color image signal is predictively coded and a residual signal is variable length coded in a TV conference system.
When decoding a signal that has a unique word that indicates the beginning of a frame and that has been rearranged so that variable-length codes are continuous without invalid bits, it is possible to prevent propagation of decoding errors even if errors occur in the transmission path. This paper relates to a decoding error propagation prevention method.

[Conventional technology]

Figure 5 shows the conventional example before (A) and after (B) sorting.
FIG. 2 is a configuration diagram of a signal.

When an image signal is predictively coded and a residual signal is variable-length coded and transmitted, as shown in FIG. 5(A), in order to make one field of pixel signals one frame, a unique word ( UW), and for each pixel ■■■■
...■■■■■..., each MS
For example, a parallel signal as shown in (°A) of 8 bits including invalid bits with B (most significant bit) as the starting point,
Next, in order to reduce the number of bits to be transmitted,
As shown in Figure 5(A), the data is rearranged and transmitted so that there are no invalid bits and it is continuous.The decoding circuit then rearranges it back to the original state shown in Figure 5(A), and then decodes the variable length code. It had become

[Problem that the invention seeks to solve]

However, when the decoding circuit rearranges the signals as shown in FIG. 5(-A), if an error occurs in the signal on the transmission path, a decoding error may occur and the frame length may increase or decrease.

This is gradually restored to normal by successive unique word detections, but the decoding error propagates during these few frames, and especially in the case of color, there is a color burst to reproduce the color after the unique word. , there is a problem that the displayed image is greatly distorted.

[Means for solving problems]

The above problem is that the transmitting side inserts a pattern that is not in the code word at a specific position in the frame, and the decoding side checks whether the pattern is at the specified position. This problem is solved by the decoding error propagation prevention method of the present invention, which adjusts the position by stopping decoding or ignoring some data.

[Effect]

According to the present invention, when detecting the beginning of a frame using a unique word and rearranging the frame, it is checked whether a pattern that is not in the code word is at a predetermined position, and if it is faster than the predetermined position, it is detected at the predetermined position. By stopping decoding until the position is reached, and aligning the position by ignoring the data in the - section if it is later than the predetermined position, subsequent decoding can be restarted correctly, and decoding errors caused by transmission path errors can be avoided. This is to prevent propagation of increases and decreases in frame length due to

〔Example〕

FIG. 1 is a block diagram of a decoding circuit according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of signals in each part of the decoding circuit of FIG.
) (B) (C) are a and b in Figure 1.

It corresponds to 0 points. FIG. 3 is a block diagram of the transmitting side of the embodiment of the present invention, and FIG. 4 is a diagram of the signal configuration of each part in FIG. 3. (A) and (B) correspond to points a and b in FIG. 3. ing.

1.2, 3, 7, 8, 102, 104, 106.1 in the diagram
08, 109, 111, 115 are flip-flops, 4
, 105, 107, and 110 are selectors; 5 is a unique word detection circuit; 6 is a variable length code detection circuit consisting of a ROM configured to output a predetermined output signal in response to a predetermined input signal; 9.112 is a counter; 10 and 114 are adders, 11 is a control signal generation circuit made up of a ROM configured to output a predetermined output signal in response to a predetermined input signal, 12 is a variable length code decoding circuit, 101 is a buffer memory, and 103 is a ROM , 113 is an AND circuit, and 116 is a NOT circuit.

Below, the parallel signal is 8 bits, the variable length code is 8 bits or less,
The unique word will be explained as 16 bits.

First, the transmitting side will be explained using FIGS. 3 and 4.

The 8-bit signal outputted from the buffer memory 101 is inputted via the flip-flop 102 to the ROM 103 which uses a variable-length code as the input signal, and is processed as shown in FIG. 4(A). , each variable length code is an 8-bit parallel signal including invalid bits with the MSB as the starting point,
The code length of the variable length code is input to the flip-flop 104 and output to the adder 114.

The signal input to the flip-flop 104 is sent to the A terminal of the selector 105, where the frame pulse is input to the SOi terminal and the unique word is input to the S terminal.

When the frame pulse is input, the selector 105 selects a unique word and sends it to the flip-flop 106, and then sends the signal input to the S terminal to the flip-flop 106.

During the period when this unique word is selected, the AND circuit 113 prohibits the sending of the sample clock to the buffer memory 101 using a frame pulse, and stops reading out the signal.

The signal containing the unique word sent to the flip-flop 106 is sent to the A terminal of the selector 107, where the signal from the counter 112 is input to the S terminal and a specific pattern that is not in the code word is input to the S terminal. .

A sample clock is input to the counter 112,
It counts the number of data, in this case the 500th, H level signal is output to the S terminal of the selector 107, and the code length (8 bits) is sent to the adder 114.
send to

The selector 107 selects a specific pattern and sends it to the flip-flop 108 based on this 1-level signal.

During the period when this specific pattern is selected, the counter 11
The NOT circuit 116 inverts the T level signal from 2 to inhibit the AND circuit 113 from sending the sample clock to the buffer memory 101, and stops reading the signal.

The signal at the input point a of the flip-flop 108 is a signal in which the 500th specific pattern is inserted, as shown in FIG. 4(A).

The signal input to the flip-flop 108 is sent to the selector 11.
It is sent to the S terminal of 0 and also sent to the A terminal of the selector 110 via the flip-flop 109.

On the other hand, the adder 114 inputs the code length of the variable length code and the code length of the specific pattern that are input one after another to the flip-flop 1.
15 is added sequentially, and the addition result is 8.
When it comes to bits, an L level signal is input to the S terminal of the selector 110 and the AND circuit 113.

Assuming that the first data output from the flip-flop 108 is 4 bits, the second data is 2 bits, and the third data is 6 bits, when added up to the code length of the third data, it becomes 8 bits. An L level signal is input.

As a result, the selector 110 creates and outputs data in which some of the first, second, and third signals up to 8 bits are packed and arranged.

During this time, reading from the buffer memory 101 is stopped by the L level signal via the AND circuit 113.

By repeating the previous operation, as shown in Figure 4 (B), the frame has a unique word at the beginning, the variable length codes are rearranged so that they are continuous without invalid bits, and the 500th code in the frame is A signal with a specific pattern inserted at a position is sent to a receiving decoder.

When this signal [equal to FIG. 2(A)] is input to the decoding circuit of FIG. , and when a unique word is detected, a load is applied to the counter 9.

On the other hand, on the output side of the flip-flop 2.3, the signals for two time slots are inputted to the A and S terminals of the selector 4, and the signals inputted to the terminal A are sequentially outputted from the earliest order. When a variable length code is detected, the code length of this variable length code is added to the control signal generation circuit 11 and added to the adder 10, and this value is added to the code length of the previous variable length code stored in the flip-flop 8. By inputting this into the selector 4, the variable length code is output from the beginning of the next variable length code.

Further, the variable length code detection circuit 6 issues a signal to the counter 9 indicating that a variable length code has been detected, causing the counter 9 to count the number of variable length codes detected in one frame.

In the control signal generation circuit 11, the variable length code is 8bit1. Flip-flops 1 to 1 output a signal that does not stop output until
3, and the output of the selector 4 outputs a signal in which each variable length code is rearranged starting from the MSB as shown in FIG. 2(B).

When the specific pattern is output from the selector 4, the variable length code decoding circuit 6 detects it and sends information indicating the detection to the control signal generating circuit 11.

On the other hand, if the counter 9 is normal, information indicating that it is the 50th variable length code is sent to the control signal generation circuit 11, and from the signal shown in FIG. 2(B), the control signal generation circuit 11 The specific pattern is removed by setting the signal to the output control terminal OC of the flip-flop 7 at H level, resulting in a signal as shown in FIG. let

When the signal from the counter 9 indicating that the number is 50 is input to the control signal generation circuit 11, if a specific pattern detection signal is not received from the variable length code detection circuit 6, the control is continued until the specific pattern detection signal arrives. In the signal generating circuit 11, the signal to the output control terminal OC of the flip-flop 7 is set to H level, and the previous data is held.

Further, when the specific pattern detection signal arrives, if the signal from the counter 9 is younger than the 50th signal, the operations of the flip-flops 1 to 3 are stopped until the 50th signal is reached, and decoding is stopped during this period.

Even when this decoding is stopped, the variable length code detection circuit 6
Rather, a signal equivalent to the detection of a variable length code is sequentially sent to the counter 9.

In this way, errors will occur in the signal due to the transmission path, and
Even if a decoding error occurs, normal decoding can be performed after the specific pattern is detected, the propagation of the decoding error can be prevented, and the disturbance in the displayed image can be minimized.

Even if an error occurs in the signal due to the signal and a decoding error occurs, normal decoding will be possible after the specific pattern is detected.
This has the effect of preventing decoding error propagation and minimizing disturbances in displayed images.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a decoding circuit according to an embodiment of the present invention, Fig. 2 is a configuration diagram of signals of each part of the decoding circuit of Fig. 1, and Fig. 3 is a block diagram of a transmitting side according to an embodiment of the present invention. 4 is a configuration diagram of signals of each part in FIG. 3, and FIG. 5 is a configuration diagram of signals before and after rearrangement in the conventional example. In the figure, 1.2.3,7,8,102,104,106°108
．． 109, 111, 115 is Furifupfu II Tubu, 4. 105, 107, 110. is a selector, 5 is a unique word detection circuit, 6 is a variable length code detection circuit, 9.112 is a counter, 10.114 is an adder, 11 is a control signal generation circuit, 12 is a variable length code decoding circuit, 101 is a buffer memory , 103 is ROM. 113 represents an AND circuit, and 116 represents a NOT circuit.

Claims (1)

[Claims] When decoding a signal that has a unique word that indicates the beginning of the frame and that has been rearranged so that variable-length codes are continuous without invalid bits, the transmitting side decodes the signal at a specific position in the frame. Insert a pattern that is not in the code word into the code word, check whether the pattern is in a predetermined position, and if it is not in the predetermined position, stop decoding or ignore some data to find the position. A method for preventing decoding error propagation, which is characterized by a method for preventing decoding error propagation.