JP2953878B2 - Data transfer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for transferring data between data processing devices, and more particularly to a data transfer system for transferring block data.

[0002]

2. Description of the Related Art In a system for performing this type of block data transfer, it is necessary to confirm the normal operation of data transfer during or after data transmission by some method. For example, in checking for each transfer unit, a method of providing a parity bit in data in advance and performing a parity check may be considered. However, in this method, when a large amount of data is transferred, it is not possible to detect the occurrence of data omission in a transfer unit.

In order to detect the occurrence of such a data drop, a conventional data transfer system transfers data having different block data sizes before transferring the block data in advance. I was

[0004]

However, the data check method for transferring block data in the conventional data transfer system described above requires additional hardware such as the necessity of a counter for counting the number of data on the receiving side. There was no good way to verify that all data was transferred correctly.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a data transfer system which can check whether or not a transfer data amount is correct with a small amount of hardware.

[0006]

According to the present invention, there is provided a data transfer system for performing block data transfer from a first data processing device to a second data processing device, wherein the second data processing device comprises: Transfer data storage means for storing block data transferred from the first data processing apparatus, address register means for designating a storage address to the transfer data storage means, and block data transferred from the first data processing apparatus Receiving the block data in which the last element of the block data is added with final address information which is information indicating the storage address of the final element itself in the data storage means, and which is stored in the final address information and the address holding means. Data comparing means for comparing the block data with the address. Data transfer error is detected.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a transmission-side data processing device, which is a control circuit for controlling transfer of block data, and a storage device for storing block data (both not shown).
including.

Reference numeral 2 denotes a receiving-side data processing device, a transfer control circuit 10 for controlling the transfer of block data, a transfer data receiving register 11 for receiving the transferred block data, and a transfer data for storing the transferred block data. It has a buffer 12, an address counter 13 indicating a byte address of the transfer data buffer 12, and a comparison circuit 14 for comparing data between the transfer data reception register 11 and the address counter 13 at the end of transfer.

Reference numeral 20 denotes a 1-byte-wide transfer data line which is a data interface for block data, 21 denotes a transfer request signal indicating a request to transfer block data from the transmission-side data processing device 1 to the reception-side data processing device 2,
Reference numeral 22 denotes the control circuit 10 in response to the transfer request signal 21.
, A transfer permission signal indicating reception of a transfer,
Is a data strobe signal of the transfer data reception register 11, 24 is an address count-up signal of the address counter 13, 25 is a check enable signal for validating the operation of the comparison circuit 14, and 26 is a signal transmitted when a mismatch occurs in the comparison circuit 14. Error signal.

FIG. 2 shows an example of block data handled by the present invention. In the present invention, the transmission-side data processing device 1
Knows in advance the byte address where the head data of the block data in the transfer data buffer 12 of the receiving side data processing device 2 is stored. For this reason, the transmission-side data processing device 1 sets the transfer data buffer 12 in which the last element itself is stored as the last element of the block data.
Is calculated from the block data size, and is added to the end of the block data as a part of the block data.

Assume that the data transfer unit is 1 byte and the block data to be transferred is 100 bytes. Assuming that the address of the transfer data buffer 12 where the first block data is stored is “100”, data “200” is added as the last address information of the block data.

FIG. 1 is a timing chart of block data transfer in this embodiment.

A description will be given in order from the cycle A. First, in the cycle A, the transmission-side data processing device 1 validates the transfer request signal 21 to the reception-side data processing device 2 when starting the block data transfer. The transfer request signal 21 is valid until the transfer of the block data including the final address information is completed.

In cycle B, the receiving data processing device 2
Transfer control circuit 10 can receive a transfer request signal 21 because it can receive block data transfer from the transmission-side data processing device 1 and sets the address counter 13 to the head address “100” of the block data as preparation before transfer. .

In a cycle C, a transfer permission signal 22 is sent to the data processor 1 on the transmission side.

In the cycle D, the transmission-side data processing device 1 having received the transfer permission signal 22 sends out the first byte of data to be transferred to the transfer data line 20. Further, the reception side data processing device 2 makes the data strobe signal 23 valid. The data strobe signal 23 becomes invalid at the same time that the transfer request signal 21 becomes invalid.

In cycle E, the receiving side data processing device 2
Captures the first 1-byte data output to the transfer data line 20 into the transfer data reception register 11 because the data strobe signal 23 is valid. The transmission-side data processing device 1 transmits the data of the second byte to the transfer data line 2
Send to 0. At this time, the address counter 13 has the value “100” set before the transfer of the block data, and the data taken into the transfer data reception register 11 is stored in the address “100” of the transfer data buffer 12.
In this cycle, the transfer control circuit 10 makes the address count-up signal 24 valid. The address count-up signal 24 becomes invalid at the same time that the transfer request signal 21 becomes invalid.

In cycle F, the receiving side data processing device 2
Captures the second byte of data output to the transfer data line 20 into the transfer data receiving register 11 because the data strobe signal 23 is valid. In addition, the transmission-side data processing device 1 sends the data of the third byte to the transfer data line 20. The address counter 13 counts up to “101” because the address count-up signal 24 is valid, and the address “10” of the transfer data buffer 12 is
The data fetched into the transfer data reception register 11 is stored in "1".

Thereafter, data acquisition and address count-up are repeated until the minimum data of the block data is transferred. In cycle H, the transmission-side data processing device 1
Sends the data of the 100th byte one byte before the last address information to the transfer data line 20. Since the data strobe signal 23 is valid, the receiving-side data processing device 2 captures the 100th byte of data output to the transfer data line 20 into the transfer data reception register 11, and the current address counter 13 in the transfer data buffer 12 It is stored at the indicated address “199”.

In cycle J, the transmission-side data processing device 1 invalidates the transfer request signal 21. In response, the data strobe signal 23 and the address count-up signal 24 become invalid. Since the data strobe signal 23 is valid in the previous cycle, the reception-side data processing device 2 takes in the data of the last address information output to the transfer data line 20 into the transfer data reception register 11. Since the address count-up signal 24 is valid in the previous cycle, the address counter 13 counts up by +1 and indicates "200". Therefore, the address "200" of the transfer data buffer 12 is taken into the transfer data reception register 11. The last address information is stored.

In response to the transfer request signal 21 being invalidated in this cycle, the transfer control circuit 10
Makes the check enable signal 25 valid. In response, the data "200" indicated by the address counter 13 is received.
The comparison circuit 14 compares the last address information “200” held in the transfer data reception register 11 with the last address information “200”. When the results do not match, an error signal 26 is sent out as a block data transfer error. Error signal 26
Is transmitted to a control device (not shown) of the entire system, and error interrupt processing is started.

Note that the final address information stored in the transfer data buffer 12 is used as transfer check information even after the block transfer described in this embodiment.

[0025]

As described above, the present invention adds the storage address information of the last element itself as the last element of the block data to be transferred by the data processing apparatus on the transmission side, and the data processing apparatus on the reception side transmits the last element. By comparing the storage address of the data with the contents of the final element itself and detecting a block data transfer error from the result, the problem of the data check method after transfer in the conventional data transfer system can be solved. It is possible to provide a system that can check whether the data amount is correct with a small amount of hardware.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing transfer block data handled by the present invention.

FIG. 3 is a timing chart of the embodiment shown in FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission-side data processing device 2 reception-side data processing device 10 transfer control circuit 11 transfer data reception register 12 transfer data buffer 13 address counter 14 comparison circuit 20 transfer data line 21 transfer request signal 22 transfer enable signal 23 data strobe signal 24 address count Up signal 25 Check enable signal 26 Error signal

Claims (1)

(57) [Claims] 1. A data transfer system for performing block data transfer from a first data processing device to a second data processing device, wherein the second data processing device includes a block transferred from the first data processing device. Transfer data storage means for storing data; address register means for designating a storage address to the transfer data storage means; and block data transferred from the first data processing device, wherein the last element of the block data is Data comparing means for receiving block data added with final address information, which is information indicating the storage address of the last element itself in the data storage means, and comparing the final address information with the address held in the address holding means. And detecting the block data transfer error from the result of the data comparing means. Data transfer system that.