JPS63197220A - Normalizing circuit - Google Patents

Abstract

PURPOSE:To avoid such a case where the normalizing result is equal to -2<n> by performing the left shift by an extent equal to the value obtained by subtracting '1' from the output of a 1st means when the output of a 2nd means is equal to '1'. CONSTITUTION:A shifter control circuit A11 outputs the control outputs L0, L1 and L2 to a table 1 (not shown here) with the output of a register 10 defined as an input based on the input/output relation. A shifter control circuit B12 outputs the control output R based on the input/output relation shown in a table 2 (not shown here). Then a left 1-bit shifter 14 controlled by the output L0 is added together with a left 2-bit shifter 15 controlled by the output L1, a left 4-bit shifter 16 controlled by the output L2, and a right 1-bit shifter 13 controlled by the output R. The data shown in a table 2 is shifted left by an extent equal to the value subtracting a single bit and therefore can be normalized in an equivalent way as the shift mode of a conventional normalizing circuit in a state where a negative number is expressed in a compliment of '2'. It is not needed to use a subtractor that calculates a left shift number reduced by a single bit. Thus, a normalizing action is performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a number system in which negative numbers are expressed as two's complement.
The present invention relates to a normalization circuit that performs normalization processing in a complement state.

2. Prior Art As a conventional normalization circuit, for example, Japanese Patent Laid-Open No. 59-188
It is disclosed in Japanese Patent No. 740 "Floating Adder" as one of the constituent elements of the invention. FIG. 3 shows only the floating point data mantissa normalization circuit extracted from the embodiment of the present invention.

1 is an arithmetic unit that performs floating-point mantissa operations;
2 is a register that holds the calculation results, 3 is calculation unit 1
A normalization shift detection circuit that counts the number of consecutive 0's from the most significant bit at the output of , 4 is a register that holds the detection result of normalization shift detection circuit 3, and 5 is a register 4 that indicates the contents of register 2. This is a chic that shifts left by a bit.

In the conventional circuit configured as described above, the maximum output of the arithmetic unit 1 (in this cited example, the input and arithmetic mode of the arithmetic unit 1 are controlled so that it is always positive) is The number of consecutive "0"s starting from the upper bits is detected by the normalization shift detection circuit 3, and the output of the arithmetic unit 1 is shifted to the left by the shifter 5 by the detected number.

Problems to be Solved by the Invention However, the above configuration requires that the data to be normalized be positive, and a negative number expressed as a two's complement is directly converted into an absolute value without being converted to an absolute value in advance. The problem was that it was not possible to normalize the expression format.

In view of this point, the present invention normalizes negative numbers expressed in two's complement representation without converting them to absolute values, and the normalization result is -(2-2) to +(2-2'') e・ ・(1) Seven (here m is the data bit length, 21 is the code nm
+1 is the weight of the bit, 2 is the weight of the least significant bit), that is, the normalization result is not -2''.

Means for Solving the Problems The present invention provides a register that holds data in which negative numbers are expressed as two's complement numbers, and when the sign bit of the register output is "0", the most significant bit excluding the sign pip). The first means outputs the number of consecutive 0's from the most significant bit excluding the sign bit, and the first means outputs the number of consecutive 1's from the most significant bit excluding the sign bit. a second means for inspecting whether or not the data has consecutive "0"s starting from the least significant bit, and outputs "1" if the data does, and outputs "0" if it does not; When the output is "0", the output of the register is shifted to the left by the output of the first means, and when the output of the second means is "1", the number is subtracted by 1 from the output of the first means. This is a normalization circuit having a shift means for shifting to the left by .

Effects The present invention has the above-described configuration, - When the sign bit is "0", remove the sign bit (number of consecutive "0"s from the most significant bit - when the sign bit is "same"). Consecutive "l" from bit
``Number 1 - where = 1 = If the data of the register output has consecutive 0's from the least significant bit = 0: The data of the register output has consecutive 0's from the least significant bit. The shift means shifts to the left by the number indicated in the case where there is no.

Embodiment FIG. 1 shows a configuration diagram of a normalization circuit in an embodiment of the present invention. To simplify the explanation, the data format is as shown in FIG. 2, with the sign bit S as the most significant bit, N=(-1)-3-2°+zn-, $2-'...
(2) Consider 8-bit data representing country 1. In FIG. 1, 10 is a register that holds data in which negative numbers are represented by two's complement; 11 is a register that receives the output of register 10, controls output according to the input/output relationship shown in Table 1, and outputs 01LL, L2; The shifter control circuit A112 made up of a combinational logic circuit is a shifter control circuit B made up of a combinational logic circuit which receives the output of the register 10 as an input and outputs a control output R according to the input/output relationship shown in Table 2. 1
3 is a right 1-bit shifter that shifts the output of the register 10 by 1 bit to the right when the output R of the shifter ili control circuit B12 is "1". 14 is a left 1-bit shifter that shifts the output of the right 1-bit shifter 13 to the left by 1 bit, 15 is a left 2-bit shifter that shifts the output of the left 1-bit shifter 14 by 2 bits to the left, and 16 is a left 2-bit shifter that shifts the output of the left 2-bit shifter 15 by 4 bits to the left. This is a left 4-bit shifter that performs bit shifting, and each operates when the output Lo1L+sL2 of the shifter control circuit All is "1".

The operation of the normalization circuit of this embodiment configured as described above will be described below.

First, data N is stored in the register 10. shifter 81
All 11 circuits follow Table 1, and when the sign bit S is "0", the sign bit is removed (consecutive from the most significant bit).
If it is the sign bit or “l”, divide the sign bit (count the number of consecutive “1”s starting from the most significant bit, and convert the result to binary numbers L2 and Ll).

Output in LO.

When the sign bit S is “0”, the left 4-bit shifter 16,
The left 2-bit shifter 15 and the left 1-bit shifter 14 each receive the control signal L! , L1%[, o, and the left 4-bit shifter 16 outputs a result in which the bit with a weight of 2 becomes "1".

Even when the sign bit S is “1”, the left 4-bit shifter 16,
The left 2-bit shifter 15 and the left 1-bit shifter 14 perform shift operations in accordance with control signals L2 and L1%LO. However, when the data in register 10 is the mantissa part of floating point data, and the data is as shown in the input column of Table 2, it is necessary to perform shift correction for the following reason.

As described in the related art section, the normalization circuit of the present invention performs normalization processing so that the normalization result becomes as shown in equation (1). This is to make the result of normalization by the normalization circuit of the present invention equal to the result of normalization by the conventional normalization circuit as shown in the conventional example in all cases.

In this example, n and m in equation (1) are each 0.8
Therefore, it is necessary to normalize the normalization result so that it becomes -<2-2) to +(2-2)...(3). That is, normalization is performed so that the normalization result does not become -2.

Here, if the shift is performed according to Table 1, the bit pattern shown in the input column of Table 2 will be shifted by one extra bit, and the output of the left 4-bit shifter 16 will be 1oooooooo,
In other words, -2 is output.

Therefore, in these cases, the shifter control circuit Bll according to Table 1
Output! , Ll, it becomes necessary to perform a left shift with the result of subtracting 1 from LO. For this reason, a sick control circuit B12 is provided. When the bit pattern shown in the input column of Table 2 is input to the register 10, the output R of the thick control circuit B12 becomes "1'", and the right 1 bit shifter 1
Operate 3. In other words, the input to the left 1-bit shifter 14 is shifted 1 bit to the right in advance (by doing so, the input to the left 1-bit shifter 14 is
Prevents left shifting by extra bits.

As described above, according to this embodiment, the output of the register LO is input, and the control output LO is set according to the input/output relationship shown in Table 1.
, L'1L2, a shifter control circuit B12 that outputs a control output R according to the input/output relationship shown in Table 2, a left 1-bit shifter 14 controlled by the control output o, a control output 1. A left 2-bit shifter 15 controlled by t, a left 4-bit shifter 16 controlled by control output 2, and a right 1-bit shifter 13 controlled by control output R are provided, and the data shown in Table 2 is shifted left by 1 bit less. By doing this, it is possible to perform normalization equivalent to that shifted by a conventional normalization circuit while representing a negative number as a two's complement number. Further, a subtracter for calculating the number of left shifts that is one bit smaller is not required, and high-speed normalization is possible.

Table 1 Table 2 As described in detail, according to the present invention, it is possible to perform normalization equivalent to that shifted by a conventional normalization circuit when a negative number is expressed in two's complement. Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a normalization circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of an example of a data format, and FIG. 3 is a block diagram of a conventional normalization circuit. 11...Shifter control circuit A112...Shifter control circuit B113...Right 1-bit shifter, 14...Left 1-bit shifter, 15...Left 2-bit shifter, 16...
Left 4-bit shifter. Name of agent: Patent attorney Toshio Nakao and 1 senior citizen
N- Figure 2 Figure 3

Claims (2)

[Claims] (1) Negative numbers are stored in a register that holds data expressed in two's complement, and when the sign bit of the register output is “0”, consecutive “0” from the most significant bit excluding the sign bit
When the sign bit is "1", the first means outputs the number of consecutive "1"s from the most significant bit excluding the sign bit, and the data of the register output is consecutive from the least significant bit. a second means for checking whether or not the second means has "0", and outputs "1" if it has, and outputs "0" if not; and when the output of the second means is "0". Said first
Shifting means for shifting the output of the register to the left using the output of the means, and shifting the output of the register to the left by a number subtracted by 1 from the output of the first means when the output of the second means is "1". A normalization circuit characterized by: (2) The shift means is connected in series to a left shifter that performs a left shift according to the output of the first means, and the left shifter, and when the output of the second means is "1", the right 1 bit is set. 2. The normalization circuit according to claim 1, comprising a rightward shifter for performing a shift.