JPH02267625A - Integer part take-out system using floating point arithmetic - Google Patents

Abstract

PURPOSE:To perform an integer part take-out arithmetic with use of a floating point adder by adding a simple hard circuit to the adder. CONSTITUTION:When an operand 1 is added to an operand 2, a floating point adder 20 puts the operand 1 containing a constant 0 of its mantissa part into one of both inputs of the adder 20 together with the operand 2 put into the other input to take out an integer part. Then the adder 20 carries out a floating point addition arithmetic up to an intermediate point and decides whether a rounding operation should be carried out or not during the arithmetic operation. When the rounding operation is carried out by a rounding part 8, a normalizing shift part 7 performs a left shift and 1 is buried into a right shift-in part. At the same time, a 1-addition part 13 adds 1 to the normalized output. As a result, the rounding operation is always carried out at the position of a decimal point. Thus it is just required to add a simple hard circuit to the adder 20. Then an integer part take-out arithmetic is attained with use of the adder 20.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an integer retrieval method using a floating point arithmetic operation in which an integer retrieval operation is performed using a sequence in which operands 1 and 2 are added using a floating point arithmetic operation, using a floating point adder. The purpose of this is to perform an operation to extract an integer part, and set a constant whose mantissa part is 0 to operand 1, and an operand for extracting an integer part to operand 2. Performs a digit alignment shift, suppresses one input of data during mantissa addition, performs a left shift for normalization based on the addition result, and determines whether to perform rounding based on the addition output and normalization shift output. , when performing rounding, 1 is filled from the right side of the left shift, and 1 is added to the normalized shift output.

[Field of Industrial Application] The present invention relates to an integer part retrieval method using floating point arithmetic, which performs an integer part retrieval operation using a sequence in which operands 1 and 2 are added using floating point arithmetic.

In order to maintain compatibility of data and processing in the field of scientific and technical computing, IEEE
of Electrical and Ele
Many systems now support the standard format created by the American Institute of Electrical and Electronics Engineers (Ctronics Engineers). The standard specifies an operation for extracting the integer part.

[Prior art] An integer part extraction operation is to extract the real integer part, including the exponent, from an operand (number to be operated on) consisting of a sign (S), an exponent (E), and a mantissa (F). Say something. The general procedure for the integer part extraction operation specified by IEEE is as follows.

■Determine whether the data is a numerical value.

■Determine whether the index is within the required range for rounding.

■If the exponent is within the required rounding range, round at the decimal point and fill in O's below the decimal point. If the exponent is not within the required rounding range, no rounding will be performed.

[Problems to be Solved by the Invention] In the integer extraction operation, rounding must be performed at the decimal point position as described above. If this rounding operation is to be executed at high speed, a decimal point position detection circuit and a rounding circuit for rounding at the decimal point position are required, which increases the number of hardware circuits and increases the price.

The present invention has been made in view of the above-mentioned problems, and provides an integer part extraction method using floating point arithmetic, which enables integer part extraction operations to be performed using a floating point adder. It is an object.

[Means for Solving the Problems] FIG. 1 is a flowchart showing the principle of the system of the present invention. In the present invention, when performing an addition operation between operand 1 and operand 2, set a constant whose mantissa part is 0 to operand 1, set an operand for extracting the integer part to operand 2, and use the operand with the smaller exponent. Performs digit alignment shift on the mantissa (Step 2), and suppresses input of one side of the data when adding the mantissa (Step 3)
), and performs a left shift for normalization based on the addition result (step 4
), Decide whether to perform rounding based on the digit alignment output and addition output. Step 5). When rounding, fill in 1 from the right side of the left shift (Step 6), and add 1 to the normalized shift output. (Step 7).

[Operation] Put a constant whose mantissa part is 0 in one side of the floating-point adder,
An operand for extracting the integer part is input to the other input, a floating point addition operation is performed halfway through the operation, and it is determined whether or not to perform rounding in the middle of the operation. When performing rounding, after performing a left shift of the normalization shift, 1 is filled in the shift-in section on the right side, and 1 is added to the normalization output. As a result, rounding is always performed at the decimal point. According to the present invention, it is only necessary to add a small amount of hardware circuitry to the floating-point adder, and the cost does not increase due to an increase in the number of hardware circuits.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit block diagram for implementing the present invention. In the figure, 20 is a standard floating point adder.

Let the exponent of operand 1 be a1, the mantissa be b1, the exponent of operand 2 be 01, and the mantissa be d.

In the figure, 1 is an index comparison unit that compares the magnitude relationship between exponents a and C, 2 is a selector that selects either one of exponents a or C, 3 is a selector that selects either mantissa or d, and 4 is a selector that selects one of exponents a and C. is also a mantissa.

This is a selector that selects either one of d.

Reference numeral 5 denotes a digit alignment shifter for digit alignment shifting of the mantissa output from the selector 4, and numeral 6 a mantissa addition unit for adding the mantissa output from the selector 3 and the mantissa output from the digit alignment shifter 5.

7 is a normalization shift unit that receives the output of the mantissa addition unit 6 and shifts the decimal point for normalization; 8 is a normalization shift unit 7
A rounding unit 9 performs rounding processing on the output of , and 9 is an exponent correction unit that performs correction on the exponent selected by the selector 2 during normalization. The part described above is the floating point adder 20 that performs floating point addition of operands 1 and 2. A mantissa is output from the rounding unit 8, an exponent is output from the exponent correction unit 9, and the exponent and the mantissa are output as an addition result.

11 is a rounding determination unit that receives the outputs of the digit alignment shift unit 5 and the mantissa addition unit 6 and determines whether or not rounding is to be performed;
2 is a filling part that fills in 1 to the right side when performing a left shift of normalization, and 0 when rounding is not performed, and 13 is a normalization shift part when performing rounding. This is a 1 adder that adds 1 to the LSB of the output of 7. The operation of the circuit configured as described above will be explained below with reference to the flowchart shown in FIG.

First, operand 1.2 is set (Sl). Operand 1 is set to a constant having a floating point number whose exponent is such that the least significant digit of the mantissa is 2 to the power of 0, and whose mantissa part is all 0.

Operand 2 is set to an operand for exponent extraction calculation. The index comparator 1 compares the index a of the operand 1 and the index C of the operand 2 (S2). As a result of the comparison, in the case of arc, the index comparator 1 gives select signals to selectors 2 to 4, selector 2 selects a, selector 3 selects b(-〇), and selector 4 implicitly Select d that includes the indicated most significant mantissa (S3).

As a result of the comparison, if a≦C, the exponent comparison unit 1 gives select signals to selectors 2 to 4, selector 2 selects C, and selector 3 selects d containing the implied highest mantissa.
, and the selector 4 selects b (-0) (S4). The digit alignment shift unit 5 shifts the output of the selector 4 to the right by the index difference determined by the index comparison unit 1, and fills it with 0 from the left (S5). Further, the digit alignment shift unit 5 obtains a guard digit, a rounding digit, an adhesive digit, etc. for rounding determination (S6).

FIG. 4 is an explanatory diagram of the protection girder, rounding girder, and adhesive girder. It is assumed that the digits of the mantissas F1 and F2 shown in the figure are aligned. The result of adding Fl and F2 is F3. F
In the IEEE format, the portion of F2 smaller than the least significant digit of l is stored as 3-bit data as a guard digit G, a rounding digit R, and a sticky digit. Here, an adhesive digit is 1 if at least one 1 is included in the digits below it (the shaded area in the figure). The necessity of rounding is determined based on these G, R, data.

Next, the mantissa addition unit 6 adds the mantissas of operands 1 and 2 (S7). Specifically, the output of the selector 3 and the output of the digit alignment shift section 5 are added. In this case, the mantissa addition unit 6 suppresses input on the constant side, assumes it to be 0, and performs addition. As a result, the output of the mantissa addition unit 6 is
When the operand (operand 2) of the integer part extraction operation is smaller than the constant (operand 1), the right end is aligned to the 0th power of 2, and the operand (operand 2) of the integer part extraction operation is smaller than the constant (operand 1). ), it becomes the number of operands.

Based on the addition result of the mantissa addition unit 6, the exponent correction unit 9 performs exponent correction (S8). In other words, since there is a possibility that a carry may occur as a result of the addition of two mantissas, if a carry occurs, it is necessary to increase the exponent of the exponent correction unit 9 by that amount. In the normalization shift section 7,
A normalized amount is determined based on the addition result of the mantissa addition unit 6 and shifted to the left (S9). At this time, the G, R, and K digits shown in Figure 4 are not included.

The rounding determination unit 11 determines whether to perform rounding based on the outputs of the digit alignment shift unit 5 and the mantissa addition unit 6 (S
10). When performing rounding, data is given from the filling unit 12 to the normalization shift unit 7, and data is rounded by 1 from the right side of the left shift.
is filled in (Sll), and the 1 addition section 13 fills in the LSB of the rounding section 8.
1 is added to (S12). As a result, when rounding is performed in the rounding unit 8, the carry propagates to the 0th power of 2, and rounding is performed to the 0th power of 2.

On the other hand, if there is no need for rounding in S10, the filling unit 12 provides data to the normalization shift unit 7,
Zeros are filled from the right side of the left shift (813), and the data is output as is without rounding (S14). In this way,
The exponent correction section 9 outputs a corrected exponent, and the rounding section 8 outputs a mantissa rounded as necessary. The data represented by these exponents and mantissas becomes the result of the integer part extraction operation.

FIG. 5 is a flowchart showing rounding control, which shows the rounding control sequence shown in FIG. 3 in more detail. First, it is checked (sl) whether or not it is an integer part extraction operation, and in the case of an integer part extraction operation, the sequence shown in the figure is obtained. Here, the sequence after the digit alignment sequence is shown. The result of digit alignment by the digit alignment shifter 5 is output (S2). Here, the code is S, the least significant digit is I, the guard digit is G, the rounding digit is R1, and the sticky digit is K.

Next, the type of rounding is determined by the rounding determination unit 11 (S3). As shown in the figure, there are four types of rounding: nearest rounding, zero rounding, positive rounding, and negative rounding. Among these roundings, in the case of zero direction rounding, no rounding is performed. In this case, the filling unit 12 fills the normalized shift-in data with "0" (S4), and performs round addition to add "0" to the least significant digit (S5). In other words, in this case, the data will be output as is without rounding.

If the rounding is the nearest value rounding, the rounding determining unit 11 checks whether any one of the R, R, and K bits in G-1 is 1 (S6). If so, the filler 12 fills the shift-in data of the normalized shift with "1" (S7), the 1 adder 13 adds "1" to the lowest significant digit, and rounding addition is performed. Execute (S8).

If this is not the case, that is, if the condition that any one of the bits in G-1 is 1 is not satisfied, S4. Perform the process of S5.

If the rounding is positive rounding, the rounding determining unit 11 checks whether any one of the bits G, R, in S-1 is 1 (S9). If so, the filler 12 fills the shift-in data of the normalized shift with "1" (S7), the 1 adder 13 adds "1" to the lowest significant digit, and rounding addition is performed. conduct(
S8).

If this is not the case, that is, if the condition that one of the bits in G, R, and S-1 is not satisfied, S4. Perform the process of S5.

If the rounding is negative rounding, the rounding determining unit 11 checks whether S-1 and any one of the G, R, and K bits is 1 (S10). If so, the filler 12 fills the shift-in data of the normalized shift with "1" (S7), and the 1 adder 1
3, "1" is added to the lowest significant digit and rounded addition is performed (S8). If not, that is S-1 big G
, If the condition that one of the R and K bits is 1 is not satisfied, step S4. Perform the process of S5.

In the above description, a case has been described in which a constant is input as operand 1 to one input of the floating point adder 20. The present invention is not limited to this, and the constant may be automatically generated by the control circuit.

[Effects of the Invention] As described above in detail, according to the present invention, by adding a simple hardware circuit to the floating-point adder, it is possible to perform integer part extraction operations using the floating-point adder. It is possible to provide an integer part extraction method using floating point arithmetic, and the hardware circuit is simple and the cost can be kept low.

[Brief explanation of drawings]

Fig. 1 is a flowchart showing the principle of the method of the present invention, Fig. 2 is a circuit block diagram for implementing the invention, Fig. 3 is a flowchart showing the operation of the circuit shown in Fig. 2, and Fig. 4 is a guard girder, rounding. FIG. 5, which is an explanatory diagram of the girder and the adhesive girder, is a flowchart showing the rounding control. In Fig. 2, 1 is an exponent comparison section, 2 to 4 are selectors, 5 is a digit alignment shift section, 6 is a mantissa addition section, 7 is a normalization shift section, 8 is a rounding section, 9 is an exponent correction section, and 11 is an exponent correction section. A rounding determination section, 12 a filling section, and 13 a 1 addition section.

Claims (1)

[Claims] When performing an addition operation between operand 1 and operand 2, set a constant whose mantissa part is 0 to operand 1, set an operand for extracting the integer part to operand 2 (step 1), and set a constant whose mantissa part is 0 to operand 1 (step 1). Performs a digit alignment shift on the mantissa of the other operand (step 2), and inhibits input of one of the data when adding the mantissa (step 3).
), and performs a left shift for normalization based on the addition result (step 4
), determines whether to perform rounding based on the digit alignment output and addition output (step 5), and when rounding, fills in 1 from the right side of the left shift (step 6), and adds 1 to the normalized shift output. An integer part extraction method using floating point arithmetic, characterized in that processing is performed (step 7).