JP3187402B2 - Floating point data addition / subtraction circuit - Google Patents

Description

The present invention relates to a circuit for adding and subtracting normalized floating-point data, and particularly to a digital signal processor (DSP for short) and a high-level circuit. It is used for microcomputers.

(Prior Art) Normalized floating-point data is widely used in signal processing LSIs that realize a high precision and a wide dynamic range, such as DSPs and high-level microcomputers. Incidentally, the signal processing LSI is required to have high speed. One of the factors that limit the increase in speed is a floating point data addition / subtraction circuit (referred to as FASU).

First, a conventional floating point addition / subtraction circuit (FASU) will be described.

 FIG. 29 shows a block diagram of a conventional FASU.

First, the exponent part data of the input X and the input Y are compared by the digit aligning circuit 1, and the mantissa data is aligned according to the difference. At this time, if the difference between the exponents is larger than the mantissa digit alignment digit, one of the mantissa data having the smaller exponent is fixed to 0 (0 determination circuit).

Next, the addition / subtraction circuit 2 performs addition / subtraction of the two-input mantissa data that has been digit-aligned.

Finally, the normalization circuit 3 estimates the amount of normalization from the result of addition and subtraction of the mantissa, and normalizes the result of addition and subtraction according to the estimation.

FIG. 30 is a circuit block diagram of a conventional 32E6 (mantissa part 32 bits, exponent part 6 bits) FASU. Next, this circuit will be described.

First, the exponent part data XE of the input X is input by the subtraction circuit 4.
With the exponent part data YE of the input Y. Digit alignment is performed by shifting the mantissa data XM or YM to the right according to the result of the subtraction. Then the shift is
This is performed by the X shifter 5 and the Y shifter 6. The following table shows the shift conditions.

Next, the mantissa data XM 'and YM' after digit matching are added or subtracted by the addition / subtraction circuit 7 according to the instruction. A normalization circuit includes a normalization amount detection circuit 8, a left shift circuit 9, and a subtraction circuit 10 for normalizing the output data added and subtracted by the addition and subtraction circuit 7. The addition / subtraction result ZM 'is input to the circuit 8, and the normalized amount of the mantissa data is detected. The mantissa ZM 'is shifted to the left according to the normalized amount. Further, the circuit 10 subtracts the normalized amount from the exponent part ZE '. The mantissa output ZM and the exponent output ZE, which are the output results, become the outputs of the floating point addition / subtraction circuit.

Next, a method of subtracting XY by actually substituting numerical values will be described. The data length is such that the mantissa part is 32 bits and the exponent part is 6 bits. The first bit of the mantissa below is the sign bit
It is. The left side of E is mantissa data and the right side is exponent data.

When calculating the above equation, first, XE-YE is determined.

From XE> YE, | XE−YE | = 4 in the above calculation result, YM
Subtract by 4 bit shift.

That is, the normalized amount is detected from the subtraction result ZM '. Sign bit
Is 0, and since 0 is continuous for 1 bit, the normalized amount is D = 1, that is, 1 bit shift.

Next, the mantissa part ZM 'is shifted one bit to the left according to the normalization amount. The output result ZM is the output of the mantissa. Since the exponent part is “XE−YE> 0”, both XE and YE are adjusted to the exponent part 100000 of XE by the digit matching circuit, and ZE ′ is Z
E '= XE = 100000. After that, the mantissa data is shifted to the left by 1 bit according to the normalization amount D = 1, so that the exponent data decreases by one. Therefore, the exponent part data ZE is 0111
It becomes 11.

In this case, XE = 100000 and YE = 011111.
Since t is different, YM is shifted right by 1 bit for digit alignment.

Here, ZM '= 00000100 ... 000, ZE' = 100000 and Z
Estimate the normal quantity from M '. Since there are four 0s after the sign bit, D = 4. That is, ZM 'is shifted to the left by 4 bits, and ZE' is reduced by 4. That is, ZM = 01000000 ... 000 and ZE = 011100.

In the case of, since XE−YE = 2, When this is normalized (one-bit shift), Z = 010011... 10 E 0111111 is obtained.

FIG. 31 is a block diagram of a conventional floating point addition / subtraction circuit having a 31-bit mantissa part and a 6-bit exponent part. Next, this circuit will be described. Here, the 0 fixed circuits 12, 13 and the 0 determination circuit 1 included in the X shifter 5, the Y shifter 6, the subtraction circuit 4, etc.
4. The shift amount detection circuit 15 and the like are extracted and shown.

In this circuit, first, the difference between the exponent part data XE of the input X and the exponent part data YE of the input Y is obtained by the subtraction circuit 4,
Digit alignment is performed by shifting the mantissa data XM or YM to the right according to the result. The shift at that time is performed by the X shift circuit 5 and the Y shift circuit 6. FIG. 32 shows the shift amounts and conditions at that time.

Next, the mantissa data XM 'and YM' after the digit alignment are added / subtracted by the 31-bit addition / subtraction circuit 7 according to the instruction.

Finally, the output data is normalized according to the output result of the addition / subtraction circuit 7. First, the output result of the 31-bit addition / subtraction circuit 7 is input, and the normalization amount detection circuit 8 detects the normalization amount. Shift the significand to the left according to that value, and convert it to ZM
And Further, the normalized amount is calculated by the subtraction circuit 10 into the exponent part ZE ′.
, And the result is ZE. The output results ZM and ZE
Is the output result of the floating point addition / subtraction circuit.

(Problems to be Solved by the Invention) The floating-point addition / subtraction circuit having a data length of 32E6 shown in FIG. 30 includes, as input data, normalized input signals X and Y of 32E6 and an operation instruction for selecting addition or subtraction. As for the output,
The result Z obtained by adding and subtracting the input signals X and Y according to the operation instruction is output.

As described above, after the input signals X and Y are input, before the calculation outputs Z (ZE and ZM) are output, the signal passes through the next circuit in series.

1) The shift amount is calculated from the 6-bit subtraction circuit 4.

2) From the result of the above 1), the signal passes through shifters 5 and 6 of 31 bits (5 stages).

3) The result of the above 2) is calculated by a 32-bit addition / subtraction circuit 7.

4) Input the calculation result "32bit + carry" and input 5bi
The signal passes through the encoder circuit 8 for calculating the normalized amount to be output.

5) According to the normalized amount detected by the encoder 8,
The data passes through a 31-bit (5-stage) shifter 9 for shifting the mantissa data.

5) ′ According to the normalized amount detected by the encoder 8,
It passes through a 6-bit subtraction circuit 10 for reducing exponent data.

As described above, the floating-point addition / subtraction circuit has a drawback that the operation speed is slow because the signal flows in series 1) to 5) or 1) to 4), 5) ', and this limits the speeding up of the signal processing LSI. It has become one of.

In addition, in the conventional FASU shown in FIG.
When the difference between the input exponents is equal to or greater than the number of digits of the mantissa data, that is, when the shift amount is equal to or greater than the shift amount, the shift cannot be performed.
Alternatively, addition and subtraction are performed by fixing the mantissa data of a small number of the exponent part of XM 'to 0 (FIG. 32).

Therefore, a 0 determination circuit 14 for fixing XM or YM to 0 based on the output result of the subtraction circuit 4 and an input signal XM ′ of the 31-bit addition / subtraction circuit 7 are provided on the critical path of the operation path of the floating-point addition / subtraction circuit (FASU). Alternatively, YM 'can be
According to the output result of (1), 0 fixing circuits 12, 13 for fixing all to "0" are inserted. This means an increase in the number of gate stages of the floating point addition / subtraction circuit, which hinders speeding up.

In the floating-point addition / subtraction circuit of FIG. 31, since the normalization circuit detects the normalization amount from the output result of the mantissa addition / subtraction circuit 7, the normalization, that is, the left shift by the normalization amount of the mantissa part is performed. Subtraction by the normalized amount of the exponent part is not performed until the result of addition / subtraction of the mantissa is detected, making it difficult to increase the speed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a floating-point data addition / subtraction circuit which can operate at a higher speed than the conventional one.

The present invention has at least first and second mantissa data operation paths, and the first mantissa data operation path includes a predetermined mantissa data operation path. A digit aligning circuit having a digit aligning function for performing digit alignment of mantissa data in accordance with a difference between exponent data within a predetermined digit range; and mantissa data adjusted by the circuit. An addition / subtraction circuit for performing addition or subtraction, a normalization amount detection circuit for detecting a normalization amount from an operation result of the circuit, and a normalization shifter for normalizing mantissa data in accordance with the normalization amount. Wherein the second mantissa data operation path has an input operand through path and an input operand sign inverting circuit, and operates the first and second mantissa data operation paths in parallel, When adding decimal point data, During but larger mantissa digits combined digits, through data operand exponent is larger as addition and subtraction result at the time of subtraction instruction of floating point data,
When the difference between the exponents is greater than the number of digits for the mantissa, the through data on the minuend is added when the minuend in the two operands is large, and the sign-reversed data on the minuend is added or subtracted when the minuend is large. A floating-point data addition / subtraction circuit, wherein the output of the first and second mantissa data operation paths is selected according to the difference between the exponent data.

The present invention also provides a digitizing circuit for performing digit alignment of mantissa data in accordance with a difference between exponent data, an addition / subtraction circuit for adding or subtracting mantissa data aligned by the circuit, Using a part of each bit of the mantissa data before the operation and several bits before and after the operation, a logical operation is performed without a carry signal, a flag is set from the operation result, and the flag is set by the normalization amount encoding circuit. A normalization amount detection circuit as an input, a normalization shifter for normalizing the mantissa data from the addition / subtraction circuit in accordance with the output of the circuit, and a right or left one of the output data from the output of the shifter Means for selecting whether or not to perform a bit shift.

That is, the present invention provides a plurality of data paths in consideration of a certain condition with respect to the data flow of the prior art, and selectively controls and selects each of the data paths with floating-point data. The function is simplified and the number of gate stages of the circuit is reduced. Further, in order to reduce the reduction in processing speed due to the 0 decision circuit and the 0 fixing circuit in the prior art, at least two operation circuits selected by a shift amount generated for digit alignment are provided. High speed is realized by selecting the result. That is, when the shift amount of the mantissa part is smaller than the number of digits of the mantissa part due to the subtraction of the exponent part, the operation result of the addition / subtraction circuit similar to the conventional technique is selected. However, a 0 fixed circuit is not added to this circuit. In other words, the mantissa part of the data with the smaller exponent part is shifted right by the subtraction result of the exponent part, and is subjected to addition / subtraction, and then normalization is performed. When the shift amount of the mantissa is greater than or equal to the number of digits of the mantissa due to the subtraction of the exponent, a data through or sign inversion circuit is selected. The above two circuits are processed in parallel, and are finally selected by the exponent input.

Further, the present invention is characterized in that the normalization circuit detects the normalization amount from the data after digit matching, that is, the input data of the mantissa addition / subtraction circuit. Detection of normalized amount,
Most of the processing used for normalization is performed in parallel with mantissa addition / subtraction by using input data of a mantissa addition / subtraction circuit.

Further, in the present invention, when the output of the adder / subtractor circuit for the mantissa data overflows, a circuit that shifts right by one bit is taken out from the normalization shifter, and these are selectively used in parallel, thereby reducing the number of gate stages and increasing the speed. I am wearing it.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a configuration diagram of a floating-point data addition / subtraction circuit considered in the course of the present invention.
1, an addition / subtraction circuit 22, and a ± 1 bit shift normalization circuit 23. The path B includes a digit aligning circuit 24 for shifting up to 1 bit, an adding / subtracting circuit 25, and a normalizing circuit 26. The paths A and B are selected by the control signal C to the selector circuit 27, and the selected signal is the output Z.

The mantissa conditions of the two normalized floating-point signals are 010000... 000 ≤ XM ≤ 0111 ...... 111 (1) 010000 ... 000 ≤ YM ≤ 0111 ... 111 (2) Here, for the sake of simplicity, the case where both XM and YM are positive will be described. However, considering that XM and YM are two's complement expressions, the same description applies when one or both of XM and YM are negative. it can. Here, the weight of the most significant bit on the left and right sides of XM (when XM> 0) is “1”, the weight of the next digit is “1/2”, the weight of the next digit is “1/4”,. The same applies to YM. Therefore, the left side of XM in equation (1) and (2)
Both the left sides of YM in the equation represent "1/2". Also XM
Are both "1" for the least significant bit.
Represents a smaller number.

From equation (5), when YM is shifted to the right by 2 bits or more, And the normalization is at most 1 or less. In other words, "1" means 1-bit shift, and "0" means no shift. From equation (6), if XM is shifted to the right by 2 bits or more, And the normalized amount is at most 1 or less.

From the above results, the condition that the normalized shift of 2 bits or more is required is when the amount of alignment (the amount of alignment of the mantissa between the exponents) is 1 bit or less, ie, | XE−YE | ≦ 1. .

The circuit of FIG. 1 is provided with two addition and subtraction paths A and B, and A has a conventional alignment circuit, but the normalized amount is at most 1 bit.
And B has a conventional normalization circuit although the digit alignment is 1 bit or less. The output of the signal path A and the output of B are obtained separately, and finally the output of A or the output of B is
To select. As a selection condition by the signal C at that time, 2
Use the difference | XE−YE | ≦ 1 of the input signals. It will be described later that high speed can be realized by the above features.

 FIG. 2 is a specific example of FIG.

1) For the signal path A, (i) subtracting the difference “XE−YE” between the exponents of the two input signals into the subtraction circuit 31
Is calculated by Accordance with the difference, the X shifters 21 _1, Y shifter 21 ₂ performs digit combined by shifting the XM or YM right. However, as a condition, when “XE−YE> 31”, YM = 0
And When “XE−YE <−31”, XM = 0. These are when the shift range is exceeded.

(Ii) According to (i) above, the mantissa data Y after digit alignment
M′1 and YM′1 are added or subtracted by the addition / subtraction circuit 22 according to an addition or subtraction instruction. Also, the larger exponent part data is selected by the selector 32, and this is set as ZE 'and the subtraction circuit is used.
Output to 34.

(Iii) The output result ZM'1 of the addition / subtraction circuit 22 is input to the ± 1 bit normalization encoder 33, and a left or right 1 bit shift control signal is output from the upper several bits of ZM'1. Normalization is performed by the left and right 1-bit shifters 23 according to the shift control signal. The output of the shifter 23 is output to the mantissa output ZM1 of the signal path A.
And

Here, there is a possibility that the normalized amount of ZM'1 becomes ± 1 bit or more, but since the output selector 27 selects the path B, it is “don't care” (no relation).

2) Next, regarding the signal path B, (i) the lower 2 bits of the exponent part of the two input signals, that is, XE1, XE0, YE1,
As input YE0, according FIG. 3, 1bit shifter 24 ₁ or
24 ₂ shifts XM or YM right by 1 bit. In FIG. 3, "X" has an undefined meaning. FIG. 6 shows a circuit for generating signals XS (X shift) and YS (Y shift) designed based on the Carnot map of FIG.

(Ii) According to (i) above, mantissa data XM 'after digit alignment
2 and YM'2 are added or subtracted by an addition or subtraction instruction.
Add or subtract 25.

(Iii) A normalization amount is detected by the normalization amount detection circuit 35 for the output result ZM'2 of the addition / subtraction circuit 25. According to the detection result, normalization is performed by shifting by the 31-bit left shifter 26. The output of the shifter 26 is used as the mantissa data ZM2 of the signal path B.

3) Next, the mantissa output results ZM1 and ZM2 and the normalized amount result M1 or the selection condition of the control signals of the selectors 27 and 36 for selecting M2 are determined by FIG.

Sign bit of input signal XM, YM, addition / subtraction instruction, exponent part XE, YE
7, the selection signal C is generated as shown in FIG. 7, and the selector 27 and the selector 36 select and output the output result accordingly.

 The circuit of FIG. 2 has the following advantages.

That is, as shown in FIG. 30, in the conventional 32E6 floating-point addition / subtraction, the signal path first obtains the difference of the exponent part by the 6-bit subtraction circuit 4, and according to the difference of the exponent part, the X shifter 5
Alternatively, digit alignment is performed by a Y shifter 6 (31-bit shifter). The data is added and subtracted by a 32-bit addition / subtraction circuit 7,
A normalization amount is detected using the result of the addition and subtraction, and the shifter 9 shifts according to the normalization amount. The data circuit delay at that time is as follows: (1) 6-bit subtraction circuit 4 → five-stage shift circuit 5 or 6 →
32bit addition / subtraction circuit 7 → -1bit, + 31bit encoder 8 → 5
The stage shift circuit 9 is obtained.

On the other hand, in the circuit of FIG. 2, (2) 6bit subtraction circuit 31 → 5-stage shift circuit 21 ₁ or 21 ₂
→ 32 bit addition / subtraction circuit 22 → ± 1 bit encoder 33 → 1-stage shift circuit 23 → select circuit 27 or (3) 4-input control circuit (Fig. 6) → 1-stage shift circuit 24
₁ or 24 ₂ → 32-bit addition / subtraction circuit 25 → + 31-bit encoder 25
→ 5-stage shift circuit 26 → select circuit 27 The circuit delay is the slower of the signal paths (2) and (3).
Obviously, (2) and (3) have a smaller number of gate stages than (1) and can achieve high speed.

FIG. 8 shows an embodiment of the present invention obtained by improving the conventional FIG. 31.
This is applied to FASU with 31 bits of mantissa and 6 bits of exponent. 9 (a) is a block diagram of a general 1-bit subtractor, FIG. 9 (b) is a truth table thereof, FIG. 9 (c) is a circuit diagram thereof, and FIG. 10 is 1-bit subtraction of FIG. 11 (a) and FIG. 12 are diagrams of a conventional X shift circuit and Y shift circuit, and FIG. 11 (b) is a block diagram of a circuit section 51. FIG. 11 (c) is the detailed circuit diagram of FIG.
13 and 14 show the X shift circuit 5 and the Y shift circuit 6 in FIG.
Is shown.

In FIG. 8, 41 to 44 are selectors, and when the selection inputs (C ₁ , C ₂ ) are “1”, the inputs on the A _{0 to} A ₃ side are selected,
When the selection input is "0", the other input is selected. 45 is PM
This is a through / −PM circuit, and this circuit 45 is a mantissa XM of X
Selector when side is selected or added (X + Y)
The output PM of the selector 41 is passed through and the output PM of the selector 41 is inverted and output when the mantissa YM side of Y is selected and subtraction (XY) is performed. In FIG. 8, (1) the absolute value | XE-YE | of the difference between the exponents of the input data is detected by the subtraction circuit 4, and when this is less than 31, the following circuit is finally selected.

First, for digit alignment, the mantissa part XM, Y is determined by the value of XE−YE.
The shift shown in FIG. 15 is performed on M.

That is, 0 is not fixed, and data need not be guaranteed in the range of | XE-YE | ≧ 31.

Next, the mantissa parts XM 'and YM' obtained by the shifter are operated by the 31-bit addition / subtraction circuit 7.

Next, the mantissa part Z obtained by the above addition / subtraction circuit 7
In order to normalize M ′, a normalization amount is detected by a normalization amount detection circuit 8. Here, the normalization amount detection circuit 8 is a priority encoder that receives the mantissa part ZM ′ and gives priority to the upper bits.

The mantissa part ZM 'is shifted to the left by the above-mentioned normalized amount, and is set as the mantissa part output.

By the subtraction circuit 10, from the larger exponent part data XE and YE, by subtracting the normalization amount, which is an exponent output B _3.

(2) When the output | XE−YE | of the subtraction circuit 4 is 31 or more, the following circuit is finally selected.

This circuit comprises a selector 41 and a PM through / -PM circuit 45.
And the operation result shown in FIG. 16 is output.

In FIG. 16, the "instruction" means X + Y, XY, and the "addition and subtraction" means both addition and subtraction.

(3) As described above, finally, (1) and (2) above
Is selected by the 0 determination circuit 14 from the operation result of the subtraction circuit 4, and these are output ZM and ZE.

In the present embodiment, two system operation results processed in parallel are finally selected by the 0 determination circuit 14. That is, in the floating point addition / subtraction circuit according to the present embodiment, the 0 determination circuit 14 is not included in the critical path. Further, in the prior art shown in FIG. 31, the floating point addition / subtraction circuit according to the present embodiment does not include the 0 fixed circuits 12 and 13 which receive the operation result of the 0 determination circuit 14 as an input. In the related art, the processing speed is largely reduced by the 0 determination circuit and the 0 fixing circuit, but in the present invention, high speed is realized by avoiding this.

FIGS. 17 to 19 show an embodiment in which the normalized amount is detected from the mantissa data before addition and subtraction to increase the speed. In the figure 51
Is a YM through / -YM circuit, and in the case of subtraction, inverts the sign of the mantissa YM. 8 ₁ is the encoder of the normalization amount detection circuit 8, 52
~ 54 is a subtraction circuit, 55 is a 1-bit correction detection circuit, 56 is 1b on the left
It is a shifter, 57 is a right 1-bit shifter, and 58 and 59 are selectors. The shifter 56 shifts one bit to the left when the 1-bit shift is insufficient, and the shifter 57 shifts one bit to the right when the shift is too much. When it is desired to pass the normalized data as it is, the path 60 is used.

(1) First, an embodiment of normalization amount detection which is a feature of the present invention will be described.

Here, it is assumed that the mantissa data is a correction number expression of 2 with no hidden bits, and only an addition instruction is considered.

First, when XM 'and YM' have the same sign in the mantissa data after digit alignment, the addition result is not left-shifted by normalization. That is, in the addition result, X
Only the case where M 'and YM' have different codes should be considered. Here, a method of directly detecting the normalized amount from XM 'and YM' will be considered. For the following explanation, the corresponding bi of XM 'and YM'
The case where both t are 0 is expressed as “0”, the case where one is 1 is expressed as “1”, and the case where both are 1 is expressed as “2”.
Normalization occurs because, in the addition result, the same data as the MSB (most significant bit), which is the sign bit, is continuously 3 bits from the MSB.
This is a case where more than bits are arranged, and there are only two cases shown in FIG.

That is, in the case of, the addition result becomes negative, and 1 continues to the normalized position in the addition result. If this is viewed from the data before addition, 1 is first followed by 0 followed by 1 bit. Next, when a value other than 2 comes, 1 does not continue below this in the addition result. If 2 comes after 0 in the data before addition, 1 continues in the addition result as long as 2 continues.

In one case, the addition result is positive, and 0 continues to the normalized position in the addition result. In the same way as in this case, when looking at the data before addition, 1 is first followed by 2 followed by 1 bit. Next, when a value other than 0 comes, 0 does not continue below the addition result in the addition result. When 0 comes after 2 in the data before addition, 0 continues in the addition result as long as 0 continues.

From the above, by examining the adjacent 3 bits in the data before addition, it is known whether or not the center bit can be a normalized position.
The above-mentioned verification is performed with 3 bits including a bit, and a flag is set for a corresponding bit, that is, a flag is set where an MSB is obtained after normalization after addition. by passing the encoder _81, it can be detected normalization amount.

In order to explain in detail, the above is divided into cases as shown in FIG. 21, and the flag position by the normalization detection is also described.

Here, as described in the remarks column in FIG. 21, two normalizations may be expected for the addition result. This is caused by carry from the lower bit, but the normalized amount differs at most by 1 bit. Since 1-bit correction is easy, 1-bit correction is performed after addition.

By the way, in FIG. 21, when the 1-bit correction is necessary, a flag (indicated by “1”) is set in 2 bits where normalization can occur, such as “... 011 ×. However, assuming that one bit is corrected after the addition, any one of these two bits may be flagged. An example in which a logic circuit for normalization amount detection is designed in consideration of this point will be described. Here, S and C are pre-addition data, SC = 00 when “0”, SC = 10 when “1”, SC when “2”
= 01. Also, for the 3 bits, S0C
0, S1C1, and S2C2.

a) When correcting the right one bit after addition.

In this case, of the 2-bit flags in consideration of the 1-bit correction, the lower bit is flagged and the upper bit is not. FIG. 22 shows a Carnot diagram, and FIG. 23 shows a normalized amount detection circuit obtained from the Carnot diagram. In FIG. 22, a portion surrounded by a circle over two columns, upper and lower or left and right, shows a technique for simplifying a circuit obtained from the Karnaugh diagram, and the circuit in FIG. 23 corresponds to S0, C0, S1, C1 in FIG. , S2, S2.

b) When correcting the left one bit after addition.

In this case, among the 2-bit flags taking into account the 1-bit correction, a flag is set for the upper bit, and the flag for the lower bit is “0”,
Any of "1" is acceptable. FIG. 24 shows a Carnot diagram, and FIG. 25 shows a normalized amount detection circuit obtained from the Carnot diagram. It can be realized with a smaller circuit than the case of correcting the right one bit.

c) When adding 1 bit left or right after addition.

In this case, among the 2-bit flags taking into account the 1-bit correction, the lower bit is flagged, the upper bit flag is set to “0”,
Any of "1" is acceptable. FIG. 26 shows a Carnot diagram, and FIG. 27 shows a normalized amount detection circuit obtained from the Carnot diagram. It can be realized with a smaller circuit than the case of correcting the left 1 bit.

(2) Next, the mantissa part 31bit and the exponent part 6 to which the present invention is applied
An embodiment of a floating-point addition / subtraction circuit for bits will be described.

FIG. 17 is a block diagram of the present embodiment in which correction of 1 bit left and right is considered.

First, the exponent part data XE of the input X is calculated by the subtraction circuit 4.
XE−YE | is calculated by the X shift circuit 5 and the Y shift circuit 6 in accordance with the result, and the mantissa data XM or YM is shifted to the right by | XE−YE |. Perform digit alignment by Also, by the selector 11
The larger of XE and YE is selected, and this is set as ZE '.

Next, in order to apply the normalization amount detection circuit described in (1), in the case of subtraction, the sign of the mantissa of Y is inverted by the circuit 51.

Next, the mantissa data XM 'and YM' are added, and at the same time, the normalization amount NE is detected by the normalization amount detection circuit (1), and the output is encoded.

Next, the normalization amount NE is subtracted from the exponent part ZE 'by the subtraction circuits 52 to 54. At this time, the subtraction circuits 52 to 54 each consider the correction of one bit left and right in the normalization of the exponent part, and
Compute NE-1, ZE'-NE, and ZE'-NE + 1.

Simultaneously with the subtraction, the mantissa part ZM 'is normalized by the left shifter 9 according to the normalization amount. Thereafter, the detection circuit 55 detects a left and right 1-bit correction value by the left 1-bit shifter 56 or the right 1-bit shifter 57.

Finally, the mantissa part ZM and the exponent part ZE are selected by the selectors 59 and 58 in accordance with the correction amount detected from the output of the left 3 bit shifter 9 at the same time as the above-mentioned normalization, and these are set as the output results of the floating point addition / subtraction circuit.

FIG. 18 is a block diagram of an embodiment in which the right one bit is corrected. As described in (1) above, the normalization amount detection circuit is complicated in the case of 1-bit correction on the left and right, but a subtraction circuit for exponent normalization and a 1-bit shifter for mantissa normalization are each one. The number of selectors 58 and 59 for selecting ZE and ZM can be small as well.

FIG. 19 is a block diagram of an embodiment in which correction of the left 1 bit is considered. As described above in (1), the normalization amount detection circuit is simpler than the case of the left 1-bit correction, but is more complicated than the case of the left and right 1-bit correction. However, the circuit scales of the subtraction circuit and the 1-bit shifter for normalization are the same as in the case of the right 1-bit correction.

In the conventional floating-point addition / subtraction circuit, since the normalization circuit detects the normalization amount from the output result of the mantissa addition / subtraction circuit, normalization is not performed until the addition / subtraction result of the mantissa is detected. In this embodiment, since the normalized amount is detected from the mantissa data before addition / subtraction, normalization is performed prior to the output of the result of addition / subtraction of the mantissa, and a high-speed floating-point addition / subtraction circuit can be designed. In particular, since the subtraction of the exponent part occupies a large proportion of the time spent for normalization, performing this operation prior to the mantissa part addition / subtraction output contributes to speeding up.

FIG. 28 is a block diagram of a floating-point data addition / subtraction circuit designed to speed up FASU, which was considered in the course of the present invention. That is, in a normal normalizing circuit (for example, see the shifter 9 in FIG. 31), a shifter for shifting right by 1 bit is provided in the preceding stage when the output of the adding / subtracting circuit overflows. The 1bit right shifter 9 _1, so may be made independent from the shifter 9, these shifter 9, 9 ₁ arranged in parallel, for example, by the control signal formed using the upper 2bit output of subtracter 7, a selector 16 If you select the output with
The number of gate stages after the addition / subtraction circuit 7 is reduced, and the speed can be increased accordingly. Alternatively, the speed can be increased similarly by making only the critical path independent of the shifter 9 without making the entire right 1-bit shifter independent.

Note that the present invention is not limited to the embodiments, and various applications are possible. For example, in the embodiment, there are two mantissa operation paths,
These are selected, but may be more.

[Effects of the Invention] As described above, according to the present invention, the number of gate stages can be reduced, and a plurality of operation paths can be operated together,
Since only the desired output is selected or the selection signal is obtained in parallel during the operation of the operation path, a high-speed floating-point data addition / subtraction circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a floating point data addition / subtraction circuit considered in the course of the present invention, FIG. 2 is a block diagram showing a specific example of the same configuration, and FIGS. 3 to 5 show the operation of the same configuration. 6 and 7 are partially detailed circuit diagrams of the same configuration, FIG. 8 is a configuration diagram of an embodiment of the present invention, FIG. 9 is a partially detailed explanatory diagram of the same configuration, and FIG. Partial diagram of subtraction circuit and 0 determination circuit, eleventh
FIGS. 12 and 13 are conventional circuit diagrams used to explain the effects of the configuration of FIG. 8, FIGS. 13 and 14 are circuit diagrams showing an improved example of the conventional circuit, and FIGS. 15 and 16 are FIGS. Chart showing the operation of the configuration of
17 to 19 are configuration diagrams of different embodiments of the present invention,
20 to 27 are partial explanatory diagrams of the same configuration, FIG. 28 is a block diagram of a floating-point data addition / subtraction circuit considered in the course of the present invention, and FIGS. 29 to 31 are conventional circuit diagrams. FIG. 32 is a table showing the operation of FIG. 31. 4,10,31 ... subtraction circuit, 5,6 ... right 30bit shifter, 7 ...
Addition / subtraction circuit, 8 Normalization amount detection circuit, 8 ₁ … Encoder, 9… Left 30-bit shifter, 9 ₁ … Right 1-bit shifter, 15…
... Shift amount detection circuit, 16 ... Selector, 21 ₁ ... X shifter, 21 ₂ ... Y shifter, 21,24 ... Digit matching circuit, 22,25 ...
… Addition / subtraction circuit, 23,26… Normalization circuit, 24 ₁ , 24 ₂ … 1 bit
Shifter, 27 ... Selector, 33,35 ... Encoder, 41,43
… Selector, 45… PM through / −PM circuit, 51… Through or inverting circuit, 55… Correction amount detection circuit, 56… Left 1 bit
Shifter, 57: Right 1-bit shifter, 59: Selector.

Continuation of the front page (72) Inventor Masayuki Koizumi 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Semiconductor System Technology Center Co., Ltd. (56) References JP-A-60-204031 (JP, A) JP-A-53-133344 (JP, A) JP-A-63-310022 (JP, A) JP-A-59-226944 (JP, A) JP-A-61-33539 (JP, A) JP-A-1-111229 (JP) , A) JP-A-63-167930 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 7/50

Claims (2)

(57) [Claims] 1. A first mantissa data operation path having at least first and second mantissa data operation paths, wherein the first mantissa data operation path has a digit matching function of a predetermined number of digits. A digit aligning circuit for performing digit alignment of mantissa data in accordance with the difference of exponent data within the range, an addition / subtraction circuit for adding or subtracting mantissa data aligned by the digit alignment circuit, and an addition / subtraction circuit And a normalization shifter for normalizing the mantissa data according to the normalization amount. The second mantissa data operation The path has an input operand through path and an input operand sign inverting circuit, operates the first and second mantissa data operation paths in parallel, and provides a difference between exponent parts when an instruction to add floating-point data is issued. Is greater than the number of digits in the mantissa, When the through data of the operand with a large part is the result of addition and subtraction and the difference of the exponent part is larger than the number of digits of the mantissa part at the time of the subtraction instruction of the floating point data, and the manuscript in the two operands is large, The through data on the subtrahend side is used as the result of addition and subtraction when the subtrahend is large, and the sign-inverted data on the subtrahend is used as the result of addition and subtraction. The first and second mantissa data operation paths are performed according to the difference between the exponent data. A floating-point data addition / subtraction circuit, wherein an output of the floating-point data is selected. 2. An alignment circuit for performing digit alignment of mantissa data in accordance with a difference between exponent data, an addition / subtraction circuit for adding or subtracting mantissa data aligned by the alignment circuit, and an addition / subtraction circuit. Using a part of each bit of the mantissa data before the operation in the circuit and several bits before and after it, a logical operation is performed without a carry signal, a flag is set from the operation result, and it is normalized encoding circuit A normalization amount detection circuit as an input of the normalization amount detection circuit; a normalization shifter for normalizing the mantissa data from the addition / subtraction circuit in accordance with an output of the normalization amount detection circuit; Means for selecting whether to shift the output data by one bit to the right or left and outputting the mantissa part of the addition / subtraction result; and outputting the output of the normalization amount detection circuit from the larger exponent part data of the exponent part data. Subtract this Floating-point data addition and subtraction circuit next instruction and or the subtraction value to be characterized in that and means for outputting the 1-bit addition or subtraction value based on the output of the shifter for the normalization as exponent of the addition and subtraction result.