JPS63137351A - Dmac device with logical operation function - Google Patents

Abstract

PURPOSE:To execute data transfer while executing logical operation and to attain data transfer without applying load to a CPU by adding a logical operation function to a DMAC. CONSTITUTION:Data are transferred from a data block 21a to a data register 14a by a 1st data transfer 22 and then transferred from a data block 21b to a data register 14b by a 2nd data transfer 24. At the time of a 3rd data transfer, logical operation between both transfer data is executed by a logical operation circuit 15 and the operated result is transferred to a data block 21c for destination data.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to data transmission between a plurality of storage devices (memories) controlled by a common central processing unit, directly between the memories without going through this central processing unit. DMAC with logical operation function used for cases (direct memory access), etc.
Regarding equipment.

2. Description of the Related Art Conventionally, this type of DMAC (direct memory access control) device has been used during data transfer between memories or between memories and input/output devices without changing the data contents.

Problems to be Solved by the Invention However, in the above-mentioned conventional DMAC device, data calculation is not possible, so the calculation is performed by the central processing unit (CPU).
), there was a problem in that it placed an extra burden on the CPU.

The present invention solves the above-mentioned conventional problems, and
It is an object of the present invention to provide a DMAC device with an excellent logic operation function that can transfer data while performing data operations without placing a burden on the computer.

Means for Solving the Problems In order to achieve the above object, the present invention provides a logic operation circuit and a data register within the DMAC device, and is configured to enable data operations without placing a burden on the central processing unit. It is something.

Effect: With the above configuration, the present invention adds an arithmetic function to the DMAC device, making it possible to transfer data while performing data arithmetic. This is particularly noticeable when the CPU bus and the data transfer bus by the DMAC device are separated. .

Embodiment FIG. 1 shows a DMA with logical operation function according to an embodiment of the present invention.
FIG. 2 is a block diagram of a C device. In FIG. 1, numeral 11 is a data transfer mode setting register, which sets the type of operation, write, read, etc. A word count register 12 is used to set the number of data transfers. A plurality of memory address registers 13 are provided, and the number of registers 13 differs depending on the data blocks 21a to 21C in FIG. 2. 14a, 1
4b is a data register, which temporarily saves data during data transfer. Reference numeral 15 denotes a logic operation circuit, which performs operations between data registers.

FIG. 2 is a block diagram showing an example of data transfer while performing logical operations using this embodiment.

In FIG. 2, 218.21b is a data block containing source data, and 21C is a data block containing destination data. These data blocks 212 to 21C are memory devices or input/output devices.
They may overlap or be completely separate.

Next, examples of the present invention will be described.

In FIGS. 1 and 2, data is first transferred from the data block 21a to the data register 14a by the first data transfer 22, transferred from the data block 21b to the data register 14b by the second data transfer 23, and then transferred to the data register 14b by the third data transfer 22. At data transfer 24, a logical operation is performed on both data and the destination data is transferred to the data block 21G.

In Figure 2, we explained the case where one unit of data is transferred in three cycles, but normal DMA transfer (
direct memory access transfer), that is, between memories and between memories and input/output devices. Also,
Data register 14a.

Fixed data can be input to 14b and the same data can be transferred. In this case, data is transferred in one cycle.

Arithmetic functions include DRI, DB2, DRI, DB2
, ノDRI, DH,2, DRI, DB,2
, DRI-1i, r-DB2.

DRI +DR2, DRI +DR2, DR, 1+DR
2, DRI +■π2. DRi$DR2, million RteD
Rz, DR[9Dπi can be considered.

However, "・" is a logical product (AND), and r+J is a logical sum (
OR), rIEIJ indicates exclusive OR. Depending on the content of the logical operation, one of the 1-cycle to 3-cycle data transfers is selected.

In this way, in this embodiment, data can be transferred while performing calculations without placing a burden on the CPU.

In particular, by separating the CPU bus and the bus dedicated to data transfer by DMAC, the effect becomes even more remarkable.

Effects of the Invention As is clear from the above embodiments, the present invention adds a logical operation function to the DMAC, so data can be transferred while performing logical operations, so data can be transferred without putting a burden on the CPU. It has this effect.

[Brief explanation of the drawing]

FIG. 1 shows a DMA with logical operation function according to an embodiment of the present invention.
FIG. 2 is a block diagram of the C device, showing an example of data transfer while performing logical operations using this embodiment. 11...Data transfer mode (MSR), 12...
Word count register (We R), 13...Memory address register (MAR1-3), 14a, 14b
・=Data register (DRI, 2), 15...Logic operation circuit, 21a to 2IC-data block (SL, S
2. D). Name of agent: Patent attorney Toshio Nakao and one other persontt
W Figure 2

Claims (1)

[Claims] A data transfer mode setting register that sets the type of operation and recording/playback, a word count register that sets the number of data transfers, multiple data registers that temporarily save data during data transfer, and logical operations between these data registers. A logic operation circuit, a data block for transferring source data and destination data of the logic operation circuit via a bus, and a memory address register for storing addresses according to the number of these data blocks, A DMAC device with a logic operation function, wherein data is transferred between the data blocks via the data register and the logic operation circuit under control of the data transfer mode setting register and the word count register.