JPH0567035A - Data alignment system for dma transfer - Google Patents

Abstract

PURPOSE:To freely set a transfer size, and to shorten a transferring time by using the transfer information of a block by setting a transfer leading address, number of transfer words, and furthermore transfer size at an array table being the transfer information of an array chain mode. CONSTITUTION:When the leading address of data to be transferred is not the multiple of the data length of a main bus 6, an MPU 1 divides the transfer data into plural blocks so that the leading address can be the multiple of the greatest common divisor of the data length, and sets an array table 4 at each block, before transmitting the command of a DMA activation to a DMA controller 5. After the array table is set, the MPU 1 transmits the command of the activation of the DMA transfer in the array chain mode. Thus, the array table 4 is functioned as a means which applies the transfer information of the DMA transfer in the array chain mode. The DMA transfer is operated in the same way even when the number of transfer bites is not the multiple of the data length of the main bus 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data alignment method in a DMA transfer, and more particularly, in a DMA transfer between a storage device and an input / output device in a data processing device, a data transfer start address or a data transfer byte number is The present invention relates to a data alignment method for transferring data by effectively utilizing the data length of the main bus when it is not a multiple of the data length of the main bus.

[0002]

2. Description of the Related Art A microprocessor unit (hereinafter referred to as MPU) for executing arithmetic processing, a storage device for storing data necessary for arithmetic processing, an input / output device for inputting / outputting data necessary for arithmetic processing, In a processing device including a DMA controller that DMA-transfers data between a storage device and an input / output device, and a main bus that connects the above devices, DMA transfer is performed between the storage device and the input / output device. In this case, when the data transfer start address or the number of data transfer bytes is not a multiple of the data length of the main bus, conventionally, the transfer is performed by one of the following two transfer methods. The first transfer method is a method of transferring all the data to be transferred with the transfer start address of the data or the transfer byte number of the data and the transfer size which is the greatest common divisor of the data length of the main bus as the transfer unit. .. In the second transfer method, when the MPU issues a data transfer start command to the DMA controller, the transfer start address of the data to be transferred or the number of transfer bytes of the data is a multiple of the data length of the main bus and the greatest common divisor. In this method, the data is divided into a plurality of data, and the data transfer is performed by activating the DMA transfer a plurality of times for each of the plurality of divided data.

[0003]

In the DMA transfer in the conventional processor, the transfer technique performed when the transfer start address of data or the number of transfer bytes of data is not a multiple of the data length of the main bus is as follows. There's a problem. According to the first transfer method, when the number of data transfer bytes is large, the number of data transfer words in each of the DMA controller and the storage device is large, and the time required for the transfer is long. Specifically, for example,
If the data length of the main bus is 4 bytes, the greatest common divisor of the data transfer start address and the data length of the main bus is 1 byte, and the number of data transfer bytes is 1 kilobyte,
The number of data transfer words is 1 kiloword. Further, in the second transfer method, the DMA transfer must be activated a plurality of times, so that the MPU sends the DM to the DMA controller.
There is a problem that the time required to perform the start processing and the end processing of the A transfer becomes long. Specifically, for example, assume that the data length of the main bus is 4 bytes, the data transfer start address is the address $ 00100001, and the number of data transfer bytes is 1 kilobyte. At this time, when the transfer data is divided into a plurality of pieces such that the transfer start address of the data to be transferred is a multiple of the data length of the main bus and a multiple of the greatest common divisor, it is divided into three data blocks. Therefore, the MPU sends a D
The number of times the MA transfer activation process and the MA transfer process are executed is three. As described above, the DM between the storage device and the input / output device
In the case of performing A transfer, when the transfer start address of the data to be transferred or the number of transfer bytes of the data is not a multiple of the data length of the main bus, the conventional transfer method has a problem that it takes a long time to transfer the data. ..

An object of the present invention is to determine the data length of the main bus when the data transfer start address or the number of data transfer bytes is not a multiple of the data length of the main bus in the DMA transfer between the storage device and the input / output device. It is an object of the present invention to provide a data alignment method in DMA transfer, which is effectively used and is intended to shorten the processing time required for data transfer.

[0005]

A data alignment method in a DMA transfer according to the present invention includes an arithmetic unit for executing arithmetic processing, a storage unit for storing data necessary for arithmetic processing, and a data necessary for arithmetic processing. This is a method executed in a processing device including an input / output device for inputting / outputting, a DMA controller for DMA-transferring each data of the storage device and the input / output device, and a main bus connecting each component. The arithmetic unit performs the DMA transfer of a predetermined amount of data between the storage device and the input / output device, and when the transfer start address or the transfer byte number of the data is not a multiple of the data length of the main bus, The data is divided into a plurality of blocks such that the transfer start address or the number of transfer bytes is a multiple of the data length of the main bus and a multiple of the greatest common divisor, and the transfer start address, the number of transfer words, and the transfer for each of the plurality of blocks. Create an array table in which size transfer information is set, and send it to the DMA controller.
The DMA transfer in the array chain mode is executed.
A feature of the present invention is that not only the transfer start address and the number of transfer words but also the transfer size can be set in the array table which is the transfer information in the array chain mode.
Further, in the above method, the array table may be provided inside the DMA controller.

[0006]

According to the data alignment method in the DMA transfer according to the present invention, in the DMA transfer between the storage device and the input / output device, when the transfer start address of the data or the transfer byte number of the data is not a multiple of the data length of the main bus, The transfer data is divided into a plurality of data blocks so that the number of data transfer bytes is a multiple of the data length of the main bus, and an array table is created in which transfer information of each data block is written. In this array table, in addition to the transfer start address and the number of transfer words for each block, D
It is possible to set the transfer size for MA transfer. By including the transfer size in the transfer information, the number of transfer words can be reduced, and the number of times the arithmetic unit is activated by the DMA controller only needs to be one, and DMA transfer can be performed in a short time.

[0007]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the configuration of the data processing apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the processing device according to the present invention includes an MPU 1 for executing arithmetic processing, a storage device 2 for storing data necessary for arithmetic processing, an input / output device 3 for inputting / outputting data necessary for arithmetic processing, Array table 4 for setting required transfer information for each data block divided according to required conditions for storing data in storage device 2
And a DMA controller 5 that DMA-transfers data between the storage device 2 and the input / output device 3 based on the transfer information set in the array table 4, and a main bus 6 that connects the above devices. Has been done.

In the above processing device, for example, when a predetermined amount of data is DMA-transferred from the input / output device 3 to the storage device 2, the transfer start address of the data to be transferred is
If it is not a multiple of the data length of the main bus 6 (for example, 4 bytes), the MPU 1 sends the DMA controller 5 a DMA start command before the transfer start address is a multiple of the multiples of the data length of the main bus 6. The transfer data is divided into a plurality of blocks A, B, C, ... so as to be a multiple of the number, and the array table 4 in which the transfer start address, the transfer word number, and the transfer information of the transfer size are written is set for each block. The array table 4 shown in FIG. 1 shows an example in which the transfer head table, the number of transfer words, and the transfer size are respectively written in the blocks A, B, C ,. Then, after the array table is set, the MPU 1 issues a command to the DMA controller 5 to activate the DMA transfer in the array chain mode. Here, “array chain mode” means D
The MA controller 5 reads the transfer information set in the array table 4 into its own register 5a, and transfers data between the storage device 2 and the input / output device 3 according to the read transfer information in blocks A, B, and C. It is an operation mode that is executed sequentially in the order of. Array table 4
Functions as means for giving transfer information of the DMA transfer in the array chain mode. In addition, DM in FIG.
The contents of the mark "*" written in the register 5a inside the A controller 5 are loaded from the array table 4 in the array chain mode. The above-described DMA transfer operation is similarly performed when the number of data transfer bytes of the transfer data is not a multiple of the data length of the main bus 6.

FIG. 2 shows a specific setting example in the array table 4 in which the transfer start address, the transfer word number, and the transfer information of the transfer size are written for each of the blocks A, B, C, .... In this embodiment, the data length of the main bus 6 is 4 bytes, and the data transfer start address is $ 0010.
It is assumed that address 0001 and the number of data transfer bytes are 1 kilobyte. For example, regarding the blocks A, B, and C in the array table 4, in the block A, the data transfer start address is $ 00100001 and the number of data words is 3.
Word, transfer size is 1 byte, in block B, the transfer start address of data is $ 00100004, the number of data words is $ FF word, transfer size is 4 bytes, in block C, the transfer start address of data is $ 00100400, data The number of words is 1 and the transfer size is 1 byte.
The MPU 1 sets the above-mentioned array table 4 and DMA
When the controller 5 is activated, the blocks A,
Data transfer of B and C is executed.

As described above, in the transfer information of each block set in the array table 4, the transfer size can be set in addition to the transfer start address and the number of transfer words. Here, the "transfer size" is a data length that can be transferred in one bus cycle. For example, if the data length of the main bus is 4 bytes and the transfer start address is $ 00100.
Address 001 and transfer size of 4 bytes mean that addresses $ 00100001 to $ 00100004
It means that the data is written in one cycle of DMA. However, if the transfer size is 4 bytes in the storage device 2 because the address $ 00100001 is not a boundary, it is 1
Can't remember in cycles. Therefore, the transfer size is set to 1 byte. According to this, it is possible to write to the addresses $ 00100001 to $ 00100004 in 1 byte per cycle by DMA transfer.

As described above, in this embodiment, the transfer size can be set efficiently. As a result, in the DMA transfer between the storage device and the input / output device in the processing device, even if the transfer start address of the data or the transfer byte number of the data is not a multiple of the data length of the main bus, the number of transfer words is small and each DMA controller The data transfer can be performed only once.

Next, when data is transferred from the input / output device 3 to the storage device 2 based on the setting contents of the array table 4 shown in FIG. 2 and addresses are assigned, it becomes as shown in FIG. In the memory device 2, in the first transfer of the block A, addresses $ 00100001 to $ 0010 are transferred.
1 word transfer to address 0003 in 3 words (A-1, A in the figure)
-2, A-3), and in the next transfer of block B, addresses $ 00100004 to $ 0010.
4-byte transfer to address 03FF is $ FF word (B-1 in the figure
B to B-FF), and in the last transfer of the block C, one word (C-1) is transferred to the address $ 00100400.

Next, the processing in the array chain mode of the DMA transfer of each data of the data blocks A to C will be described with reference to FIG.
It will be described according to the flowchart of The MPU 1 sets the array table 4 in the configuration shown in FIG. 2 described above (step 11), and activates the DMA transfer of the array mode chain to the DMA controller 5 (step 12). As a result, the DMA controller 5 first
The block A in the array table 4 is read into its own register (step 13), and the data of the block A is transferred between the storage device 2 and the input / output device 3 according to the transfer information (step 14). The same operation as the above-mentioned operation regarding the block A is performed by the data of the block B (steps 15 and 16) and the data of the block C (step 17,
Continue to step 18). Finally, the MPU1 is DM
A termination process of the A controller 5 is executed (step 1
9).

As described above, the data length of the main bus 6 is 4
Data transfer start address in bytes is $ 001000
Even if the address is 01 and the data transfer byte count is 1 kilobyte, the data transfer can be performed with the transfer word count of $ 103 words by one activation of the DMA controller 5.

In the processing apparatus according to the above-mentioned embodiment, the array table 4 is constructed as an independent apparatus connected to the main bus 6. However, with this device configuration, DM
It is necessary for the A controller 5 to read the setting contents of the array table 4. Therefore, as the configuration of another embodiment, as shown in FIG.
It can also be configured as a register in the MA controller 21. With the configuration according to this embodiment, the time required for the DMA transfer can be further shortened.

[0016]

As is apparent from the above description, according to the present invention, in the DMA transfer between the storage device and the input / output device, the transfer start address and the transfer word number are stored in the array table which is the transfer information in the array chain mode. In addition to the above, since the transfer size is set, the transfer size can be set freely. Therefore, if the data transfer start address or the number of transfer bytes is not a multiple of the main bus data length, the data transfer start address or the number of transfer bytes should be a multiple of the main bus data length and a multiple of the greatest common divisor. The transfer data can be divided into a plurality of blocks, the transfer information of each block can be used to perform the DMA transfer of the data by one transfer start, and the transfer time can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of setting an array table.

FIG. 3 is a diagram showing an address allocation diagram of a storage device.

FIG. 4 is a diagram showing an allocation diagram in an array chain mode.

FIG. 5 is a configuration diagram of a processing device according to a second embodiment of the present invention.

[Explanation of symbols]

 1 MPU 2 storage device 3 input / output device 4,20 array table 5,21 DMA controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Yanokura HSP Building, 832 Horiguchi, Katsuta City, Ibaraki Prefecture Hitachi Measurement Engineering Co., Ltd.

Claims (3)

[Claims] 1. An arithmetic device for performing arithmetic processing, a storage device for storing data necessary for arithmetic processing, an input / output device for inputting / outputting data required for arithmetic processing, the storage device and the input / output device. In a processing device comprising a DMA controller for DMA-transferring each data item and a main bus connecting each of the constituent elements, the arithmetic device DMAs a predetermined amount of data between the storage device and the input / output device. When the transfer is performed and the transfer start address of the data is not a multiple of the data length of the main bus, the transfer start address of the data is a multiple of the data length of the main bus and a multiple of the greatest common divisor. In addition, the data is divided into a plurality of blocks, and the transfer start address, the number of transfer words, and transfer information of the transfer size are set for each of the plurality of blocks. A data alignment method in DMA transfer, characterized by creating a table and causing the DMA controller to execute a DMA transfer in an array chain mode. 2. An arithmetic device for executing arithmetic processing, a storage device for storing data necessary for arithmetic processing, an input / output device for inputting / outputting data necessary for arithmetic processing, the storage device and the input / output device. In a processing device comprising a DMA controller for DMA-transferring each data item and a main bus connecting each of the constituent elements, the arithmetic device DMAs a predetermined amount of data between the storage device and the input / output device. When performing the transfer and the number of transfer bytes of the data is not a multiple of the data length of the main bus, the number of transfer bytes of the data becomes a multiple of the data length of the main bus and a multiple of the greatest common divisor. An array table in which the data is divided into a plurality of blocks, and transfer information such as a transfer start address, the number of transfer words, and a transfer size is set for each of the plurality of blocks. A data alignment method in DMA transfer, which is created and causes the DMA controller to execute a DMA transfer in an array chain mode. 3. The data alignment method for DMA transfer according to claim 1, wherein the array table is provided inside the DMA controller.