JPS62217747A - Synchronization detecting device - Google Patents

Abstract

PURPOSE:To minimize the out of synchronism by providing a storage device for plural frames, a pattern detector and a majority decision logic circuit so as to recover a data of the frame even when a synchronizing signal is not correctly received. CONSTITUTION:A memory 1 is constituted to store information by 3 frames and extracting bits of a synchronizing pattern length by the frame length and pattern detectors 2-4 receive a data of a synchronizing pattern length extracted from the memory 1 as the address input. Then '1' is stored in the input data and outputted to a majority decision logic circuit 5, which outputs logical '1' in case two or over of three signals from the circuits 2-4 are logical '1' and the data are outputted via a synchronizing protection circuit 6. Through the provision of the circuit 5 above, even if the 1st frame synchronizing signal is not detected due to its error, for example, if the 2nd and 3rd synchronizing signals are received correctly, the first data synchronizing position is ensured. Thus, the data of the first frame is recovered to minimize the out of synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronization signal detection device for transmitting information by adding a frame synchronization signal.

[Technical background of the invention and its problems]

In a normal data transmission system, in order to detect or correct errors in data that occur during transmission, data is encoded in units of a certain amount of data (hereinafter abbreviated as frames), and then the data is transmitted. For this reason, it is important for the receiving side to accurately detect the starting point of the frame.For this purpose, the transmitting side prefixes the frame with a specific code pattern called a synchronization signal, and the receiving side A commonly used method is to set the point at which the pattern is detected as the starting point of the frame. There are two problems with this pattern detection method.
The first is due to an error that occurred during transmission. The synchronized turn changes and becomes undetectable. The second thing is.

This is a case where the same pattern as a synchronization pattern that happens to occur in data is mistakenly captured as a synchronization signal.

In either case, the synchronization will be out of order and data will not be received correctly. In order to avoid these two problems, a synchronization protection circuit is required. The conventionally used protection circuit is
For example, if the detection is not possible, a pseudo synchronization signal is output instead by counting the clock of the received data from the previous synchronization timing, and for the second error detection, the clock counter is used to calculate the time from the previous detection timing. Methods such as providing a detection window are used.

However, all of the above measures are taken after the synchronization state has been established, and are not effective for the first frame in which the synchronization state has not yet been established. Furthermore, once an out-of-synchronization state occurs, it takes several frames or more to recover, and data during this time cannot be received correctly.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned drawbacks of the prior art and to provide a means for recovering the data of a frame even if the synchronization signal is not correctly received and minimizing the out-of-synchronization condition. .

[Summary of the invention]

The present invention includes means for sequentially storing received codes and a plurality of synchronization pattern detection mechanisms at frame data length intervals to simultaneously detect synchronization timing of a plurality of frames,
This is a synchronization detection device that determines synchronization timing using majority logic.

[Effects of the Invention] According to the present invention, even if the first frame synchronization signal cannot be detected due to an error, if the second and third synchronization signals are correctly received, the synchronization position of the first data can be determined. This allows us to recover the first frame of data.

- [Embodiments of the Invention] The present invention will be explained in detail below with reference to FIGS. 1, 2, 3, and 4.

As shown in FIG. 1, this embodiment is applied to a high-density magnetic recording device that records information diagonally on a tape, such as a VTR. Characteristics of reproduced data from a magnetic recording device that performs such recording include a high data error rate and large time axis fluctuations (jitter). Furthermore, since there is a non-contact period between the head and the tape, the reproduced data becomes discontinuous from track to track, and frame synchronization must be re-established each time the head traces a new track.

Figure 2 is a functional block diagram of this embodiment. In this embodiment, synchronization patterns of three frame lengths are simultaneously detected, and the synchronization timing is defined as the point in time when two or more synchronization patterns are detected. It is configured so that In FIG. 2, numeral 1 denotes a memory that stores information for three frames, and is configured so that bits corresponding to the synchronization pattern length can be extracted based on the frame length. 2 to 4 are pattern detectors;
In this embodiment, ROM (read-only memory) is used to
Detection is performed using a lookup table method.

That is, input the synchronization pattern length data retrieved from the memory into the address input of the ROM, and store 1" in the data of the address that becomes the synchronization pattern. This detection is performed by R.
It can be constructed using an inverter and a gate without using an OM. 5 is a majority logic circuit, and pattern detection circuits 2 to 4
When two or more of the three signals from the circuit become "1", an output of 1' is generated. In this embodiment, an analog system is used and the configuration is as shown in FIG.

It should be noted that the comparison level is -'' x J'I P-.

A digital logic circuit is also possible. 6 is a cycle protection circuit similar to the conventional one, which is composed of a counter and a decoder circuit as shown in Fig. 4, and is used to generate false alarms when two or more synchronization patterns are erroneously generated and there is no cycle output at the timing when it should be output. This is a part that generates a synchronization window to prevent erroneous capture due to the occurrence of two or more synchronization patterns in the frame length in the data. Even if the synchronization signal of one frame is incorrect, the data of that frame can be recovered.

Furthermore, the implementation of the present invention is not limited to the above-mentioned embodiments, but generally has the versatility of relieving synchronization signal errors in up to n frames (m and n are integers) among m frames.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a recording and reproducing method on a tape of a magnetic recording device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the functions of the embodiment of the present invention, and FIG. 3 is a concrete configuration of a majority logic circuit. FIG. 4 is a diagram showing a specific configuration example of a synchronization protection circuit. 1...Memory 2-4...Pattern detector 5...Majority logic circuit 6...Synchronization protection circuit agent Patent attorney Nori Chika Yudo Kikuo Takehana

Claims (1)

[Claims] In a synchronization detection device that receives information obtained by adding a synchronization pattern to each frame and detects the synchronization pattern in the information, the synchronization detection device includes a storage device that stores the information of a plurality of frames, and the synchronization pattern of each stored frame. What is claimed is: 1. A synchronization detection device characterized by simultaneously comprising: and detection means.