JPH0646485B2 - Digital data recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention records synchronization information in data in an apparatus for serially storing data such as an optical disk, and recovers synchronization by this synchronization information during reproduction. The present invention relates to a digital data recording / reproducing device.

[Background of the Invention]

In a digital data recording / reproducing apparatus that encodes recording data by a variable word length encoding method and serially records it on a recording medium, in addition to the synchronization information indicating the beginning of the recording data, resynchronization information indicating a break in the middle of the data is provided. Insert and record, and at the time of playback, start decoding with the synchronization information at the beginning as a reference, and detect resynchronization information in the middle of the data if the decoder has a timing shift due to noise or some other cause during playback. Japanese Patent Laid-Open No. 58-161111 discloses a method of correcting the timing deviation and recovering the correct data. According to this method, the data error due to the timing shift does not propagate before the resynchronization information,
This is effective because it can prevent the whole data from being mistaken.

However, in the method disclosed in the publication, although the synchronization of the bid and the synchronization of the byte are recovered, it is not always guaranteed what number of data the recovered data corresponds to from the synchronization information at the head. When such a situation occurs, for example, when an error correction code is added beyond the range in which the resynchronization information is inserted, there is a problem in that the data arrangement becomes incorrect and uncorrectable or erroneous correction occurs. .

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data recording / reproducing apparatus that does not cause data and deviation even if the decoding timing is deviated due to noise or the like after detection of the leading synchronization information.

[Outline of Invention]

The present invention is characterized in that the second counter, which counts the number of pieces of data based on the synchronization information at the head, is corrected to a correct value for each resynchronization information, thereby preventing a data arrangement shift. is there.

Example of Invention

The present invention will be described below with reference to examples. This embodiment is a case where the present invention is applied to an optical disk memory device, and its sector format has an ID (Identifi) in which address information of each sector is recorded as shown in FIG.
(cation data) section 50, user data section 51, and gaps (GAP) 52 and 53.

As shown in FIG. 2, the user data section 51 includes a UFOSYNC for synchronizing a reproduction clock of a clock reproduction circuit (not shown) with a reproduction signal, synchronization information (SYNC) at the head, resynchronization information (RESYNC), and It consists of 1376 bytes of data.

According to this example, one block is composed of 32 bytes of data and 1 byte of RESYNC attached to this data.
There are 43 blocks in the sector. Note that this data structure is merely an example, and the present invention is not limited to this, and various format structures are conceivable.

FIG. 1 shows the circuit configuration of an embodiment of the present invention. In this embodiment, as the recording data coding method, Run Length Limited Variable Length C
oding; RLL) method is adopted.

In the figure, 20 is an RLL decoder, 21 is a SYNC detector, 22 is a RESYNC detector, 32 is a RESYNC gate generator,
23 is a data serial-to-parallel converter, 24 is an 8-minute cycle for generating a clock for each byte, 25 is a first counter for generating a carry for each 33-byte count, 26 is a clock for the carry of the first counter 25. As a second counter for counting 43 blocks, 27 is a serial-parallel converter 2
The data converted into parallel signals in 3 are counters 25, 26
Memory for storing at the address indicated by the output of 2
8 is a decoder, 29 is a data latch, 30 is an R gate, and 31 is an AND gate.

The serial reproduction data 1 reproduced from the optical disk (not shown) and the reproduction clock 2 generated by the clock reproduction circuit (not shown) so as to be synchronized with the reproduction data are the RLL decoder 20, the SYNC detector 21, and the RESYNC. It is input to the detector 22. Since the decode clock 4 corresponding to each bit of the decode data 3 has a frequency half that of the reproduced clock 2, it is obtained by dividing the reproduced clock 2 inside the RLL decoder 20. There are two types of phases,
In order to select the clock of the correct phase, SYNC signal 5
The RESYNC signal 6 is used.

In order to convert the decoded data 3 that is serial data into parallel data 8 by the data serial-parallel converter 23 and store the data in the semiconductor memory device 27 in byte units, the decode clock 4 to the 8 frequency divider 24 for each byte. Clock 7 is generated. In order to synchronize the byte clock 7 with the parallel data 8, the SYNC signal 5 and the RESYNC signal 6 are used.
The 8 divider 24 is reset. Counters 25 and 26 are 1
It is a counter that counts the number of data in a sector and is reset by a reset signal 11 at the head of each sector.

The counter 25 counts one block length, and 33 byte clocks 7 (RESYNC 1 byte + data 32
(Byte) Carry 9 is output for each count and returns to the initial value.
The counter 25 is also reset to the initial value by the RESYNC signal 6.

Normally, the cycle of the counter 25 and the cycle of RESYNC are the same, so the counter 25 performs a continuous counting operation.

The carry 9 is input to the counter 2 via the R gate 30 and advances the value of the counter 26 by 1. This counter 2
6 is for counting the blocks delimited by RESYNC in one sector, and in the case of this example, the carry 10 is output every 43 counts. This carry 10 is input to a system control unit (not shown) as a data end signal.

The SYNC detector 21 and the RESYNC detector 22 hold predetermined patterns in the SYNC detector 21 and RESYNC detector 22, respectively, and when these patterns match the pattern of the reproduction data, the SYNC detector And judge as RESYNC
To detect. Therefore, if one element of the SYNC pattern is set to the same pattern as the RESYNC pattern, the detection circuit can be shared.

Since the same RESYNC pattern appears in user data, the master clock 12 is generated by the RESYNC gate generator 32 based on the SYNC signal 5 or RESYNC signal 6.
Is counted to generate the RESYNC gate 13, and the RESYNC detector 22 detects only the RESYNC signal arriving while the RESYNC gate 13 is on, thereby preventing erroneous detection of RESYNC.

The operation at the timing correction by RESYNC will be described with reference to the time chart of FIG.

First, as shown in (a) of the figure, the RESYNC signal 6
However, if the count value 15 of the counter 25 is detected earlier than the reset value (o) by the byte clock 7, the counter 25 is reset to "0" by the RESYNC signal 6. On the other hand, the decoder 28 decodes the output value of the counter 25 with the decoder 28, and outputs "0
"15", "L", "16-32", "H"
Then, the data latch 29 latches the input signal level at a timing delayed by one clock from the byte clock 7 output from the 8 frequency divider 24. Therefore, RESY
When the NC signal 6 precedes the reset of the count value 15 of the counter 25 by the byte clock 7, the gate signal 1
4 is "H", and the RESYNC signals 6 and 17 that have passed through the AND gate 31 are supplied to the counter 26 via the OR gate 30 and advance the count value 16 by 1.

Conversely, as shown in FIG. 3 (b), the counter 25
When the RESYNC signal 6 is detected at the time when the count value of 15 is reset by the byte clock 7, the counter 25 has already become “0” in its own cycle, and the counter 26 is The carry value of 25 has already advanced the count value by 1. On the other hand, at this time, since the gate signal 14 is "L", the RESYNC signal 6 is blocked by the AND gate 31 and is not input to the counter 26. Therefore, the counter 26 is not counted up again by the RESYNC signal 6.

As described above, according to the present embodiment, the value of the counter 26 becomes a correct value regardless of where the RESYNC signal detection position is, so that the position of the block in one sector is stored without displacement on the memory address.

Therefore, even if the decoded data before the timing is corrected by the RESYNC signal is incorrect, the bit synchronization, byte synchronization, and block synchronization are all reproduced correctly after the correction. I can do it.

〔The invention's effect〕

According to the present invention, the decoding timing of the variable word length coding system is deviated due to the influence of noise after the detection of the head synchronization information,
Even if the bit synchronization, the byte synchronization, and the block synchronization are deviated, the resynchronization information detection has an effect that not only the bit synchronization and the byte synchronization but also the block synchronization is corrected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a format of a user data part, FIG. 3 is a time chart of signals of main parts of FIG. 1, and FIG. 4 is a sector format. 20 ... RLL decoder, 21 ... SYNC detector, 22 ... RESYNC detector, 24 ... 8 frequency divider, 25 ... lower counter, 26 ... upper counter, 27 ... semiconductor memory device, 28 ... Decoder, 29 ... Data latch, 30 ... OR gate, 31 ...
AND gate

Claims (2)

[Claims] 1. A block is composed of a predetermined number of data and re-synchronization information indicating a delimiter of data, a sector is composed of a plurality of blocks, and synchronization information is added to the head of the sector to perform recording on a recording medium. In the data recording / reproducing apparatus, synchronization information detecting means for detecting the beginning of a sector from the reproduction signal of the recording medium, re-synchronization information detecting means for detecting the delimiter of the data, demodulation means for demodulating the data, First counting means which is set to an initial value by a synchronization information detection signal and outputs a carry signal each time a predetermined number of data in a block delimited by the resynchronization information is counted and returns to the initial value; When the re-synchronization information is detected before the one counting means outputs the carry signal, the re-synchronization information detection signal is passed, and the re-synchronization information is output after the carry signal is output. Gate means for controlling the passage of the resynchronization information detection signal by the value of the first counting means so as to prevent passage of the resynchronization information detection signal when detected, and a carrier of the first counting means. Second counting means for counting the number of blocks by using the signal and the output signal of the gate means as a clock, the count value of the first counting means as a lower address, and the count value of the second counting means as an upper address And a storage means for storing demodulated data. 2. The second counting means counts the number of blocks divided by the resynchronization information in one sector, and outputs a data end signal when the predetermined number of blocks is reached. A digital data recording / reproducing apparatus according to claim 1.