JPH04117672A - Synchronizing method and synchronizing circuit for digital information signal - Google Patents

Abstract

PURPOSE:To obtain correct synchronism by adding an M number of synchronizing signals during a fixed period just before the leading block of a segment signal and starting an operation to get timing synchronism when an N number of synchronizing signals are detected from the reproduced or received segment signal. CONSTITUTION:Digital information signals are recorded or transmitted while adding the M (M is an integer >=2) number of synchronizing signals 2-6, for example, 5 synchronizing signals during the fixed period just before a leading block 9 of each segment signals as the segment signal composed of plural blocks respectively added with the synchronizing signals for timing synchronism. When the N (N is the integer of M>=N) number of synchronizing signals are detected from the segment signal, on the side of reproduction or reception, the operation to get the timing synchronism of the block 9 in the segment signal is started. Thus, when the new segment signal is inputted, correct timing synchronism can be obtained without being affected by block synchronism in the other segment signal.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a device for recording/reproducing, transmitting/receiving digital information signals, and particularly relates to a device for recording/reproducing, transmitting/receiving a digital information signal, and particularly for recording/reproducing a segment signal consisting of a plurality of blocks during reproduction or reception. This invention relates to a synchronization method for synchronizing the timing of blocks for data discrimination of digital information signals, and a synchronization circuit therefor.

(Prior art) Digital recording technology has been applied not only to various data signals but also to recording and reproducing devices such as audio information and image information, such as CD players, R-DAT, digital VT
It has been put into practical use as products such as R. In these digital recording and reproducing devices, a digital information signal is generally divided into multiple blocks and recorded on a recording medium as a unit consisting of multiple blocks to which a synchronization signal is added (this is called a segment signal). . on the other hand,
During reproduction, it is common to detect a synchronization signal for each block in a segment signal, and use this synchronization signal detection pulse to synchronize the timing of the blocks and perform data discrimination. This method is the same as the concept of pattern detection type frame synchronization in PCM transmission.

Figure M5 shows the structure of the above segment signal, in which a pit clock pull-in signal is placed at the beginning, followed by n-bit synchronization signals added to the beginning, respectively. Blocks of information signals are arranged. When reproducing such segment signals, a synchronization signal at the beginning of each block is detected, and this synchronization signal is used to synchronize the timing of the blocks, thereby ensuring correct data discrimination.

In such digital recording/playback devices, if an error occurs during the recording/playback process, it is not always possible to detect a synchronization signal, and a synchronization signal may be mistakenly detected where there should be no synchronization signal. There is a possibility. In order to prevent this, the timing synchronization of the blocks can be achieved as accurately as possible by applying protection by utilizing the fact that the original synchronization signals exist at temporally correlated positions.

FIG. 6 is a state transition diagram showing a synchronization algorithm for timing synchronization of the blocks described above.

A synchronizing signal is detected in the search mode, and when the synchronizing signal is detected, the mode shifts to the check mode, and it is checked whether the synchronizing signal is detected again after one block length. If the synchronizing signal is detected in the check mode, the mode shifts to the lock mode. , if not detected, returns to search mode. In the lock mode, it is checked whether a synchronizing signal is detected again after one block length, and if detected, the lock mode is maintained, and the checking is repeated to see if a synchronizing signal is detected after one block length. If no synchronizing signal is detected after one block length in lock mode, the mode shifts to one keep mode. In 1 keep mode, even though correlated synchronization signals are being played for each block, if the synchronization signal of the next block cannot be detected for some reason, that block will be lost. In order to prevent this, it is assumed that there is a synchronization signal one block length after the synchronization signal of the previous block.
Maintain block synchronization. Further, in the 1-keep mode, if a synchronizing signal is detected after one block length, the lock mode is returned to, but if no synchronization signal is detected, the mode shifts to the 2-keep mode. In the 2-keep mode F, as in the 1-keep mode, block synchronization is maintained on the assumption that the sync signal is detected at the position where the sync signal should originally be. If a synchronizing signal is detected after one block length, the lock mode is returned to. If no synchronizing signal is detected, block synchronization is canceled and the search mode is returned to.

In the synchronous mode where block timing synchronization is maintained in this way, if a synchronization signal is not detected at the expected position twice in a row, synchronization is maintained (this is called backward protection). call), and if it is not detected three times in a row, the synchronization is canceled and the mode is set to asynchronous mode.

Depending on how many keep modes are set, it is possible to determine the number of consecutive non-detections of a synchronous signal, which is a condition for setting an asynchronous mode.

However, the conventional synchronization method described above has the following problems.

When recording digital information signals on magnetic tape using a rotating head, such as R-DAT or digital VTR,
Since no signals are recorded on the magnetic tape over the entire circumference of the rotating drum, the reproduced digital information signal is an intermittent signal. FIG. 7 shows this situation, in which segment signals consisting of digital information signals made up of several blocks as shown in FIG. 5 are generated intermittently with certain time gaps. Timing diagrams when such segment signals are input to the synchronization circuit are shown in FIGS. 8 and 9.

FIG. 8(a) shows the first part of the segment signal, and the hatched part is the synchronization signal. Figure 8 (b
) is a synchronization signal detection pulse, and this detection pulse is (C
) is the synchronous mode while the wind pulse of (d) is captured, and the mode signal of (d) is at a high level.

Figure 9 (a) shows the last part of the segment signal, and even if the segment signal ends and the synchronization signal detection pulse shown in (b) is no longer obtained, the synchronization mode is maintained due to backward protection. .

For this reason, is the wind pulse in Figure 9(C) created?
Set number of consecutive times when the synchronization signal detection pulse is not captured by the wind pulse (in this case, "3")
, the mode setting becomes asynchronous mode, as shown in Figure 9 (
The mode signal of d) becomes low level.

FIG. 10 is a timing diagram when segment signals are input successively after a certain time gap as shown in FIG. 10(a). As explained in Fig. 9, the synchronization mode in the previous segment signal is maintained for a while due to backward protection, so in the next segment signal, the synchronization signal detection pulse in Fig. 10(b) is actually obtained from the synchronization signal. Instead of the detected pulse that was set, the detected pulse has the timing shown by the broken line, and correct synchronization cannot be obtained during this time. Backward protection is finished and the mode setting is asynchronous mode.
In other words, when the mode signal in FIG. 10(d) goes low, block synchronization is reestablished, and correct timing synchronization is obtained for this segment signal.

(Problem to be Solved by the Invention) As mentioned above, in the conventional synchronization method, even if one segment signal ends, the previous synchronization state is maintained for a while due to the set number of times of backward protection. Even though synchronization should be re-established immediately when a signal is input, there is a problem in that synchronization is established at the wrong timing while backward protection continues.

In addition, if the synchronization signal is incorrectly detected due to noise etc. in the time gap between segment signals, the synchronization mode will be entered incorrectly, so even after the segment signal is input, the timing may be incorrect. There also arises the problem that synchronization is lost.

Furthermore, in addition to equipment that uses a rotating head, in which the digital information signal is structurally reproduced intermittently, it is also possible to divide the digital information signal into segment signals due to the signal structure, such as a video signal portion and an audio signal portion. Even when a structure is adopted in which a no-signal portion called an edit gap is provided between each segment signal, the same problem as described above occurs.

The present invention was made to solve such problems, and when a new segment signal is input, the influence of block synchronization in other segment signals, erroneously detected synchronization signals, or pseudo It is an object of the present invention to provide a synchronization method and a synchronization circuit that can achieve correct timing synchronization using a synchronization signal added to a block within the segment signal without being affected by synchronization.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention converts a digital information signal into a segment signal consisting of a plurality of blocks to which synchronization signals for timing synchronization are respectively added.
M synchronization signals (M is an integer of 2 or more) are added to a certain period immediately before the first block of each segment signal and are recorded or transmitted. Then, on the reproduction or reception side, when N synchronization signals (N is an integer of M≧N) are detected from the segment signal, an operation for synchronizing the timing of the blocks in the segment signal is started.

Further, the synchronization circuit according to the present invention includes a means for detecting a synchronization signal from the segment signals, and a means for counting the number of synchronization signals detected by the means, and the count value is N (N+,
and means for starting an operation for synchronizing the timing of the program block in the segment signal when tM≧N>1 (an integer).

(Function) The fact that N (M≧N〉1) synchronization signals are successively detected from the segment signal means that one of the M synchronization signals added during a certain period immediately before the first block of the segment signal. This means that the area is detected. Therefore, when N synchronization signals are detected, for example, if you change the mode setting to asynchronous mode and start timing synchronization, the block will always be blocked using the synchronization signal added to the first block of the segment signal. The block timing synchronization operation can be started without being affected by block timing synchronization in other segment signals or by pseudo synchronization in edit gaps between segment signals.

Here, the reason why N is made larger than 1 is, of course, to distinguish it from the synchronization signal added to the beginning of the block. Also,
When a segment signal is input, it is not always the case that all M synchronization signals are detected due to an error or the like, so N may be set smaller than M if this is taken into consideration.

(Embodiment) FIG. 1 shows the structure of a segment signal in an embodiment of the present invention. As shown in the figure, this segment signal is set before the first block 9 of the digital information signal so that it is not continuous with the synchronization signal 8 (consisting of n bits) added to the beginning of the first block 9. A portion is provided in which five synchronization signals 2 to 6 are consecutively arranged in a concentrated manner.

Note that the synchronization signals 2 to 6 may not be arranged consecutively, but may be arranged at a certain interval. A pull-in signal 1 for bit clock reproduction is arranged before the concentrated arrangement portion of the synchronization signals 2 to 6. Synchronization signal group and first block 9
The signal 7 placed between the two may be any signal other than a synchronization signal, but considering the synchronization of the bit clock, it may be the same signal as the input signal 1 for bit clock reproduction. .

FIG. 2 is a block diagram showing the configuration of the synchronous circuit in this embodiment. Each element operates based on, for example, a reproduced output signal from a recording medium or a pit clock reproduced by a PLL circuit or the like from a signal received on the receiving side, but the bit clock reproduction system and supply system are omitted in the figure. It is.

In FIG. 2, an n-bit shift register 12, a synchronization signal detection section 13, a window generation section 14, a gate circuit 15,
The backward protection circuit 16, mode setting section 17, and data extraction section 18 are components of a general synchronous circuit, and the gate generation section 20, counting section 21, and OR circuit 22 are newly provided elements based on the present invention. It is.

The segment signal shown in FIG. 1 is input to the input terminal 11. This segment signal is, for example, a signal that is reproduced from a recording medium in a digital recording/reproducing device or received on the receiving side of a digital information transmitting/receiving system, and is serially taken into the n-bit shift register 12. The output of the n-bit shift register 12 is compared with the n-bit synchronization signal pattern stored in advance in the synchronization signal detection unit 13, and the bits corresponding to the n-bit synchronization signal pattern are compared with each other.
When all bits match, a synchronization signal detection pulse is output. The synchronization signal detection pulse is input to the window generation section 14 for generating a wind pulse, and is also supplied to the gate generation section 20 and the counting section 21.

When the synchronization signal detection pulse is input, the gate generation section 20 generates a gate pulse of a constant width and supplies it to the counting section 21 .

The counting section 21 counts the number of synchronizing signal detection pulses inputted while the gate pulse is being supplied, and outputs a reset pulse when the counted value reaches a set value (denoted as N). This reset pulse is input to the mode setting section 17 via the OR circuit 22, and the mode setting section 17 is reset to the asynchronous mode.

The reset pulse from the counting section 21 is also input to the window generation section 14 in order to cause the window generation section 14 to generate a wind pulse using the synchronization signal at the beginning of the block, and reset the window generation section 14. .

In this way, since the mode is always set to the asynchronous mode at the beginning of the segment signal, the timing synchronization operation of the block can be started from the synchronization signal 8 at the head of the block 9 detected first.

The synchronization signal detection pulse obtained when the synchronization signal detection unit 13 detects the synchronization signal at the beginning of the block is supplied to the window generation unit 14, which generates a window to check whether a synchronization signal is detected after the block length. A pulse is generated.

This wind pulse is supplied to the gate circuit 15, during which the gate circuit 15 is opened. If the synchronizing signal detection pulse is input to the gate circuit 15 at a timing one block length after the gate circuit 15 is open due to the wind pulse, the synchronizing signal detection pulse passes through the gate circuit 15 as it is and is input to the mode setting section 17. mode setting section 1
7 to the set state to set the synchronous mode. In the synchronous mode, the window generator 14 continues to generate wind pulses at regular intervals of one block length. The rear protection circuit 1-6 detects the case where the detection pulse of the synchronization signal is not captured by the wind pulse, and outputs a reset pulse when the detection pulse of the synchronization signal is not captured for a set number of consecutive pulses. This reset pulse is input to the mode setting section 17 via the OR circuit 22, and sets the mode setting section 17 to a reset state and to an asynchronous mode.

When the synchronization signal at the beginning of the block is detected by the synchronization signal detection unit 13, the synchronization signal detection pulse is generated by the gate generation unit 2.
0 and the counting unit 21, but since only one synchronization signal is added to the beginning of the block, the synchronization signal input while the gate pulse from the gate generation unit 20 is being supplied is detected. The number of pulses will never reach the set value N in the counting section 21.

On the other hand, the segment signal that has passed through the n-bit shift register 12 is input to the data extraction section 18. The data extraction unit 18 reads the data of the digital information signal included in each block of the segment signal and discriminates the data using the synchronization signal detection pulse that has passed through the gate circuit 15 when the mode signal from the mode setting unit 17 is in the synchronization mode. , and sends the discrimination results to the output terminal 19. This makes it possible to always discriminate data at the correct timing.

FIG. 3 is a timing diagram illustrating the operation of the gate generation section 20 and the counting section 21 for the first part of the segment signal, in which (a) is the first part of the segment signal shown in FIG. 1, and (b) is This is a synchronization signal detection pulse output from the synchronization signal detection section 13 in FIG. 2. FIG. 3(C) shows the gate generation unit 20 when the synchronization signal detection pulse is input.
In the case of the segment signal shown in FIG. 1, the pulse width is set to be slightly longer than five synchronizing signals. FIG. 3(d) shows a reset output from the counter 21 when a set value N (in this case, M-5" or less, for example, "4") is detected with a synchronization signal detection pulse between gate pulses. It's a pulse.

The gate pulse in FIG. 3(C) always opens for a certain period of time when there is a detection pulse of the synchronization signal, but the gate pulse is not supplied except for the concentrated arrangement of synchronization signals 2 to 6 set at the beginning of the segment signal. Since the number of synchronizing signal detection pulses input during this period never reaches the set value N, the reset pulses shown in FIG. 3(d) are not output.

FIG. 4 is a timing diagram illustrating a case where the segment signals shown in FIG. 1 are inputted successively after a certain time gap. FIG. 4(a) shows a segment signal, where the hatched part is a synchronization signal added to each block, and the cross-hatched part is a concentrated arrangement part of synchronization signals 2 to 6 set at the beginning of the segment signal. . Figure 4 (b
) are synchronization signal detection pulses, but the synchronization signal detection pulses obtained in the concentrated arrangement portion of the synchronization signals set at the beginning of the segment signal are omitted. As explained in Fig. 9, the synchronization mode in the previous segment signal is maintained for a while due to backward protection, so as shown in Fig. 4(e).
The mode signal is at a high level, that is, the mode setting is synchronous mode, but the reset pulse shown in FIG. The mode signal in FIG. 4(e) is at a low level, that is, the mode setting is the asynchronous mode. Therefore, since the wind pulse shown in FIG. 4(e) is generated from the synchronization signal of the first block of the segment signal, the timing synchronization of the blocks can be correctly achieved.

In this way, by concentrating and using the same synchronization signal as the block synchronization signal in the first part of the segment signal, the synchronization signal detection unit 13 can be used to detect the beginning part of the segment signal, and the synchronization signal for a certain period of time can be used. A gate generation unit 20 and a counting unit 2 for counting the number of synchronization signal detection pulses of
1 only needs to be added, and the circuit scale does not need to be increased.

In addition, in the above embodiment, the set value N in the counting section 21
The reason why is made smaller than the number M of centrally arranged synchronization signals is as follows.
This is because not all synchronization signals centrally arranged are necessarily detected due to errors or the like. The number M of synchronization signals to be centrally arranged and the set value N in the counting section 21 may be selected to be optimal values depending on the system.

[Effects of the Invention] As explained above, according to the present invention, it is possible to always start the synchronization operation from the beginning of a segment signal. The influence of false synchronization in time gaps or edit gaps between segment signals can be eliminated.

Furthermore, in the present invention, the segment signal has a format in which the same synchronization signals that are added to the block are concentrated at the beginning part, and when a predetermined number or more of the synchronization signals are consecutively detected, the timing synchronization operation of the block is started. Since this method does not use a special identification signal, there is no need to provide a special signal detection section, and the circuit configuration does not become complicated.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a segment signal according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a synchronous circuit according to the same embodiment, and FIGS. 3 and 4 are the same embodiment. 5 is a timing diagram showing a segment signal of a digital information signal consisting of a plurality of blocks to which conventional synchronization signals are respectively added. FIG. 6 is a state transition diagram showing a synchronization algorithm. , Fig. 7 is a timing diagram of a temporally intermittent reproduction signal, Figs. 8 and 9.
1 and 10 are timing diagrams for explaining the problems of the prior art. 1... Pull-in signals 2-6... Synchronous signal 13... Synchronous signal detection section 17... Mode setting section 18... Data discrimination section 19... Output terminal 20... Gate generation section 21... Counting section 22... OR circuit

Claims (2)

[Claims] (1) A digital information signal is treated as a segment signal consisting of a plurality of blocks to which a synchronization signal for timing synchronization is added, and M synchronization signals are transmitted in a certain period immediately before the first block of each segment signal (M is 2 or more). When N (N is an integer of M≧N>1) synchronization signals are detected from the segment signal that is added, recorded or transmitted, and played back or received, the timing synchronization of the blocks in the segment signal is performed. A method for synchronizing digital information signals, characterized in that the method starts an operation that takes a signal. (2) It consists of a plurality of blocks of digital information signals to which synchronization signals for timing synchronization are added, and M synchronization signals are transmitted in a certain period immediately before the first block (M is 2
means for detecting the synchronization signal from the added segment signal (an integer greater than or equal to ) for starting an operation for synchronizing the timing of blocks in the segment signal.