JPS62188536A - Line state display system - Google Patents

Abstract

PURPOSE:To improve the bus processing efficiency and the throughput of the equipment by adopting a constitution in which a line state data is written in a display control circuit and displayed on a display unit. CONSTITUTION:A line state supervisory means 18 supervising the state of a line accommodating a communication adaptor 100 based on the access from a panel adaptor 200 and a line state access means 25 accessing the line state supervisory means 18 by a line address corresponding to line and receiving the line state data via the means 18 are provided. Then the line state to the display unit 24 is displayed based on the line state data sent from the means 18 to the means 25. A main processor 3 applies control having only to control the operation start command of the communication adaptor 100 and the panel adaptor 200. Thus, the bus processing efficiency in the device and the throughout of the device are improved.

Description

[Detailed Description of the Invention] [Summary] ゛Data processing that performs data communication processing with a terminal or host device via each line accommodated in a communication adapter connected to a main processor and a panel adapter by an internal bus. This is a device line status display method in which the line status data to be displayed on the display unit inside the panel adapter is sent to the internal bus and then sent to the display unit via the main processor. By configuring the communication adapter to display line status data obtained by accessing it from the panel adapter under the control of the main processor, it is possible to improve bus processing efficiency and increase the throughput of the device.

[Industrial application field]

The present invention relates to a line status display method for a data processing device accommodating a plurality of lines.

2. Description of the Related Art Many systems have been put into practical use that perform data processing between data processing devices, terminal devices, etc. located at various locations through communication lines.

In such a system, it is required to constantly monitor the state of a communication line housed in a data processing device or the like, and to know whether data processing is being performed normally.

It is desired to put into practical use a method for easily and efficiently displaying the line status from the main processor in the device.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.

This block diagram shows the general configuration of a data processing device, and its configuration consists of a data processing system that accommodates multiple communication lines, data conversion for transferring data through each communication line, and a communication system that performs line control and line monitoring. Adapter 1 and panel adapter 2 that displays and controls the display so that the status of each communication line can be seen.
and a main processor 3 that controls various processing operations within the device, monitors them, controls transfer of data to and from the outside, and the like.

These communication adapters 1. The panel adapter 2 and the main processor 3 are connected by a bus (al), and the communication adapter 1.panel adapter 2.main processor 3 sends various data and signals to each other via the bus (a),
I have received it.

Therefore, these include the bus controller 17, which sends data and signals to the bus (a), and determines whether the data and signals sent to the bus (al) are addressed to the bus (al).
23.32 each.

Further, each of the functional blocks 1 to 3 is provided with a microprocessor (hereinafter referred to as MPU) 11, 21, and 31 for controlling the operation of the functions possessed by the functional blocks 1 to 3 based on a program.

Furthermore, the communication adapter l is connected to the MPUl1. a bus controller 17; a line unit control circuit 12 that controls each line unit 13 to 16 (however, in this example, the case where four lines ■ to ■ are accommodated is taken as an example, and the following explanations are the same); , Line units 13 to 16 that perform driver functions of the corresponding lines ■ to ■ and perform parallel/direct conversion of data and signals to be transferred, etc.
It is configured with the following.

Moreover, the panel adapter 2 also connects to the MPU 21. A display control circuit 22 that sets each line status data stored in the communication adapter 1 sent from the main processor 3 via the bus (a) and controls line status display on the display unit 24. and a display unit 24 that visually displays the line status such as the usage status of each line (1) to (2) accommodated in the communication adapter 1.

For example, when the line unit 13 is in use, the MPU II transmits the line use status data of the line unit 13, which has been confirmed by the line unit control circuit 12, to the main processor 3 via the bus controller 17 according to instructions from the main processor 3. is sent to bus (a) as the destination.

The main processor 3 confirms and receives the line usage status data sent to itself on the bus (a) using the bus controller 32, and then sends it to the bus (a) with the panel adapter 2 as the destination.
Send to.

The panel adapter 2 similarly checks and receives the line usage status data addressed to itself using the bus controller 23, and displays the usage status of the line ■ corresponding to the line unit 13 on the control circuit 2.
It is displayed under the control of 2.

[Problem that the invention seeks to solve]

As described above, conventionally, the main processor 3 instructs the communication adapter 1 to read line status data, and after the reading is completed, the line status data is sent to the panel adapter 2 via the bus (a).
The data is transferred to the main processor 3 via the main processor 3, and is instructed to be displayed on the display unit 24.

Therefore, there is a problem in that the load on the main processor 3 increases accordingly, the processing efficiency of the main processor 3 decreases, and the bus usage efficiency also decreases.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The block diagram of FIG. 1 shows the main processor 3 explained in FIG. 4, the functional blocks 11 to 17 explained in FIG. A communication adapter 100 is configured by adding a line status monitoring means (line status monitoring circuit) 18 that switches and transmits line status data using a corresponding line address, and functional blocks 21 to 24 explained in FIG. and the line status monitoring means (line status monitoring circuit) 18 to the line unit 13.
A line status access means (which transmits and accesses the line address corresponding to 16 to 16 and receives the corresponding line status data)
The panel adapter 200 is configured by adding a line status access circuit) 25.

[Effect]

The panel adapter is equipped with a line status monitoring means (line status monitoring circuit) that pulls in multiple line units and monitors the line status data of each line unit provided in the communication adapter under the control of the main processor. By accessing and receiving the line status data from the line status access means (line status access circuit) used to access the line, writing the line status data to the display control circuit, and displaying it on the display unit, the bus processing efficiency can be improved and the equipment can be improved. It becomes possible to increase throughput.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 to 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart in an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

The line status monitoring circuit 18 and line status access circuit 25 of this embodiment are constructed as shown in FIG.

That is, the line status monitoring circuit 18 Line status data with line status access circuit 25.

Based on the access address from the input/output interface circuit 181, which has a function of transferring addresses, control signals, etc., and the line status access circuit 25, one line status is determined from the line status data of the plurality of line units 13 to 16. Select data and input/output interface circuit 18
1 (hereinafter referred to as MPX) 1
82, and a line address latch circuit 183 that launches the access address from the line status access circuit 25 and sends it out as a control signal for the MPX1B2.

Further, the line status access circuit 25 is connected to the line units 13 to 1.
A line address register 251 that writes and holds the line address corresponding to 6 under the control of the MPU 21, a line status register 252 that writes and holds line status data from the communication adapter 100, and line status data, addresses, and control between the communication adapter 100 and an input/output interface circuit 253 having a function for transmitting signals and the like;
A line status clock generation circuit 254 generates a clock signal for operation timing of the input/output interface circuits 181 and 253 and the panel adapter bus response circuit 255, and when line status data is written to the line status register 252, a response signal is sent to the panel. The panel adapter bus response circuit 255 sends data to the adapter bus (b).

The processing speed of each functional block 21 to 25 in the panel adapter 200 depends on a system clock (shown in FIG. 3(1)) generated from a circuit not shown.

The timing at which the line address accessed by the line status access circuit 25 is written to the line address register 251 is also determined by
It is processed depending on the system clock.

That is, it is generated from the MPU 21, and the panel adapter bus (
The line address sent to bl is written during the sending of the panel adapter data strobe signal shown in FIG. 3(5).

When the line address is written to the line address register 251, the line address is written to the input/output interface circuit 253 according to the timing of the line status clock (shown in FIG. 3 (8)) generated by the line status clock generation circuit 254.
．． 181. MP via the line address latch circuit 183
Sent to X182.

MPX1B2 selects line units 13 to 16 corresponding to this line address, and selects line units 13 to 16 that correspond to this line address.
16 line status data to the input/output interface circuit 18
1.253 to the line status register 252,
A response signal to the line status data storage confirmation signal (panel adapter data acknowledge in FIG. 3(6)) from the MPU 21 to the line status register 252 is outputted from the panel adapter bus response circuit 255 for confirmation.

The line address and line status data are processed alternately using the line status clock generated by the line status clock generation circuit 254 as shown in FIG. 3(9). For details of these time charts, see (1) to (9) in Figure 3.
Shown below.

The line status data stored in the line status register 252 is set in the display control circuit 22 by the MPU 21 and displayed on the display unit 24 after being controlled by the display control circuit 22.

It should be noted that the main processor 3 in this embodiment only gives an instruction to start the operation of the communication adapter 100 and the panel adapter 200, and can perform other controls when the line address and line status data are inherited.

〔Effect of the invention〕

According to the present invention as described above, it is possible to improve the bus processing efficiency within the device and increase the throughput of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention, and FIG. 4 is a conventional block diagram. A block diagram illustrating an example is shown, respectively. In the figure, 1.100 is the communication adapter, 2.200 is the panel adapter, 3 is the main processor, 11, 21.31 is the MPtl
. 12 is a line unit control circuit; 13 to 16 are line units; 17, 23.32 are bus controllers; 18 is a line status monitoring circuit; 22 is a display control circuit; 24 is a display unit; 25 is a line status access circuit; 181. 253 is an input/output interface circuit, 182
is MPX. 183 is a line address launch circuit, 251 is a line address register, 252 is a line status register, 254 is a line status clock generation circuit, and 255 is a panel adapter bus response circuit.

Claims (1)

[Claims] A communication adapter (100) that accommodates a plurality of lines and controls each line, and a display unit (24), and displays the line status on the display unit (24). A panel adapter (200) to control and the communication adapter (1)
00) and the panel adapter (200) to the bus ((
a)) and a main processor (3) that controls data communication processing with a terminal or host device via each line accommodated in the communication adapter (100), a line status monitoring means (18) for monitoring the status of the line accommodated in the adapter (100) based on access from the panel adapter (200); ) and receives line status data via the line status monitoring unit (18), the line status accessing unit (25) accessing the line status monitoring unit (18) and receiving line status data via the line status monitoring unit (18). A line status display method characterized in that the line status is displayed on the display unit (24) based on the line status data sent to the line status data.